diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l.ll | 13 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll | 10 |
3 files changed, 1 insertions, 24 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 3d383b3dfe3..ba05b0f48df 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -3868,7 +3868,7 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, return std::make_pair(0U, nullptr); case 'l': // use the `lo` register to store values // that are no bigger than a word - if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) + if (VT == MVT::i32) return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); case 'x': // use the concatenated `hi` and `lo` registers diff --git a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l.ll b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l.ll deleted file mode 100644 index 1cd86d617a2..00000000000 --- a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l.ll +++ /dev/null @@ -1,13 +0,0 @@ -; Negative test. The constraint 'l' represents the register 'lo'. -; Check error message in case of invalid usage. -; -; RUN: not llc -march=mips -filetype=obj < %s 2>&1 | FileCheck %s - -define void @constraint_l() nounwind { -entry: - -; CHECK: error: invalid operand for instruction - - tail call i16 asm sideeffect "addiu $0,$1,$2", "=l,r,r,~{$1}"(i16 0, i16 0) - ret void -} diff --git a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll index b4c1587a8fb..63ee42c0c7c 100644 --- a/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll +++ b/llvm/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll @@ -41,15 +41,5 @@ entry: call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind store volatile i32 %4, i32* %bosco, align 4 -; Check the 'l' constraint for 16-bit type. -; CHECK: #APP -; CHECK: mtlo ${{[0-9]+}} -; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}} -; CHECK: #NO_APP -; CHECK-NEXT: mflo ${{[0-9]+}} - %bosco16 = alloca i16, align 4 - call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind - store volatile i16 %5, i16* %bosco16, align 4 - ret i32 0 } |
