diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fp16-v3.ll | 12 |
2 files changed, 13 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 5804dfeb57f..22ab8497f4c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -436,10 +436,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) { EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); SDLoc dl(N); - SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); - - return DAG.getNode(ISD::AssertZext, dl, - NVT, Res, DAG.getValueType(N->getValueType(0))); + return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); } SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { diff --git a/llvm/test/CodeGen/ARM/fp16-v3.ll b/llvm/test/CodeGen/ARM/fp16-v3.ll index 6ed9c9d22c9..182469d514e 100644 --- a/llvm/test/CodeGen/ARM/fp16-v3.ll +++ b/llvm/test/CodeGen/ARM/fp16-v3.ll @@ -25,4 +25,16 @@ define void @test_vec3(<3 x half>* %arr, i32 %i) #0 { ret void } +; CHECK-LABEL: test_bitcast: +; CHECK: vcvtb.f16.f32 +; CHECK: vcvtb.f16.f32 +; CHECK: vcvtb.f16.f32 +; CHECK: pkhbt +; CHECK: uxth +define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 { + %bc = bitcast <3 x half> %inp to <3 x i16> + store <3 x i16> %bc, <3 x i16>* %arr, align 8 + ret void +} + attributes #0 = { nounwind } |
