diff options
| -rw-r--r-- | llvm/test/CodeGen/X86/combine-shl.ll | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/combine-shl.ll b/llvm/test/CodeGen/X86/combine-shl.ll index 68c4ddffdf3..88a68b5a8b9 100644 --- a/llvm/test/CodeGen/X86/combine-shl.ll +++ b/llvm/test/CodeGen/X86/combine-shl.ll @@ -543,6 +543,42 @@ define <4 x i32> @combine_vec_shl_add1(<4 x i32> %x) { ret <4 x i32> %2 } +; FIXME: fold (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) +define <4 x i32> @combine_vec_shl_or0(<4 x i32> %x) { +; SSE-LABEL: combine_vec_shl_or0: +; SSE: # BB#0: +; SSE-NEXT: por {{.*}}(%rip), %xmm0 +; SSE-NEXT: pslld $2, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: combine_vec_shl_or0: +; AVX: # BB#0: +; AVX-NEXT: vpbroadcastd {{.*}}(%rip), %xmm1 +; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpslld $2, %xmm0, %xmm0 +; AVX-NEXT: retq + %1 = or <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5> + %2 = shl <4 x i32> %1, <i32 2, i32 2, i32 2, i32 2> + ret <4 x i32> %2 +} + +define <4 x i32> @combine_vec_shl_or1(<4 x i32> %x) { +; SSE-LABEL: combine_vec_shl_or1: +; SSE: # BB#0: +; SSE-NEXT: por {{.*}}(%rip), %xmm0 +; SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: combine_vec_shl_or1: +; AVX: # BB#0: +; AVX-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: retq + %1 = or <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8> + %2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4> + ret <4 x i32> %2 +} + ; fold (shl (mul x, c1), c2) -> (mul x, c1 << c2) define <4 x i32> @combine_vec_shl_mul0(<4 x i32> %x) { ; SSE-LABEL: combine_vec_shl_mul0: |
