diff options
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SPARC/select-mask.ll | 17 |
2 files changed, 25 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 1811631d6b3..9c8a0a64525 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1423,6 +1423,14 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM, : TargetLowering(TM), Subtarget(&STI) { MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize()); + // Instructions which use registers as conditionals examine all the + // bits (as does the pseudo SELECT_CC expansion). I don't think it + // matters much whether it's ZeroOrOneBooleanContent, or + // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the + // former. + setBooleanContents(ZeroOrOneBooleanContent); + setBooleanVectorContents(ZeroOrOneBooleanContent); + // Set up the register classes. addRegisterClass(MVT::i32, &SP::IntRegsRegClass); addRegisterClass(MVT::f32, &SP::FPRegsRegClass); diff --git a/llvm/test/CodeGen/SPARC/select-mask.ll b/llvm/test/CodeGen/SPARC/select-mask.ll new file mode 100644 index 00000000000..12e57103594 --- /dev/null +++ b/llvm/test/CodeGen/SPARC/select-mask.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=sparc < %s + +;; getBooleanContents on Sparc used to claim that no bits mattered +;; other than the first for SELECT. Thus, the 'trunc' got eliminated +;; as redundant. But, cmp does NOT ignore the other bits! + +; CHECK-LABEL select_mask: +; CHECK: ldub [%o0], [[R:%[goli][0-7]]] +; CHECK: and [[R]], 1, [[V:%[goli][0-7]]] +; CHECK: cmp [[V]], 0 +define i32 @select_mask(i8* %this) { +entry: + %bf.load2 = load i8, i8* %this, align 4 + %bf.cast5 = trunc i8 %bf.load2 to i1 + %cond = select i1 %bf.cast5, i32 2, i32 0 + ret i32 %cond +} |
