diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrVFP.td | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/fp16-instructions.ll | 40 |
3 files changed, 42 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 0c9f615d888..e86e5bce2b6 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1048,6 +1048,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::SELECT, MVT::i32, Custom); setOperationAction(ISD::SELECT, MVT::f32, Custom); setOperationAction(ISD::SELECT, MVT::f64, Custom); + setOperationAction(ISD::SELECT_CC, MVT::f16, Custom); setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 9efc4f9c343..8731a7fdce9 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -451,9 +451,9 @@ multiclass vsel_inst<string op, bits<2> opc, int CC> { let DecoderNamespace = "VFPV8", PostEncoderMethod = "", Uses = [CPSR], AddedComplexity = 4 in { def H : AHbInp<0b11100, opc, 0, - (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), + (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"), - []>, + [(set HPR:$Sd, (ARMcmov HPR:$Sm, HPR:$Sn, CC))]>, Requires<[HasFullFP16]>; def S : ASbInp<0b11100, opc, 0, diff --git a/llvm/test/CodeGen/ARM/fp16-instructions.ll b/llvm/test/CodeGen/ARM/fp16-instructions.ll index 75a11a53199..3aef5fc60fd 100644 --- a/llvm/test/CodeGen/ARM/fp16-instructions.ll +++ b/llvm/test/CodeGen/ARM/fp16-instructions.ll @@ -687,6 +687,7 @@ entry: ; CHECK-HARDFP-FULLFP16: vnmul.f16 s0, s0, s1 } +; TODO: ; 28. VRINTA ; 29. VRINTM ; 30. VRINTN @@ -694,11 +695,48 @@ entry: ; 32. VRINTR ; 33. VRINTX ; 34. VRINTZ + ; 35. VSELEQ +define half @select_cc1() { + %1 = fcmp nsz oeq half undef, 0xH0001 + %2 = select i1 %1, half 0xHC000, half 0xH0002 + ret half %2 + +; CHECK-LABEL: select_cc1: +; CHECK-HARDFP-FULLFP16: vseleq.f16 s0, s{{.}}, s{{.}} +} + ; 36. VSELGE +define half @select_cc2() { + %1 = fcmp nsz oge half undef, 0xH0001 + %2 = select i1 %1, half 0xHC000, half 0xH0002 + ret half %2 + +; CHECK-LABEL: select_cc2: +; CHECK-HARDFP-FULLFP16: vselge.f16 s0, s{{.}}, s{{.}} +} + ; 37. VSELGT +define half @select_cc3() { + %1 = fcmp nsz ogt half undef, 0xH0001 + %2 = select i1 %1, half 0xHC000, half 0xH0002 + ret half %2 + +; CHECK-LABEL: select_cc3: +; CHECK-HARDFP-FULLFP16: vselgt.f16 s0, s{{.}}, s{{.}} +} + ; 38. VSELVS -; 39. VSQRT +define half @select_cc4() { + %1 = fcmp nsz ueq half undef, 0xH0001 + %2 = select i1 %1, half 0xHC000, half 0xH0002 + ret half %2 + +; CHECK-LABEL: select_cc4: +; CHECK-HARDFP-FULLFP16: vselvs.f16 s0, s{{.}}, s{{.}} +} + +; 39. VSQRT - TODO ; 40. VSUB define float @Sub(float %a.coerce, float %b.coerce) { |
