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-rw-r--r--llvm/include/llvm/CodeGen/MachineInstr.h3
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp9
-rw-r--r--llvm/lib/CodeGen/TargetInstrInfo.cpp14
-rw-r--r--llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp4
-rw-r--r--llvm/lib/Target/X86/X86FloatingPoint.cpp3
-rw-r--r--llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir2
6 files changed, 29 insertions, 6 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 635c1482bd3..6aeb411c862 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -1124,7 +1124,8 @@ public:
/// Replace all occurrences of FromReg with ToReg:SubIdx,
/// properly composing subreg indices where necessary.
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
- const TargetRegisterInfo &RegInfo);
+ const TargetRegisterInfo &RegInfo,
+ bool ClearIsRenamable = false);
/// We have determined MI kills a register. Look for the
/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 32785dee0cb..d2d3bc77ac4 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -928,10 +928,10 @@ void MachineInstr::clearKillInfo() {
}
}
-void MachineInstr::substituteRegister(unsigned FromReg,
- unsigned ToReg,
+void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
unsigned SubIdx,
- const TargetRegisterInfo &RegInfo) {
+ const TargetRegisterInfo &RegInfo,
+ bool ClearIsRenamable) {
if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
if (SubIdx)
ToReg = RegInfo.getSubReg(ToReg, SubIdx);
@@ -939,8 +939,11 @@ void MachineInstr::substituteRegister(unsigned FromReg,
if (!MO.isReg() || MO.getReg() != FromReg)
continue;
MO.substPhysReg(ToReg, RegInfo);
+ if (ClearIsRenamable)
+ MO.setIsRenamable(false);
}
} else {
+ assert(!ClearIsRenamable && "IsRenamable invalid for virtual registers");
for (MachineOperand &MO : operands()) {
if (!MO.isReg() || MO.getReg() != FromReg)
continue;
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index bd90ed5b55b..963f8178b50 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -174,6 +174,14 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();
bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
+ // Avoid calling isRenamable for virtual registers since we assert that
+ // renamable property is only queried/set for physical registers.
+ bool Reg1IsRenamable = TargetRegisterInfo::isPhysicalRegister(Reg1)
+ ? MI.getOperand(Idx1).isRenamable()
+ : false;
+ bool Reg2IsRenamable = TargetRegisterInfo::isPhysicalRegister(Reg2)
+ ? MI.getOperand(Idx2).isRenamable()
+ : false;
// If destination is tied to either of the commuted source register, then
// it must be updated.
if (HasDef && Reg0 == Reg1 &&
@@ -211,6 +219,12 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
CommutedMI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
+ // Avoid calling setIsRenamable for virtual registers since we assert that
+ // renamable property is only queried/set for physical registers.
+ if (TargetRegisterInfo::isPhysicalRegister(Reg1))
+ CommutedMI->getOperand(Idx2).setIsRenamable(Reg1IsRenamable);
+ if (TargetRegisterInfo::isPhysicalRegister(Reg2))
+ CommutedMI->getOperand(Idx1).setIsRenamable(Reg2IsRenamable);
return CommutedMI;
}
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
index 2dc6f2702b3..e77c98a72cf 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
@@ -246,6 +246,7 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst);
PrepareExecInst->getOperand(0).setReg(AMDGPU::EXEC);
+ PrepareExecInst->getOperand(0).setIsRenamable(false);
DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n');
@@ -352,7 +353,8 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) {
for (MachineInstr *OtherInst : OtherUseInsts) {
OtherInst->substituteRegister(CopyToExec, AMDGPU::EXEC,
- AMDGPU::NoSubRegister, *TRI);
+ AMDGPU::NoSubRegister, *TRI,
+ /*ClearIsRenamable=*/true);
}
}
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index 9a72e7114be..6a13367e3ce 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -1383,6 +1383,7 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
// Change from the pseudo instruction to the concrete instruction.
MI.getOperand(0).setReg(getSTReg(Op1));
+ MI.getOperand(0).setIsRenamable(false);
MI.RemoveOperand(1);
MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
@@ -1410,6 +1411,7 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
MI.RemoveOperand(0);
MI.RemoveOperand(1);
MI.getOperand(0).setReg(getSTReg(Op1));
+ MI.getOperand(0).setIsRenamable(false);
MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
// If we kill the second operand, make sure to pop it from the stack.
@@ -1626,6 +1628,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
else
// Operand with a single register class constraint ("t" or "u").
Op.setReg(X86::ST0 + FPReg);
+ Op.setIsRenamable(false);
}
// Simulate the inline asm popping its inputs and pushing its outputs.
diff --git a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
index 85ce251ac31..9939fa61820 100644
--- a/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
+++ b/llvm/test/CodeGen/Mips/sll-micromips-r6-encoding.mir
@@ -40,7 +40,7 @@ stack:
constants:
body: |
bb.0.entry:
- renamable %zero = SLL_MMR6 killed renamable %zero, 0
+ %zero = SLL_MMR6 killed %zero, 0
JRC16_MM undef %ra, implicit %v0
...
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