diff options
| -rw-r--r-- | llvm/include/llvm/IR/IntrinsicsPowerPC.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx-elementary-arith.ll | 31 |
3 files changed, 43 insertions, 0 deletions
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index 05adc5a757b..630f89a0bdd 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -694,6 +694,12 @@ def int_ppc_vsx_xvrspip : def int_ppc_vsx_xvrdpip : Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>; +// Vector rsqrte +def int_ppc_vsx_xvrsqrtesp : GCCBuiltin<"__builtin_vsx_xvrsqrtesp">, + Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>; +def int_ppc_vsx_xvrsqrtedp : GCCBuiltin<"__builtin_vsx_xvrsqrtedp">, + Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>; + // Vector compare def int_ppc_vsx_xvcmpeqdp : PowerPC_VSX_Intrinsic<"xvcmpeqdp", [llvm_v2i64_ty], diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 43ba4994fde..3cb67deacbf 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -989,6 +989,12 @@ def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B), def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B), (XVDIVDP $A, $B)>; +// Recip. square root estimate +def : Pat<(int_ppc_vsx_xvrsqrtesp v4f32:$A), + (XVRSQRTESP $A)>; +def : Pat<(int_ppc_vsx_xvrsqrtedp v2f64:$A), + (XVRSQRTEDP $A)>; + } // AddedComplexity } // HasVSX diff --git a/llvm/test/CodeGen/PowerPC/vsx-elementary-arith.ll b/llvm/test/CodeGen/PowerPC/vsx-elementary-arith.ll index d8f76bb989e..5416f667aef 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-elementary-arith.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-elementary-arith.ll @@ -116,5 +116,36 @@ entry: ; CHECK: xssqrtdp {{[0-9]+}} } +; Vector forms +; Function Attrs: nounwind +define <4 x float> @emit_xvrsqrtesp() { +entry: +; CHECK-LABEL: @emit_xvrsqrtesp + %vf = alloca <4 x float>, align 16 + %vfr = alloca <4 x float>, align 16 + %0 = load <4 x float>, <4 x float>* %vf, align 16 + %call = call <4 x float> @llvm.ppc.vsx.xvrsqrtesp(<4 x float> %0) +; CHECK: xvrsqrtesp {{[0-9]+}}, {{[0-9]+}} + ret <4 x float> %call +} + +; Function Attrs: nounwind +define <2 x double> @emit_xvrsqrtedp() { +entry: +; CHECK-LABEL: @emit_xvrsqrtedp + %vd = alloca <2 x double>, align 16 + %vdr = alloca <2 x double>, align 16 + %0 = load <2 x double>, <2 x double>* %vd, align 16 + %call = call <2 x double> @llvm.ppc.vsx.xvrsqrtedp(<2 x double> %0) + ret <2 x double> %call +; CHECK: xvrsqrtedp {{[0-9]+}}, {{[0-9]+}} +} + ; Function Attrs: nounwind declare double @sqrt(double) + +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.ppc.vsx.xvrsqrtesp(<4 x float>) + +; Function Attrs: nounwind readnone +declare <2 x double> @llvm.ppc.vsx.xvrsqrtedp(<2 x double>) |
