diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/setcc.ll | 20 |
2 files changed, 21 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index eb417e5b15b..104b909c4e8 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -103,6 +103,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM, setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); + setOperationAction(ISD::SETCC, MVT::i1, Promote); setOperationAction(ISD::SETCC, MVT::v2i1, Expand); setOperationAction(ISD::SETCC, MVT::v4i1, Expand); diff --git a/llvm/test/CodeGen/AMDGPU/setcc.ll b/llvm/test/CodeGen/AMDGPU/setcc.ll index 430989faf9b..47eb76da546 100644 --- a/llvm/test/CodeGen/AMDGPU/setcc.ll +++ b/llvm/test/CodeGen/AMDGPU/setcc.ll @@ -389,3 +389,23 @@ if: endif: ret void } + +; FUNC-LABEL: setcc-i1-and-xor +; SI-DAG: v_cmp_le_f32_e64 [[A:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}} +; SI-DAG: v_cmp_ge_f32_e64 [[B:s\[[0-9]+:[0-9]+\]]], 1.0, s{{[0-9]+}} +; SI: s_and_b64 s[2:3], [[A]], [[B]] +define void @setcc-i1-and-xor(i32 addrspace(1)* %out, float %cond) #0 { +bb0: + %tmp5 = fcmp oge float %cond, 0.000000e+00 + %tmp7 = fcmp ole float %cond, 1.000000e+00 + %tmp9 = and i1 %tmp5, %tmp7 + %tmp11 = xor i1 %tmp9, 1 + br i1 %tmp11, label %bb2, label %bb1 + +bb1: + store i32 0, i32 addrspace(1)* %out + br label %bb2 + +bb2: + ret void +} |
