diff options
12 files changed, 43 insertions, 456 deletions
diff --git a/llvm/docs/GlobalISel.rst b/llvm/docs/GlobalISel.rst index fd247a534f6..176bd4edea3 100644 --- a/llvm/docs/GlobalISel.rst +++ b/llvm/docs/GlobalISel.rst @@ -358,41 +358,6 @@ existing patterns (as any pattern we can select is by definition legal). Expanding that to describe legalization actions is a much larger but potentially useful project. -.. _milegalizer-scalar-narrow: - -Scalar narrow types -^^^^^^^^^^^^^^^^^^^ - -In the AArch64 port, we currently mark as legal operations on narrow integer -types that have a legal equivalent in a wider type. - -For example, this: - - %2(GPR,s8) = G_ADD %0, %1 - -is selected to a 32-bit instruction: - - %2(GPR32) = ADDWrr %0, %1 - -This avoids unnecessarily legalizing operations that can be seen as legal: -8-bit additions are supported, but happen to have a 32-bit result with the high -24 bits undefined. - -``TODO``: -This has implications regarding vreg classes (as narrow values can now be -represented by wider vregs) and should be investigated further. - -``TODO``: -In particular, s1 comparison results can be represented as wider values in -different ways. -SelectionDAG has the notion of BooleanContents, which allows targets to choose -what true and false are when in a larger register: - -* ``ZeroOrOne`` --- if only 0 and 1 are valid bools, even in a larger register. -* ``ZeroOrMinusOne`` --- if -1 is true (common for vector instructions, - where compares produce -1). -* ``Undefined`` --- if only the low bit is relevant in determining truth. - .. _milegalizer-non-power-of-2: Non-power of 2 types diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 3163f6e5228..dea651631bd 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -119,7 +119,7 @@ static bool unsupportedBinOp(const MachineInstr &I, } /// Select the AArch64 opcode for the basic binary operation \p GenericOpc -/// (such as G_OR or G_ADD), appropriate for the register bank \p RegBankID +/// (such as G_OR or G_SDIV), appropriate for the register bank \p RegBankID /// and of size \p OpSize. /// \returns \p GenericOpc if the combination is unsupported. static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, @@ -140,9 +140,6 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, return AArch64::EORWrr; case TargetOpcode::G_AND: return AArch64::ANDWrr; - case TargetOpcode::G_ADD: - assert(OpSize != 32 && "s32 G_ADD should have been selected"); - return AArch64::ADDWrr; case TargetOpcode::G_SUB: return AArch64::SUBWrr; case TargetOpcode::G_SHL: @@ -759,7 +756,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { case TargetOpcode::G_ASHR: case TargetOpcode::G_SDIV: case TargetOpcode::G_UDIV: - case TargetOpcode::G_ADD: case TargetOpcode::G_SUB: case TargetOpcode::G_GEP: { // Reject the various things we don't support yet. diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp index dad390b752c..985260700e3 100644 --- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -39,8 +39,11 @@ AArch64LegalizerInfo::AArch64LegalizerInfo() { for (auto BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, G_SHL}) { // These operations naturally get the right answer when used on // GPR32, even if the actual type is narrower. - for (auto Ty : {s1, s8, s16, s32, s64, v2s32, v4s32, v2s64}) + for (auto Ty : {s32, s64, v2s32, v4s32, v2s64}) setAction({BinOp, Ty}, Legal); + + for (auto Ty : {s1, s8, s16}) + setAction({BinOp, Ty}, WidenScalar); } setAction({G_GEP, p0}, Legal); @@ -148,6 +151,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo() { setAction({G_UITOFP, 1, Ty}, Legal); } for (auto Ty : { s1, s8, s16 }) { + // FIXME: These should be widened on types smaller than s32. setAction({G_FPTOSI, 0, Ty}, Legal); setAction({G_FPTOUI, 0, Ty}, Legal); setAction({G_SITOFP, 1, Ty}, WidenScalar); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index 9c7b73052a3..eb7827fd74b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -8,34 +8,22 @@ --- | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" - define void @add_s8_gpr() { ret void } - define void @add_s16_gpr() { ret void } define void @add_s32_gpr() { ret void } define void @add_s64_gpr() { ret void } - define void @sub_s8_gpr() { ret void } - define void @sub_s16_gpr() { ret void } define void @sub_s32_gpr() { ret void } define void @sub_s64_gpr() { ret void } - define void @or_s1_gpr() { ret void } - define void @or_s16_gpr() { ret void } define void @or_s32_gpr() { ret void } define void @or_s64_gpr() { ret void } define void @or_v2s32_fpr() { ret void } - define void @xor_s8_gpr() { ret void } - define void @xor_s16_gpr() { ret void } define void @xor_s32_gpr() { ret void } define void @xor_s64_gpr() { ret void } - define void @and_s8_gpr() { ret void } - define void @and_s16_gpr() { ret void } define void @and_s32_gpr() { ret void } define void @and_s64_gpr() { ret void } - define void @shl_s8_gpr() { ret void } - define void @shl_s16_gpr() { ret void } define void @shl_s32_gpr() { ret void } define void @shl_s64_gpr() { ret void } @@ -45,8 +33,6 @@ define void @ashr_s32_gpr() { ret void } define void @ashr_s64_gpr() { ret void } - define void @mul_s8_gpr() { ret void } - define void @mul_s16_gpr() { ret void } define void @mul_s32_gpr() { ret void } define void @mul_s64_gpr() { ret void } @@ -157,62 +143,6 @@ ... --- -# CHECK-LABEL: name: add_s8_gpr -name: add_s8_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ADDWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s8) = COPY %w0 - %1(s8) = COPY %w1 - %2(s8) = G_ADD %0, %1 -... - ---- -# CHECK-LABEL: name: add_s16_gpr -name: add_s16_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ADDWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s16) = COPY %w0 - %1(s16) = COPY %w1 - %2(s16) = G_ADD %0, %1 -... - ---- # Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32. # Also check that we constrain the register class of the COPY to GPR32. # CHECK-LABEL: name: add_s32_gpr @@ -272,62 +202,6 @@ body: | ... --- -# CHECK-LABEL: name: sub_s8_gpr -name: sub_s8_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = SUBWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s8) = COPY %w0 - %1(s8) = COPY %w1 - %2(s8) = G_SUB %0, %1 -... - ---- -# CHECK-LABEL: name: sub_s16_gpr -name: sub_s16_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = SUBWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s16) = COPY %w0 - %1(s16) = COPY %w1 - %2(s16) = G_SUB %0, %1 -... - ---- # Same as add_s32_gpr, for G_SUB operations. # CHECK-LABEL: name: sub_s32_gpr name: sub_s32_gpr @@ -386,62 +260,6 @@ body: | ... --- -# CHECK-LABEL: name: or_s1_gpr -name: or_s1_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ORRWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s1) = COPY %w0 - %1(s1) = COPY %w1 - %2(s1) = G_OR %0, %1 -... - ---- -# CHECK-LABEL: name: or_s16_gpr -name: or_s16_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ORRWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s16) = COPY %w0 - %1(s16) = COPY %w1 - %2(s16) = G_OR %0, %1 -... - ---- # Same as add_s32_gpr, for G_OR operations. # CHECK-LABEL: name: or_s32_gpr name: or_s32_gpr @@ -531,62 +349,6 @@ body: | ... --- -# CHECK-LABEL: name: xor_s8_gpr -name: xor_s8_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = EORWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s8) = COPY %w0 - %1(s8) = COPY %w1 - %2(s8) = G_XOR %0, %1 -... - ---- -# CHECK-LABEL: name: xor_s16_gpr -name: xor_s16_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = EORWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s16) = COPY %w0 - %1(s16) = COPY %w1 - %2(s16) = G_XOR %0, %1 -... - ---- # Same as add_s32_gpr, for G_XOR operations. # CHECK-LABEL: name: xor_s32_gpr name: xor_s32_gpr @@ -645,62 +407,6 @@ body: | ... --- -# CHECK-LABEL: name: and_s8_gpr -name: and_s8_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ANDWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s8) = COPY %w0 - %1(s8) = COPY %w1 - %2(s8) = G_AND %0, %1 -... - ---- -# CHECK-LABEL: name: and_s16_gpr -name: and_s16_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ANDWrr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s16) = COPY %w0 - %1(s16) = COPY %w1 - %2(s16) = G_AND %0, %1 -... - ---- # Same as add_s32_gpr, for G_AND operations. # CHECK-LABEL: name: and_s32_gpr name: and_s32_gpr @@ -759,62 +465,6 @@ body: | ... --- -# CHECK-LABEL: name: shl_s8_gpr -name: shl_s8_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = LSLVWr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s8) = COPY %w0 - %1(s8) = COPY %w1 - %2(s8) = G_SHL %0, %1 -... - ---- -# CHECK-LABEL: name: shl_s16_gpr -name: shl_s16_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = LSLVWr %0, %1 -body: | - bb.0: - liveins: %w0, %w1 - - %0(s16) = COPY %w0 - %1(s16) = COPY %w1 - %2(s16) = G_SHL %0, %1 -... - ---- # Same as add_s32_gpr, for G_SHL operations. # CHECK-LABEL: name: shl_s32_gpr name: shl_s32_gpr @@ -989,62 +639,6 @@ body: | ... --- -# CHECK-LABEL: name: mul_s8_gpr -name: mul_s8_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = MADDWrrr %0, %1, %wzr -body: | - bb.0: - liveins: %w0, %w1 - - %0(s8) = COPY %w0 - %1(s8) = COPY %w1 - %2(s8) = G_MUL %0, %1 -... - ---- -# CHECK-LABEL: name: mul_s16_gpr -name: mul_s16_gpr -legalized: true -regBankSelected: true - -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32 } -# CHECK-NEXT: - { id: 1, class: gpr32 } -# CHECK-NEXT: - { id: 2, class: gpr32 } -registers: - - { id: 0, class: gpr } - - { id: 1, class: gpr } - - { id: 2, class: gpr } - -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = MADDWrrr %0, %1, %wzr -body: | - bb.0: - liveins: %w0, %w1 - - %0(s16) = COPY %w0 - %1(s16) = COPY %w1 - %2(s16) = G_MUL %0, %1 -... - ---- # Check that we select s32 GPR G_MUL. This is trickier than other binops because # there is only MADDWrrr, and we have to use the WZR physreg. # CHECK-LABEL: name: mul_s32_gpr diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir index 252e60c6b2e..679c6b4788f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir @@ -69,7 +69,10 @@ body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_add_small - ; CHECK: [[RES:%.*]](s8) = G_ADD %2, %3 + ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) + ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) + ; CHECK: [[RES32:%.*]](s32) = G_ADD [[OP0]], [[OP1]] + ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) %0(s64) = COPY %x0 %1(s64) = COPY %x1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir index 69459bfacb0..cdd885cb673 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir @@ -22,7 +22,10 @@ body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_and_small - ; CHECK: %4(s8) = G_AND %2, %3 + ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) + ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) + ; CHECK: [[RES32:%.*]](s32) = G_AND [[OP0]], [[OP1]] + ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) %0(s64) = COPY %x0 %1(s64) = COPY %x1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir index eb642d4b1a7..e56eef0bc4f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir @@ -22,7 +22,10 @@ body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_mul_small - ; CHECK: %4(s8) = G_MUL %2, %3 + ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) + ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) + ; CHECK: [[RES32:%.*]](s32) = G_MUL [[OP0]], [[OP1]] + ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) %0(s64) = COPY %x0 %1(s64) = COPY %x1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir index edf10cd411e..802d8ad1989 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir @@ -22,7 +22,10 @@ body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_or_small - ; CHECK: %4(s8) = G_OR %2, %3 + ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) + ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) + ; CHECK: [[RES32:%.*]](s32) = G_OR [[OP0]], [[OP1]] + ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) %0(s64) = COPY %x0 %1(s64) = COPY %x1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir index e77f3487609..bd8cdf4f1ae 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir @@ -45,8 +45,15 @@ body: | ; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %7 ; CHECK: [[QUOT32:%[0-9]+]](s32) = G_SDIV [[LHS32]], [[RHS32]] ; CHECK: [[QUOT:%[0-9]+]](s8) = G_TRUNC [[QUOT32]] - ; CHECK: [[PROD:%[0-9]+]](s8) = G_MUL [[QUOT]], %7 - ; CHECK: [[RES:%[0-9]+]](s8) = G_SUB %6, [[PROD]] + + ; CHECK: [[QUOT32_2:%.*]](s32) = G_ANYEXT [[QUOT]](s8) + ; CHECK: [[RHS32_2:%.*]](s32) = G_ANYEXT %7(s8) + ; CHECK: [[PROD32:%.*]](s32) = G_MUL [[QUOT32_2]], [[RHS32_2]] + ; CHECK: [[PROD:%.*]](s8) = G_TRUNC [[PROD32]](s32) + + ; CHECK: [[LHS32_2:%.*]](s32) = G_ANYEXT %6(s8) + ; CHECK: [[PROD32_2:%.*]](s32) = G_ANYEXT [[PROD]](s8) + ; CHECK: [[RES:%[0-9]+]](s32) = G_SUB [[LHS32_2]], [[PROD32_2]] %6(s8) = G_TRUNC %0 %7(s8) = G_TRUNC %1 %8(s8) = G_SREM %6, %7 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir index 673b23562ff..5d95c5ee2d8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir @@ -39,6 +39,9 @@ body: | ; CHECK: %5(s8) = G_TRUNC [[RES32]] %5(s8) = G_LSHR %2, %3 - ; CHECK: %6(s8) = G_SHL %2, %3 + ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) + ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) + ; CHECK: [[RES32:%.*]](s32) = G_SHL [[OP0]], [[OP1]] + ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) %6(s8) = G_SHL %2, %3 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir index e5403cb73c3..6652d2b4d7a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir @@ -22,7 +22,10 @@ body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_sub_small - ; CHECK: [[RES:%.*]](s8) = G_SUB %2, %3 + ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) + ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) + ; CHECK: [[RES32:%.*]](s32) = G_SUB [[OP0]], [[OP1]] + ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) %0(s64) = COPY %x0 %1(s64) = COPY %x1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir index 919e674965c..a2f3c8ea3b1 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir @@ -22,7 +22,10 @@ body: | bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_xor_small - ; CHECK: %4(s8) = G_XOR %2, %3 + ; CHECK: [[OP0:%.*]](s32) = G_ANYEXT %2(s8) + ; CHECK: [[OP1:%.*]](s32) = G_ANYEXT %3(s8) + ; CHECK: [[RES32:%.*]](s32) = G_XOR [[OP0]], [[OP1]] + ; CHECK: [[RES:%.*]](s8) = G_TRUNC [[RES32]](s32) %0(s64) = COPY %x0 %1(s64) = COPY %x1 |
