diff options
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZInstrFP.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/fp-move-01.ll | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/fp-move-12.ll | 33 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/vec-sub-01.ll | 2 |
5 files changed, 40 insertions, 3 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFP.td b/llvm/lib/Target/SystemZ/SystemZInstrFP.td index 0cb267290cc..82dccd3878b 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFP.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFP.td @@ -37,6 +37,10 @@ let hasSideEffects = 0 in { def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>; def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>; def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>; + + // For z13 we prefer LDR over LER to avoid partial register dependencies. + let isCodeGenOnly = 1 in + def LDR32 : UnaryRR<"ld", 0x28, null_frag, FP32, FP32>; } // Moves between two floating-point registers that also set the condition diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index 39c43739e1c..8dadd017770 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -572,7 +572,8 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB, if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg)) Opcode = SystemZ::LGR; else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg)) - Opcode = SystemZ::LER; + // For z13 we prefer LDR over LER to avoid partial register dependencies. + Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER; else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg)) Opcode = SystemZ::LDR; else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg)) diff --git a/llvm/test/CodeGen/SystemZ/fp-move-01.ll b/llvm/test/CodeGen/SystemZ/fp-move-01.ll index 843b1b6a6e6..55c09e5d779 100644 --- a/llvm/test/CodeGen/SystemZ/fp-move-01.ll +++ b/llvm/test/CodeGen/SystemZ/fp-move-01.ll @@ -1,7 +1,6 @@ ; Test moves between FPRs. ; ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s ; Test f32 moves. define float @f1(float %a, float %b) { diff --git a/llvm/test/CodeGen/SystemZ/fp-move-12.ll b/llvm/test/CodeGen/SystemZ/fp-move-12.ll new file mode 100644 index 00000000000..131f7c374ca --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/fp-move-12.ll @@ -0,0 +1,33 @@ +; Test moves between FPRs on z13. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s + +; Test that we use LDR instead of LER. +define float @f1(float %a, float %b) { +; CHECK-LABEL: f1: +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + ret float %b +} + +; Test f64 moves. +define double @f2(double %a, double %b) { +; CHECK-LABEL: f2: +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + ret double %b +} + +; Test f128 moves. Since f128s are passed by reference, we need to force +; a copy by other means. +define void @f3(fp128 *%x) { +; CHECK-LABEL: f3: +; CHECK: lxr +; CHECK: axbr +; CHECK: br %r14 + %val = load volatile fp128 , fp128 *%x + %sum = fadd fp128 %val, %val + store volatile fp128 %sum, fp128 *%x + store volatile fp128 %val, fp128 *%x + ret void +} diff --git a/llvm/test/CodeGen/SystemZ/vec-sub-01.ll b/llvm/test/CodeGen/SystemZ/vec-sub-01.ll index 4afad8bef65..9829bd02433 100644 --- a/llvm/test/CodeGen/SystemZ/vec-sub-01.ll +++ b/llvm/test/CodeGen/SystemZ/vec-sub-01.ll @@ -52,7 +52,7 @@ define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) { ; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v[[A2]], 2 ; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v[[A1]], 3 ; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v[[A2]], 3 -; CHECK-DAG: ler %f[[A1copy:[0-5]]], %f[[A1]] +; CHECK-DAG: ldr %f[[A1copy:[0-5]]], %f[[A1]] ; CHECK-DAG: sebr %f[[A1copy]], %f[[A2]] ; CHECK-DAG: sebr %f[[B1]], %f[[B2]] ; CHECK-DAG: sebr %f[[C1]], %f[[C2]] |
