diff options
| -rw-r--r-- | llvm/lib/CodeGen/LowerSubregs.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll | 34 |
2 files changed, 42 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/LowerSubregs.cpp b/llvm/lib/CodeGen/LowerSubregs.cpp index 9c23a5ac155..e9e60a00f0e 100644 --- a/llvm/lib/CodeGen/LowerSubregs.cpp +++ b/llvm/lib/CodeGen/LowerSubregs.cpp @@ -254,7 +254,13 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { // Insert sub-register copy const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); + if (MI->getOperand(2).isUndef()) + // If the source register being inserted is undef, then this becomes an + // implicit_def. + BuildMI(*MBB, MI, MI->getDebugLoc(), + TII.get(TargetInstrInfo::IMPLICIT_DEF), DstSubReg); + else + TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); MachineBasicBlock::iterator CopyMI = MI; --CopyMI; @@ -270,7 +276,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { } // Make sure the inserted register gets killed - if (MI->getOperand(2).isKill()) + if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef()) TransferKillFlag(MI, InsReg, TRI); } diff --git a/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll b/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll new file mode 100644 index 00000000000..f2a2729a5b7 --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll @@ -0,0 +1,34 @@ +; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mattr=+neon,+neonfp +; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mattr=+neon,+neonfp | grep fcpys | count 1 +; rdar://7117307 + + %struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List } + %struct.List = type { %struct.List*, %struct.Patient*, %struct.List* } + %struct.Patient = type { i32, i32, i32, %struct.Village* } + %struct.Results = type { float, float, float } + %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } + +define arm_apcscc void @get_results(%struct.Results* noalias nocapture sret %agg.result, %struct.Village* %village) nounwind { +entry: + br i1 undef, label %bb, label %bb6.preheader + +bb6.preheader: ; preds = %entry + call void @llvm.memcpy.i32(i8* undef, i8* undef, i32 12, i32 4) + br i1 undef, label %bb15, label %bb13 + +bb: ; preds = %entry + ret void + +bb13: ; preds = %bb13, %bb6.preheader + %0 = fadd float undef, undef ; <float> [#uses=1] + %1 = fadd float undef, 1.000000e+00 ; <float> [#uses=1] + br i1 undef, label %bb15, label %bb13 + +bb15: ; preds = %bb13, %bb6.preheader + %r1.0.0.lcssa = phi float [ 0.000000e+00, %bb6.preheader ], [ %1, %bb13 ] ; <float> [#uses=1] + %r1.1.0.lcssa = phi float [ undef, %bb6.preheader ], [ %0, %bb13 ] ; <float> [#uses=0] + store float %r1.0.0.lcssa, float* undef, align 4 + ret void +} + +declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind |
