diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/amdpal.ll | 29 |
2 files changed, 2 insertions, 33 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 84cde4bafeb..a3f107b10fc 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -405,7 +405,7 @@ void SIFrameLowering::emitEntryFunctionScratchSetup(const SISubtarget &ST, .addReg(ScratchRsrcReg, RegState::ImplicitDefine); // We now have the GIT ptr - now get the scratch descriptor from the entry - // at offset 0 (or offset 16 for a compute shader). + // at offset 0. PointerType *PtrTy = PointerType::get(Type::getInt64Ty(MF.getFunction().getContext()), AMDGPUAS::CONSTANT_ADDRESS); @@ -416,11 +416,9 @@ void SIFrameLowering::emitEntryFunctionScratchSetup(const SISubtarget &ST, MachineMemOperand::MOInvariant | MachineMemOperand::MODereferenceable, 0, 0); - unsigned Offset - = MF.getFunction().getCallingConv() == CallingConv::AMDGPU_CS ? 16 : 0; BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg) .addReg(Rsrc01) - .addImm(Offset) // offset + .addImm(0) // offset .addImm(0) // glc .addReg(ScratchRsrcReg, RegState::ImplicitDefine) .addMemOperand(MMO); diff --git a/llvm/test/CodeGen/AMDGPU/amdpal.ll b/llvm/test/CodeGen/AMDGPU/amdpal.ll index 8d4c09cdeaf..c8f37fbe0b3 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal.ll @@ -52,36 +52,7 @@ entry: ret void } -; Check code sequence for amdpal use of scratch for alloca in a compute shader. -; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset -; 0 in a graphics shader. - -; PAL-LABEL: {{^}}scratch2_cs: -; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234 -; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0 -; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:{{[0-9]+\]}}, 0x10 -; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]: - -define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 { -entry: - %v = alloca [3 x i32], addrspace(5) - %v0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 0 - %v1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 1 - store i32 %extra, i32 addrspace(5)* %v0 - %v1a = bitcast i32 addrspace(5)* %v1 to [2 x i32] addrspace(5)* - %vv = bitcast [2 x i32] addrspace(5)* %v1a to <2 x i32> addrspace(5)* - store <2 x i32> %in, <2 x i32> addrspace(5)* %vv - %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v1a, i32 0, i32 %idx - %x = load i32, i32 addrspace(5)* %e - %xf = bitcast i32 %x to float - call void @llvm.amdgcn.buffer.store.f32(float %xf, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0) - ret void -} - attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" } -declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) - - ; Check we have CS_NUM_USED_VGPRS in PAL metadata. ; PAL: .amd_amdgpu_pal_metadata {{.*}},0x10000027, |
