diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/pr37820.ll | 25 |
2 files changed, 28 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 3d835266b90..ee767c0fd03 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -8688,8 +8688,9 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { if (ShiftMask.isMask()) { EVT MaskedVT = EVT::getIntegerVT(*DAG.getContext(), ShiftMask.countTrailingOnes()); - // Recompute the type. - if (TLI.isLoadExtLegal(ExtType, N0.getValueType(), MaskedVT)) + // If the mask is smaller, recompute the type. + if ((ExtVT.getSizeInBits() > MaskedVT.getSizeInBits()) && + TLI.isLoadExtLegal(ExtType, N0.getValueType(), MaskedVT)) ExtVT = MaskedVT; } } diff --git a/llvm/test/CodeGen/X86/pr37820.ll b/llvm/test/CodeGen/X86/pr37820.ll new file mode 100644 index 00000000000..1eff3394682 --- /dev/null +++ b/llvm/test/CodeGen/X86/pr37820.ll @@ -0,0 +1,25 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s + +@a = external dso_local local_unnamed_addr global i64, align 8 +@c = external dso_local local_unnamed_addr global i64, align 8 +@b = external dso_local local_unnamed_addr global i64, align 8 + +; Should generate a 16-bit load + +define void @foo() { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movzwl a+{{.*}}(%rip), %eax +; CHECK-NEXT: movq %rax, {{.*}}(%rip) +; CHECK-NEXT: retq +entry: + %0 = load i64, i64* @a, align 8 + %1 = load i64, i64* @c, align 8 + %and = and i64 %1, -16384 + %add = add nsw i64 %and, 4503359447364223024 + %shr = lshr i64 %0, %add + %conv1 = and i64 %shr, 4294967295 + store i64 %conv1, i64* @b, align 8 + ret void +} |
