diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir | 15 |
2 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp index af6505c9862..53bf4ba1dc5 100644 --- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -89,6 +89,8 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { setAction({G_SELECT, 1, s1}, Legal); setAction({G_CONSTANT, s32}, Legal); + for (auto Ty : {s1, s8, s16}) + setAction({G_CONSTANT, Ty}, WidenScalar); setAction({G_ICMP, s1}, Legal); for (auto Ty : {s8, s16}) diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir index bf759728c36..d66a16e6c2a 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir @@ -689,11 +689,26 @@ selected: false tracksRegLiveness: true registers: - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } body: | bb.0: %0(s32) = G_CONSTANT 42 ; CHECK: {{%[0-9]+}}(s32) = G_CONSTANT 42 + %1(s16) = G_CONSTANT i16 21 + ; CHECK: [[EXT:%[0-9]+]](s32) = G_CONSTANT i32 21 + ; CHECK: {{%[0-9]+}}(s16) = G_TRUNC [[EXT]](s32) + + %2(s8) = G_CONSTANT i8 10 + ; CHECK: [[EXT:%[0-9]+]](s32) = G_CONSTANT i32 10 + ; CHECK: {{%[0-9]+}}(s8) = G_TRUNC [[EXT]](s32) + + %3(s1) = G_CONSTANT i1 1 + ; CHECK: [[EXT:%[0-9]+]](s32) = G_CONSTANT i32 -1 + ; CHECK: {{%[0-9]+}}(s1) = G_TRUNC [[EXT]](s32) + %r0 = COPY %0(s32) BX_RET 14, _, implicit %r0 ... |
