diff options
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/dpp_combine.mir | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine.mir index 76a2082cfc2..9c3841cba11 100644 --- a/llvm/test/CodeGen/AMDGPU/dpp_combine.mir +++ b/llvm/test/CodeGen/AMDGPU/dpp_combine.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=gcn-dpp-combine -o - %s | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=gcn-dpp-combine -verify-machineinstrs -o - %s | FileCheck %s --- # old is undefined: only combine when masks are fully enabled and @@ -530,22 +530,24 @@ body: | # Test instruction which does not have modifiers in VOP1 form but does in DPP form. # CHECK-LABEL: name: dpp_vop1 -# CHECK: %3:vgpr_32 = V_CEIL_F32_dpp %1:vgpr_32, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $exec +# CHECK: %3:vgpr_32 = V_CEIL_F32_dpp %0, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $exec name: dpp_vop1 tracksRegLiveness: true body: | bb.0: - %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec + %1:vgpr_32 = IMPLICIT_DEF + %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $exec ... # Test instruction which does not have modifiers in VOP2 form but does in DPP form. # CHECK-LABEL: name: dpp_min -# CHECK: %3:vgpr_32 = V_MIN_F32_dpp %1:vgpr_32, 0, undef %2:vgpr_32, 0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $exec +# CHECK: %3:vgpr_32 = V_MIN_F32_dpp %0, 0, undef %2:vgpr_32, 0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $exec name: dpp_min tracksRegLiveness: true body: | bb.0: - %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec + %1:vgpr_32 = IMPLICIT_DEF + %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec %4:vgpr_32 = V_MIN_F32_e32 %2, undef %3:vgpr_32, implicit $exec ... |
