diff options
| -rw-r--r-- | llvm/test/CodeGen/ARM/vcvt_combine.ll | 103 |
1 files changed, 36 insertions, 67 deletions
diff --git a/llvm/test/CodeGen/ARM/vcvt_combine.ll b/llvm/test/CodeGen/ARM/vcvt_combine.ll index 0c856e8d761..9a8f084d230 100644 --- a/llvm/test/CodeGen/ARM/vcvt_combine.ll +++ b/llvm/test/CodeGen/ARM/vcvt_combine.ll @@ -1,95 +1,64 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s -@in = global float 0x400921FA00000000, align 4 - ; Test signed conversion. -; CHECK: t0 -; CHECK-NOT: vmul -define void @t0() nounwind { -entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 - %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00> +; CHECK-LABEL: @t0 +; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #2 +; CHECK: bx lr +define <2 x i32> @t0(<2 x float> %in) { + %mul.i = fmul <2 x float> %in, <float 4.0, float 4.0> %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> - tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind - ret void + ret <2 x i32> %vcvt.i } -declare void @foo_int32x2_t(<2 x i32>) - ; Test unsigned conversion. -; CHECK: t1 -; CHECK-NOT: vmul -define void @t1() nounwind { -entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 - %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00> +; CHECK-LABEL: @t1 +; CHECK: vcvt.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #3 +; CHECK: bx lr +define <2 x i32> @t1(<2 x float> %in) { + %mul.i = fmul <2 x float> %in, <float 8.0, float 8.0> %vcvt.i = fptoui <2 x float> %mul.i to <2 x i32> - tail call void @foo_uint32x2_t(<2 x i32> %vcvt.i) nounwind - ret void + ret <2 x i32> %vcvt.i } -declare void @foo_uint32x2_t(<2 x i32>) - ; Test which should not fold due to non-power of 2. -; CHECK: t2 +; CHECK-LABEL: @t2 ; CHECK: vmul -define void @t2() nounwind { +; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}} +; CHECK: bx lr +define <2 x i32> @t2(<2 x float> %in) { entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 - %mul.i = fmul <2 x float> %vecinit2.i, <float 0x401B333340000000, float 0x401B333340000000> + %mul.i = fmul <2 x float> %in, <float 0x401B333340000000, float 0x401B333340000000> %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> - tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind - ret void + ret <2 x i32> %vcvt.i } ; Test which should not fold due to power of 2 out of range. -; CHECK: t3 +; CHECK-LABEL: @t3 ; CHECK: vmul -define void @t3() nounwind { -entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 - %mul.i = fmul <2 x float> %vecinit2.i, <float 0x4200000000000000, float 0x4200000000000000> +; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}} +; CHECK: bx lr +define <2 x i32> @t3(<2 x float> %in) { + %mul.i = fmul <2 x float> %in, <float 0x4200000000000000, float 0x4200000000000000> %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> - tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind - ret void + ret <2 x i32> %vcvt.i } ; Test which case where const is max power of 2 (i.e., 2^32). -; CHECK: t4 -; CHECK-NOT: vmul -define void @t4() nounwind { -entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 - %mul.i = fmul <2 x float> %vecinit2.i, <float 0x41F0000000000000, float 0x41F0000000000000> +; CHECK-LABEL: @t4 +; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #32 +; CHECK: bx lr +define <2 x i32> @t4(<2 x float> %in) { + %mul.i = fmul <2 x float> %in, <float 0x41F0000000000000, float 0x41F0000000000000> %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> - tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind - ret void + ret <2 x i32> %vcvt.i } ; Test quadword. -; CHECK: t5 -; CHECK-NOT: vmul -define void @t5() nounwind { -entry: - %tmp = load float, float* @in, align 4 - %vecinit.i = insertelement <4 x float> undef, float %tmp, i32 0 - %vecinit2.i = insertelement <4 x float> %vecinit.i, float %tmp, i32 1 - %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %tmp, i32 2 - %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %tmp, i32 3 - %mul.i = fmul <4 x float> %vecinit6.i, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00> +; CHECK-LABEL: @t5 +; CHECK: vcvt.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}, #3 +; CHECK: bx lr +define <4 x i32> @t5(<4 x float> %in) { + %mul.i = fmul <4 x float> %in, <float 8.0, float 8.0, float 8.0, float 8.0> %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32> - tail call void @foo_int32x4_t(<4 x i32> %vcvt.i) nounwind - ret void + ret <4 x i32> %vcvt.i } - -declare void @foo_int32x4_t(<4 x i32>) |
