summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--llvm/lib/Target/RISCV/RISCVFrameLowering.cpp55
-rw-r--r--llvm/test/CodeGen/RISCV/exception-pointer-register.ll10
-rw-r--r--llvm/test/CodeGen/RISCV/frame-info.ll52
-rw-r--r--llvm/test/CodeGen/RISCV/large-stack.ll15
-rw-r--r--llvm/test/CodeGen/RISCV/split-offsets.ll4
-rw-r--r--llvm/test/CodeGen/RISCV/vararg.ll22
-rw-r--r--llvm/test/DebugInfo/RISCV/relax-debug-frame.ll5
7 files changed, 2 insertions, 161 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 1aef67f90a6..4ba4606612b 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -233,8 +233,6 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
}
}
-// FIXME Fix emission of .cfi_restore and .cfi_def_cfa CFI directives that can
-// incorrectly affect subsequent basic blocks.
void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
@@ -242,7 +240,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
MachineFrameInfo &MFI = MF.getFrameInfo();
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
DebugLoc DL = MBBI->getDebugLoc();
- const RISCVInstrInfo *TII = STI.getInstrInfo();
Register FPReg = getFPReg(STI);
Register SPReg = getSPReg(STI);
@@ -271,51 +268,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,
MachineInstr::FrameDestroy);
-
- // Emit ".cfi_def_cfa_offset FirstSPAdjustAmount" if using an sp-based CFA
- if (!hasFP(MF)) {
- unsigned CFIIndex = MF.addFrameInst(
- MCCFIInstruction::createDefCfaOffset(nullptr, -FirstSPAdjustAmount));
- BuildMI(MBB, LastFrameDestroy, DL,
- TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
- }
- }
-
- if (hasFP(MF)) {
- // To find the instruction restoring FP from stack.
- for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
- if (I->mayLoad() && I->getOperand(0).isReg()) {
- Register DestReg = I->getOperand(0).getReg();
- if (DestReg == FPReg) {
- // If there is frame pointer, after restoring $fp registers, we
- // need adjust CFA back to the correct sp-based offset.
- // Emit ".cfi_def_cfa $sp, CFAOffset"
- uint64_t CFAOffset =
- FirstSPAdjustAmount
- ? -FirstSPAdjustAmount + RVFI->getVarArgsSaveSize()
- : -FPOffset;
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
- nullptr, RI->getDwarfRegNum(SPReg, true), CFAOffset));
- BuildMI(MBB, std::next(I), DL,
- TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
- break;
- }
- }
- }
- }
-
- // Add CFI directives for callee-saved registers.
- const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
- // Iterate over list of callee-saved registers and emit .cfi_restore
- // directives.
- for (const auto &Entry : CSI) {
- Register Reg = Entry.getReg();
- unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
- nullptr, RI->getDwarfRegNum(Reg, true)));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
}
if (FirstSPAdjustAmount)
@@ -323,13 +275,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
// Deallocate stack
adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
-
- // After restoring $sp, we need to adjust CFA to $(sp + 0)
- // Emit ".cfi_def_cfa_offset 0"
- unsigned CFIIndex =
- MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, 0));
- BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
- .addCFIIndex(CFIIndex);
}
int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF,
diff --git a/llvm/test/CodeGen/RISCV/exception-pointer-register.ll b/llvm/test/CodeGen/RISCV/exception-pointer-register.ll
index b341268ff38..fafd506bc78 100644
--- a/llvm/test/CodeGen/RISCV/exception-pointer-register.ll
+++ b/llvm/test/CodeGen/RISCV/exception-pointer-register.ll
@@ -40,11 +40,7 @@ define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personali
; RV32I-NEXT: lw s1, 4(sp)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
-; RV32I-NEXT: .cfi_restore ra
-; RV32I-NEXT: .cfi_restore s0
-; RV32I-NEXT: .cfi_restore s1
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_4: # %lpad
; RV32I-NEXT: .Ltmp4:
@@ -81,11 +77,7 @@ define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personali
; RV64I-NEXT: ld s1, 8(sp)
; RV64I-NEXT: ld s0, 16(sp)
; RV64I-NEXT: ld ra, 24(sp)
-; RV64I-NEXT: .cfi_restore ra
-; RV64I-NEXT: .cfi_restore s0
-; RV64I-NEXT: .cfi_restore s1
; RV64I-NEXT: addi sp, sp, 32
-; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_4: # %lpad
; RV64I-NEXT: .Ltmp4:
@@ -119,12 +111,10 @@ end2:
define internal void @callee(i1* %p) {
; RV32I-LABEL: callee:
; RV32I: # %bb.0:
-; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: callee:
; RV64I: # %bb.0:
-; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
ret void
}
diff --git a/llvm/test/CodeGen/RISCV/frame-info.ll b/llvm/test/CodeGen/RISCV/frame-info.ll
index 7af02b54e65..4908dec3501 100644
--- a/llvm/test/CodeGen/RISCV/frame-info.ll
+++ b/llvm/test/CodeGen/RISCV/frame-info.ll
@@ -9,12 +9,10 @@
define void @trivial() {
; RV32-LABEL: trivial:
; RV32: # %bb.0:
-; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: trivial:
; RV64: # %bb.0:
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
;
; RV32-WITHFP-LABEL: trivial:
@@ -28,12 +26,8 @@ define void @trivial() {
; RV32-WITHFP-NEXT: addi s0, sp, 16
; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV32-WITHFP-NEXT: lw s0, 8(sp)
-; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
; RV32-WITHFP-NEXT: lw ra, 12(sp)
-; RV32-WITHFP-NEXT: .cfi_restore ra
-; RV32-WITHFP-NEXT: .cfi_restore s0
; RV32-WITHFP-NEXT: addi sp, sp, 16
-; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV32-WITHFP-NEXT: ret
;
; RV64-WITHFP-LABEL: trivial:
@@ -47,12 +41,8 @@ define void @trivial() {
; RV64-WITHFP-NEXT: addi s0, sp, 16
; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV64-WITHFP-NEXT: ld s0, 0(sp)
-; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
; RV64-WITHFP-NEXT: ld ra, 8(sp)
-; RV64-WITHFP-NEXT: .cfi_restore ra
-; RV64-WITHFP-NEXT: .cfi_restore s0
; RV64-WITHFP-NEXT: addi sp, sp, 16
-; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV64-WITHFP-NEXT: ret
ret void
}
@@ -75,12 +65,8 @@ define void @stack_alloc(i32 signext %size) {
; RV32-NEXT: call callee_with_args
; RV32-NEXT: addi sp, s0, -16
; RV32-NEXT: lw s0, 8(sp)
-; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: lw ra, 12(sp)
-; RV32-NEXT: .cfi_restore ra
-; RV32-NEXT: .cfi_restore s0
; RV32-NEXT: addi sp, sp, 16
-; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: stack_alloc:
@@ -105,12 +91,8 @@ define void @stack_alloc(i32 signext %size) {
; RV64-NEXT: call callee_with_args
; RV64-NEXT: addi sp, s0, -16
; RV64-NEXT: ld s0, 0(sp)
-; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: ld ra, 8(sp)
-; RV64-NEXT: .cfi_restore ra
-; RV64-NEXT: .cfi_restore s0
; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
;
; RV32-WITHFP-LABEL: stack_alloc:
@@ -130,12 +112,8 @@ define void @stack_alloc(i32 signext %size) {
; RV32-WITHFP-NEXT: call callee_with_args
; RV32-WITHFP-NEXT: addi sp, s0, -16
; RV32-WITHFP-NEXT: lw s0, 8(sp)
-; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
; RV32-WITHFP-NEXT: lw ra, 12(sp)
-; RV32-WITHFP-NEXT: .cfi_restore ra
-; RV32-WITHFP-NEXT: .cfi_restore s0
; RV32-WITHFP-NEXT: addi sp, sp, 16
-; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV32-WITHFP-NEXT: ret
;
; RV64-WITHFP-LABEL: stack_alloc:
@@ -160,12 +138,8 @@ define void @stack_alloc(i32 signext %size) {
; RV64-WITHFP-NEXT: call callee_with_args
; RV64-WITHFP-NEXT: addi sp, s0, -16
; RV64-WITHFP-NEXT: ld s0, 0(sp)
-; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
; RV64-WITHFP-NEXT: ld ra, 8(sp)
-; RV64-WITHFP-NEXT: .cfi_restore ra
-; RV64-WITHFP-NEXT: .cfi_restore s0
; RV64-WITHFP-NEXT: addi sp, sp, 16
-; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV64-WITHFP-NEXT: ret
entry:
%0 = alloca i8, i32 %size, align 16
@@ -173,8 +147,6 @@ entry:
ret void
}
-; FIXME: fix use of .cfi_restore with wrong CFAs
-
define void @branch_and_tail_call(i1 %a) {
; RV32-LABEL: branch_and_tail_call:
; RV32: # %bb.0:
@@ -186,16 +158,12 @@ define void @branch_and_tail_call(i1 %a) {
; RV32-NEXT: beqz a0, .LBB2_2
; RV32-NEXT: # %bb.1: # %blue_pill
; RV32-NEXT: lw ra, 12(sp)
-; RV32-NEXT: .cfi_restore ra
; RV32-NEXT: addi sp, sp, 16
-; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: tail callee1
; RV32-NEXT: .LBB2_2: # %red_pill
; RV32-NEXT: call callee2
; RV32-NEXT: lw ra, 12(sp)
-; RV32-NEXT: .cfi_restore ra
; RV32-NEXT: addi sp, sp, 16
-; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
;
; RV64-LABEL: branch_and_tail_call:
@@ -208,16 +176,12 @@ define void @branch_and_tail_call(i1 %a) {
; RV64-NEXT: beqz a0, .LBB2_2
; RV64-NEXT: # %bb.1: # %blue_pill
; RV64-NEXT: ld ra, 8(sp)
-; RV64-NEXT: .cfi_restore ra
; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: tail callee1
; RV64-NEXT: .LBB2_2: # %red_pill
; RV64-NEXT: call callee2
; RV64-NEXT: ld ra, 8(sp)
-; RV64-NEXT: .cfi_restore ra
; RV64-NEXT: addi sp, sp, 16
-; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
;
; RV32-WITHFP-LABEL: branch_and_tail_call:
@@ -234,22 +198,14 @@ define void @branch_and_tail_call(i1 %a) {
; RV32-WITHFP-NEXT: beqz a0, .LBB2_2
; RV32-WITHFP-NEXT: # %bb.1: # %blue_pill
; RV32-WITHFP-NEXT: lw s0, 8(sp)
-; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
; RV32-WITHFP-NEXT: lw ra, 12(sp)
-; RV32-WITHFP-NEXT: .cfi_restore ra
-; RV32-WITHFP-NEXT: .cfi_restore s0
; RV32-WITHFP-NEXT: addi sp, sp, 16
-; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV32-WITHFP-NEXT: tail callee1
; RV32-WITHFP-NEXT: .LBB2_2: # %red_pill
; RV32-WITHFP-NEXT: call callee2
; RV32-WITHFP-NEXT: lw s0, 8(sp)
-; RV32-WITHFP-NEXT: .cfi_def_cfa sp, 16
; RV32-WITHFP-NEXT: lw ra, 12(sp)
-; RV32-WITHFP-NEXT: .cfi_restore ra
-; RV32-WITHFP-NEXT: .cfi_restore s0
; RV32-WITHFP-NEXT: addi sp, sp, 16
-; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV32-WITHFP-NEXT: ret
;
; RV64-WITHFP-LABEL: branch_and_tail_call:
@@ -266,22 +222,14 @@ define void @branch_and_tail_call(i1 %a) {
; RV64-WITHFP-NEXT: beqz a0, .LBB2_2
; RV64-WITHFP-NEXT: # %bb.1: # %blue_pill
; RV64-WITHFP-NEXT: ld s0, 0(sp)
-; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
; RV64-WITHFP-NEXT: ld ra, 8(sp)
-; RV64-WITHFP-NEXT: .cfi_restore ra
-; RV64-WITHFP-NEXT: .cfi_restore s0
; RV64-WITHFP-NEXT: addi sp, sp, 16
-; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV64-WITHFP-NEXT: tail callee1
; RV64-WITHFP-NEXT: .LBB2_2: # %red_pill
; RV64-WITHFP-NEXT: call callee2
; RV64-WITHFP-NEXT: ld s0, 0(sp)
-; RV64-WITHFP-NEXT: .cfi_def_cfa sp, 16
; RV64-WITHFP-NEXT: ld ra, 8(sp)
-; RV64-WITHFP-NEXT: .cfi_restore ra
-; RV64-WITHFP-NEXT: .cfi_restore s0
; RV64-WITHFP-NEXT: addi sp, sp, 16
-; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV64-WITHFP-NEXT: ret
br i1 %a, label %blue_pill, label %red_pill
blue_pill:
diff --git a/llvm/test/CodeGen/RISCV/large-stack.ll b/llvm/test/CodeGen/RISCV/large-stack.ll
index 7808698ae2b..7acf0f4076e 100644
--- a/llvm/test/CodeGen/RISCV/large-stack.ll
+++ b/llvm/test/CodeGen/RISCV/large-stack.ll
@@ -16,7 +16,6 @@ define void @test() {
; RV32I-FPELIM-NEXT: lui a0, 74565
; RV32I-FPELIM-NEXT: addi a0, a0, 1664
; RV32I-FPELIM-NEXT: add sp, sp, a0
-; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: test:
@@ -36,12 +35,8 @@ define void @test() {
; RV32I-WITHFP-NEXT: addi a0, a0, -352
; RV32I-WITHFP-NEXT: add sp, sp, a0
; RV32I-WITHFP-NEXT: lw s0, 2024(sp)
-; RV32I-WITHFP-NEXT: .cfi_def_cfa sp, 2032
; RV32I-WITHFP-NEXT: lw ra, 2028(sp)
-; RV32I-WITHFP-NEXT: .cfi_restore ra
-; RV32I-WITHFP-NEXT: .cfi_restore s0
; RV32I-WITHFP-NEXT: addi sp, sp, 2032
-; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV32I-WITHFP-NEXT: ret
%tmp = alloca [ 305419896 x i8 ] , align 4
ret void
@@ -77,13 +72,9 @@ define void @test_emergency_spill_slot(i32 %a) {
; RV32I-FPELIM-NEXT: lui a0, 97
; RV32I-FPELIM-NEXT: addi a0, a0, 672
; RV32I-FPELIM-NEXT: add sp, sp, a0
-; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 2032
; RV32I-FPELIM-NEXT: lw s1, 2024(sp)
; RV32I-FPELIM-NEXT: lw s0, 2028(sp)
-; RV32I-FPELIM-NEXT: .cfi_restore s0
-; RV32I-FPELIM-NEXT: .cfi_restore s1
; RV32I-FPELIM-NEXT: addi sp, sp, 2032
-; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
@@ -123,14 +114,8 @@ define void @test_emergency_spill_slot(i32 %a) {
; RV32I-WITHFP-NEXT: lw s2, 2016(sp)
; RV32I-WITHFP-NEXT: lw s1, 2020(sp)
; RV32I-WITHFP-NEXT: lw s0, 2024(sp)
-; RV32I-WITHFP-NEXT: .cfi_def_cfa sp, 2032
; RV32I-WITHFP-NEXT: lw ra, 2028(sp)
-; RV32I-WITHFP-NEXT: .cfi_restore ra
-; RV32I-WITHFP-NEXT: .cfi_restore s0
-; RV32I-WITHFP-NEXT: .cfi_restore s1
-; RV32I-WITHFP-NEXT: .cfi_restore s2
; RV32I-WITHFP-NEXT: addi sp, sp, 2032
-; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0
; RV32I-WITHFP-NEXT: ret
%data = alloca [ 100000 x i32 ] , align 4
%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
diff --git a/llvm/test/CodeGen/RISCV/split-offsets.ll b/llvm/test/CodeGen/RISCV/split-offsets.ll
index 8642425344f..2d943ae71cd 100644
--- a/llvm/test/CodeGen/RISCV/split-offsets.ll
+++ b/llvm/test/CodeGen/RISCV/split-offsets.ll
@@ -22,7 +22,6 @@ define void @test1([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a3, 0(a1)
; RV32I-NEXT: sw a2, 4(a1)
-; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test1:
@@ -38,7 +37,6 @@ define void @test1([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
; RV64I-NEXT: sw a3, 4(a0)
; RV64I-NEXT: sw a3, 0(a1)
; RV64I-NEXT: sw a2, 4(a1)
-; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
entry:
%s = load [65536 x i32]*, [65536 x i32]** %sp
@@ -74,7 +72,6 @@ define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
; RV32I-NEXT: mv a3, a4
; RV32I-NEXT: blt a3, a2, .LBB1_1
; RV32I-NEXT: .LBB1_2: # %while_end
-; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: test2:
@@ -99,7 +96,6 @@ define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
; RV64I-NEXT: sext.w a4, a3
; RV64I-NEXT: blt a4, a2, .LBB1_1
; RV64I-NEXT: .LBB1_2: # %while_end
-; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
entry:
%s = load [65536 x i32]*, [65536 x i32]** %sp
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
index 0918830c5d3..afa766930ab 100644
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -53,7 +53,6 @@ define i32 @va1(i8* %fmt, ...) {
; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 24
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
-; ILP32-ILP32F-FPELIM-NEXT: .cfi_def_cfa_offset 0
; ILP32-ILP32F-FPELIM-NEXT: ret
;
; ILP32-ILP32F-WITHFP-LABEL: va1:
@@ -77,12 +76,8 @@ define i32 @va1(i8* %fmt, ...) {
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 8
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp)
-; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa sp, 16
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp)
-; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore ra
-; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore s0
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
-; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 0
; ILP32-ILP32F-WITHFP-NEXT: ret
;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va1:
@@ -100,7 +95,6 @@ define i32 @va1(i8* %fmt, ...) {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 24
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
;
; LP64-LP64F-LP64D-FPELIM-LABEL: va1:
@@ -119,7 +113,6 @@ define i32 @va1(i8* %fmt, ...) {
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 24(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 80
-; LP64-LP64F-LP64D-FPELIM-NEXT: .cfi_def_cfa_offset 0
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
;
; LP64-LP64F-LP64D-WITHFP-LABEL: va1:
@@ -144,12 +137,8 @@ define i32 @va1(i8* %fmt, ...) {
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, 8(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 16(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa sp, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 24(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore ra
-; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore s0
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 96
-; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 0
; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%va = alloca i8*, align 4
%1 = bitcast i8** %va to i8*
@@ -1809,7 +1798,6 @@ define i32 @va_large_stack(i8* %fmt, ...) {
; ILP32-ILP32F-FPELIM-NEXT: lui a1, 24414
; ILP32-ILP32F-FPELIM-NEXT: addi a1, a1, 304
; ILP32-ILP32F-FPELIM-NEXT: add sp, sp, a1
-; ILP32-ILP32F-FPELIM-NEXT: .cfi_def_cfa_offset 0
; ILP32-ILP32F-FPELIM-NEXT: ret
;
; ILP32-ILP32F-WITHFP-LABEL: va_large_stack:
@@ -1842,12 +1830,8 @@ define i32 @va_large_stack(i8* %fmt, ...) {
; ILP32-ILP32F-WITHFP-NEXT: addi a1, a1, -1728
; ILP32-ILP32F-WITHFP-NEXT: add sp, sp, a1
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 1992(sp)
-; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa sp, 2000
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 1996(sp)
-; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore ra
-; ILP32-ILP32F-WITHFP-NEXT: .cfi_restore s0
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 2032
-; ILP32-ILP32F-WITHFP-NEXT: .cfi_def_cfa_offset 0
; ILP32-ILP32F-WITHFP-NEXT: ret
;
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-LABEL: va_large_stack:
@@ -1893,7 +1877,6 @@ define i32 @va_large_stack(i8* %fmt, ...) {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lui a1, 24414
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, a1, 304
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: add sp, sp, a1
-; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: .cfi_def_cfa_offset 0
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
;
; LP64-LP64F-LP64D-FPELIM-LABEL: va_large_stack:
@@ -1943,7 +1926,6 @@ define i32 @va_large_stack(i8* %fmt, ...) {
; LP64-LP64F-LP64D-FPELIM-NEXT: lui a1, 24414
; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a1, a1, 336
; LP64-LP64F-LP64D-FPELIM-NEXT: add sp, sp, a1
-; LP64-LP64F-LP64D-FPELIM-NEXT: .cfi_def_cfa_offset 0
; LP64-LP64F-LP64D-FPELIM-NEXT: ret
;
; LP64-LP64F-LP64D-WITHFP-LABEL: va_large_stack:
@@ -1977,12 +1959,8 @@ define i32 @va_large_stack(i8* %fmt, ...) {
; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a1, a1, -1680
; LP64-LP64F-LP64D-WITHFP-NEXT: add sp, sp, a1
; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 1952(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa sp, 1968
; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 1960(sp)
-; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore ra
-; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_restore s0
; LP64-LP64F-LP64D-WITHFP-NEXT: addi sp, sp, 2032
-; LP64-LP64F-LP64D-WITHFP-NEXT: .cfi_def_cfa_offset 0
; LP64-LP64F-LP64D-WITHFP-NEXT: ret
%large = alloca [ 100000000 x i8 ]
%va = alloca i8*, align 4
diff --git a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
index aaf382da1f1..3fc4433c3af 100644
--- a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
+++ b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll
@@ -12,14 +12,13 @@
; RELAX: 0x20 R_RISCV_ADD32
; RELAX: 0x20 R_RISCV_SUB32
; RELAX-NOT: {{[}]}}
-; RELAX: 0x25 R_RISCV_SET6
-; RELAX: 0x25 R_RISCV_SUB6
+; RELAX: 0x39 R_RISCV_SET6
+; RELAX: 0x39 R_RISCV_SUB6
;
; RELAX-DWARFDUMP: CIE
; RELAX-DWARFDUMP: DW_CFA_advance_loc
; RELAX-DWARFDUMP: DW_CFA_def_cfa_offset
; RELAX-DWARFDUMP: DW_CFA_offset
-; RELAX-DWARFDUMP: DW_CFA_restore
source_filename = "frame.c"
; Function Attrs: noinline nounwind optnone
OpenPOWER on IntegriCloud