summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp18
-rw-r--r--llvm/tools/llvm-exegesis/lib/CodeTemplate.h9
-rw-r--r--llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp9
3 files changed, 19 insertions, 17 deletions
diff --git a/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp b/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
index f3111797993..677bddd10b8 100644
--- a/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
+++ b/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
@@ -67,15 +67,6 @@ bool InstructionTemplate::hasImmediateVariables() const {
});
}
-void InstructionTemplate::randomizeUnsetVariables(
- const llvm::BitVector &ForbiddenRegs) {
- for (const Variable &Var : Instr.Variables) {
- llvm::MCOperand &AssignedValue = getValueFor(Var);
- if (!AssignedValue.isValid())
- randomize(Instr, Var, AssignedValue, ForbiddenRegs);
- }
-}
-
llvm::MCInst InstructionTemplate::build() const {
llvm::MCInst Result;
Result.setOpcode(Instr.Description->Opcode);
@@ -161,4 +152,13 @@ void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
setRegisterOperandValue(randomElement(RandomConf.Uses), UseIB);
}
+void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs,
+ InstructionTemplate &IT) {
+ for (const Variable &Var : IT.Instr.Variables) {
+ llvm::MCOperand &AssignedValue = IT.getValueFor(Var);
+ if (!AssignedValue.isValid())
+ randomize(IT.Instr, Var, AssignedValue, ForbiddenRegs);
+ }
+}
+
} // namespace exegesis
diff --git a/llvm/tools/llvm-exegesis/lib/CodeTemplate.h b/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
index b11ef16ab1e..e330c6de133 100644
--- a/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
+++ b/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
@@ -36,10 +36,6 @@ struct InstructionTemplate {
const llvm::MCOperand &getValueFor(const Operand &Op) const;
bool hasImmediateVariables() const;
- // Assigns a Random Value to all Variables that are still Invalid.
- // Do not use any of the registers in `ForbiddenRegs`.
- void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs);
-
// Builds an llvm::MCInst from this InstructionTemplate setting its operands
// to the corresponding variable values. Precondition: All VariableValues must
// be set.
@@ -84,6 +80,11 @@ size_t randomBit(const llvm::BitVector &Vector);
void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
InstructionTemplate &DefIB, InstructionTemplate &UseIB);
+// Assigns a Random Value to all Variables in IT that are still Invalid.
+// Do not use any of the registers in `ForbiddenRegs`.
+void randomizeUnsetVariables(const llvm::BitVector &ForbiddenRegs,
+ InstructionTemplate &IT);
+
} // namespace exegesis
#endif // LLVM_TOOLS_LLVM_EXEGESIS_CODETEMPLATE_H
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
index 6bfef1ee4ab..de57bf3fd70 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -35,16 +35,17 @@ llvm::Expected<std::vector<BenchmarkCode>>
SnippetGenerator::generateConfigurations(unsigned Opcode) const {
if (auto E = generateCodeTemplate(Opcode)) {
CodeTemplate &CT = E.get();
+ const llvm::BitVector &ForbiddenRegs =
+ CT.ScratchSpacePointerInReg
+ ? RATC.getRegister(CT.ScratchSpacePointerInReg).aliasedBits()
+ : RATC.emptyRegisters();
std::vector<BenchmarkCode> Output;
// TODO: Generate as many BenchmarkCode as needed.
{
BenchmarkCode BC;
BC.Info = CT.Info;
for (InstructionTemplate &IT : CT.Instructions) {
- IT.randomizeUnsetVariables(
- CT.ScratchSpacePointerInReg
- ? RATC.getRegister(CT.ScratchSpacePointerInReg).aliasedBits()
- : RATC.emptyRegisters());
+ randomizeUnsetVariables(ForbiddenRegs, IT);
BC.Instructions.push_back(IT.build());
}
if (CT.ScratchSpacePointerInReg)
OpenPOWER on IntegriCloud