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-rw-r--r--llvm/test/CodeGen/RISCV/inline-asm.ll29
-rw-r--r--llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll714
2 files changed, 659 insertions, 84 deletions
diff --git a/llvm/test/CodeGen/RISCV/inline-asm.ll b/llvm/test/CodeGen/RISCV/inline-asm.ll
index 39403360215..c5aa8540427 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm.ll
@@ -182,6 +182,13 @@ define i32 @modifier_z_zero(i32 %a) nounwind {
; RV32I-NEXT: add a0, a0, zero
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret
+;
+; RV64I-LABEL: modifier_z_zero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: #APP
+; RV64I-NEXT: add a0, a0, zero
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
%1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,r"(i32 %a, i32 0)
ret i32 %1
}
@@ -194,6 +201,14 @@ define i32 @modifier_z_nonzero(i32 %a) nounwind {
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret
+;
+; RV64I-LABEL: modifier_z_nonzero:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 1
+; RV64I-NEXT: #APP
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
%1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,r"(i32 %a, i32 1)
ret i32 %1
}
@@ -205,6 +220,13 @@ define i32 @modifier_i_imm(i32 %a) nounwind {
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret
+;
+; RV64I-LABEL: modifier_i_imm:
+; RV64I: # %bb.0:
+; RV64I-NEXT: #APP
+; RV64I-NEXT: addi a0, a0, 1
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
%1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 1)
ret i32 %1
}
@@ -216,6 +238,13 @@ define i32 @modifier_i_reg(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret
+;
+; RV64I-LABEL: modifier_i_reg:
+; RV64I: # %bb.0:
+; RV64I-NEXT: #APP
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ret
%1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 %b)
ret i32 %1
}
diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
index 3e14b7511fe..91b6249d06d 100644
--- a/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
+++ b/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
@@ -2,9 +2,9 @@
; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32
; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \
-; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-F
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32IF
; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \
-; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32-FD
+; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32IFD
;
; TODO: Add RV64 tests when we can lower global addresses.
@@ -40,6 +40,39 @@ define void @foo_i32() nounwind #0 {
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: mret
;
+; CHECK-RV32IF-LABEL: foo_i32:
+; CHECK-RV32IF: # %bb.0:
+; CHECK-RV32IF-NEXT: addi sp, sp, -16
+; CHECK-RV32IF-NEXT: sw a0, 12(sp)
+; CHECK-RV32IF-NEXT: sw a1, 8(sp)
+; CHECK-RV32IF-NEXT: lui a0, %hi(a)
+; CHECK-RV32IF-NEXT: lw a0, %lo(a)(a0)
+; CHECK-RV32IF-NEXT: lui a1, %hi(b)
+; CHECK-RV32IF-NEXT: lw a1, %lo(b)(a1)
+; CHECK-RV32IF-NEXT: add a0, a1, a0
+; CHECK-RV32IF-NEXT: lui a1, %hi(c)
+; CHECK-RV32IF-NEXT: sw a0, %lo(c)(a1)
+; CHECK-RV32IF-NEXT: lw a1, 8(sp)
+; CHECK-RV32IF-NEXT: lw a0, 12(sp)
+; CHECK-RV32IF-NEXT: addi sp, sp, 16
+; CHECK-RV32IF-NEXT: mret
+;
+; CHECK-RV32IFD-LABEL: foo_i32:
+; CHECK-RV32IFD: # %bb.0:
+; CHECK-RV32IFD-NEXT: addi sp, sp, -16
+; CHECK-RV32IFD-NEXT: sw a0, 12(sp)
+; CHECK-RV32IFD-NEXT: sw a1, 8(sp)
+; CHECK-RV32IFD-NEXT: lui a0, %hi(a)
+; CHECK-RV32IFD-NEXT: lw a0, %lo(a)(a0)
+; CHECK-RV32IFD-NEXT: lui a1, %hi(b)
+; CHECK-RV32IFD-NEXT: lw a1, %lo(b)(a1)
+; CHECK-RV32IFD-NEXT: add a0, a1, a0
+; CHECK-RV32IFD-NEXT: lui a1, %hi(c)
+; CHECK-RV32IFD-NEXT: sw a0, %lo(c)(a1)
+; CHECK-RV32IFD-NEXT: lw a1, 8(sp)
+; CHECK-RV32IFD-NEXT: lw a0, 12(sp)
+; CHECK-RV32IFD-NEXT: addi sp, sp, 16
+; CHECK-RV32IFD-NEXT: mret
%1 = load i32, i32* @a
%2 = load i32, i32* @b
%add = add nsw i32 %2, %1
@@ -74,6 +107,49 @@ define void @foo_fp_i32() nounwind #1 {
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: mret
;
+; CHECK-RV32IF-LABEL: foo_fp_i32:
+; CHECK-RV32IF: # %bb.0:
+; CHECK-RV32IF-NEXT: addi sp, sp, -16
+; CHECK-RV32IF-NEXT: sw ra, 12(sp)
+; CHECK-RV32IF-NEXT: sw s0, 8(sp)
+; CHECK-RV32IF-NEXT: sw a0, 4(sp)
+; CHECK-RV32IF-NEXT: sw a1, 0(sp)
+; CHECK-RV32IF-NEXT: addi s0, sp, 16
+; CHECK-RV32IF-NEXT: lui a0, %hi(a)
+; CHECK-RV32IF-NEXT: lw a0, %lo(a)(a0)
+; CHECK-RV32IF-NEXT: lui a1, %hi(b)
+; CHECK-RV32IF-NEXT: lw a1, %lo(b)(a1)
+; CHECK-RV32IF-NEXT: add a0, a1, a0
+; CHECK-RV32IF-NEXT: lui a1, %hi(c)
+; CHECK-RV32IF-NEXT: sw a0, %lo(c)(a1)
+; CHECK-RV32IF-NEXT: lw a1, 0(sp)
+; CHECK-RV32IF-NEXT: lw a0, 4(sp)
+; CHECK-RV32IF-NEXT: lw s0, 8(sp)
+; CHECK-RV32IF-NEXT: lw ra, 12(sp)
+; CHECK-RV32IF-NEXT: addi sp, sp, 16
+; CHECK-RV32IF-NEXT: mret
+;
+; CHECK-RV32IFD-LABEL: foo_fp_i32:
+; CHECK-RV32IFD: # %bb.0:
+; CHECK-RV32IFD-NEXT: addi sp, sp, -16
+; CHECK-RV32IFD-NEXT: sw ra, 12(sp)
+; CHECK-RV32IFD-NEXT: sw s0, 8(sp)
+; CHECK-RV32IFD-NEXT: sw a0, 4(sp)
+; CHECK-RV32IFD-NEXT: sw a1, 0(sp)
+; CHECK-RV32IFD-NEXT: addi s0, sp, 16
+; CHECK-RV32IFD-NEXT: lui a0, %hi(a)
+; CHECK-RV32IFD-NEXT: lw a0, %lo(a)(a0)
+; CHECK-RV32IFD-NEXT: lui a1, %hi(b)
+; CHECK-RV32IFD-NEXT: lw a1, %lo(b)(a1)
+; CHECK-RV32IFD-NEXT: add a0, a1, a0
+; CHECK-RV32IFD-NEXT: lui a1, %hi(c)
+; CHECK-RV32IFD-NEXT: sw a0, %lo(c)(a1)
+; CHECK-RV32IFD-NEXT: lw a1, 0(sp)
+; CHECK-RV32IFD-NEXT: lw a0, 4(sp)
+; CHECK-RV32IFD-NEXT: lw s0, 8(sp)
+; CHECK-RV32IFD-NEXT: lw ra, 12(sp)
+; CHECK-RV32IFD-NEXT: addi sp, sp, 16
+; CHECK-RV32IFD-NEXT: mret
%1 = load i32, i32* @a
%2 = load i32, i32* @b
%add = add nsw i32 %2, %1
@@ -86,25 +162,88 @@ define void @foo_fp_i32() nounwind #1 {
@d = external global float
define void @foo_float() nounwind #0 {
-; CHECK-RV32-F-LABEL: foo_float:
-; CHECK-RV32-F: # %bb.0:
-; CHECK-RV32-F-NEXT: addi sp, sp, -16
-; CHECK-RV32-F-NEXT: sw a0, 12(sp)
-; CHECK-RV32-F-NEXT: fsw ft0, 8(sp)
-; CHECK-RV32-F-NEXT: fsw ft1, 4(sp)
-; CHECK-RV32-F-NEXT: lui a0, %hi(f)
-; CHECK-RV32-F-NEXT: flw ft0, %lo(f)(a0)
-; CHECK-RV32-F-NEXT: lui a0, %hi(e)
-; CHECK-RV32-F-NEXT: flw ft1, %lo(e)(a0)
-; CHECK-RV32-F-NEXT: fadd.s ft0, ft1, ft0
-; CHECK-RV32-F-NEXT: lui a0, %hi(d)
-; CHECK-RV32-F-NEXT: fsw ft0, %lo(d)(a0)
-; CHECK-RV32-F-NEXT: flw ft1, 4(sp)
-; CHECK-RV32-F-NEXT: flw ft0, 8(sp)
-; CHECK-RV32-F-NEXT: lw a0, 12(sp)
-; CHECK-RV32-F-NEXT: addi sp, sp, 16
-; CHECK-RV32-F-NEXT: mret
+; CHECK-RV32-LABEL: foo_float:
+; CHECK-RV32: # %bb.0:
+; CHECK-RV32-NEXT: addi sp, sp, -64
+; CHECK-RV32-NEXT: sw ra, 60(sp)
+; CHECK-RV32-NEXT: sw t0, 56(sp)
+; CHECK-RV32-NEXT: sw t1, 52(sp)
+; CHECK-RV32-NEXT: sw t2, 48(sp)
+; CHECK-RV32-NEXT: sw a0, 44(sp)
+; CHECK-RV32-NEXT: sw a1, 40(sp)
+; CHECK-RV32-NEXT: sw a2, 36(sp)
+; CHECK-RV32-NEXT: sw a3, 32(sp)
+; CHECK-RV32-NEXT: sw a4, 28(sp)
+; CHECK-RV32-NEXT: sw a5, 24(sp)
+; CHECK-RV32-NEXT: sw a6, 20(sp)
+; CHECK-RV32-NEXT: sw a7, 16(sp)
+; CHECK-RV32-NEXT: sw t3, 12(sp)
+; CHECK-RV32-NEXT: sw t4, 8(sp)
+; CHECK-RV32-NEXT: sw t5, 4(sp)
+; CHECK-RV32-NEXT: sw t6, 0(sp)
+; CHECK-RV32-NEXT: lui a0, %hi(e)
+; CHECK-RV32-NEXT: lw a0, %lo(e)(a0)
+; CHECK-RV32-NEXT: lui a1, %hi(f)
+; CHECK-RV32-NEXT: lw a1, %lo(f)(a1)
+; CHECK-RV32-NEXT: call __addsf3
+; CHECK-RV32-NEXT: lui a1, %hi(d)
+; CHECK-RV32-NEXT: sw a0, %lo(d)(a1)
+; CHECK-RV32-NEXT: lw t6, 0(sp)
+; CHECK-RV32-NEXT: lw t5, 4(sp)
+; CHECK-RV32-NEXT: lw t4, 8(sp)
+; CHECK-RV32-NEXT: lw t3, 12(sp)
+; CHECK-RV32-NEXT: lw a7, 16(sp)
+; CHECK-RV32-NEXT: lw a6, 20(sp)
+; CHECK-RV32-NEXT: lw a5, 24(sp)
+; CHECK-RV32-NEXT: lw a4, 28(sp)
+; CHECK-RV32-NEXT: lw a3, 32(sp)
+; CHECK-RV32-NEXT: lw a2, 36(sp)
+; CHECK-RV32-NEXT: lw a1, 40(sp)
+; CHECK-RV32-NEXT: lw a0, 44(sp)
+; CHECK-RV32-NEXT: lw t2, 48(sp)
+; CHECK-RV32-NEXT: lw t1, 52(sp)
+; CHECK-RV32-NEXT: lw t0, 56(sp)
+; CHECK-RV32-NEXT: lw ra, 60(sp)
+; CHECK-RV32-NEXT: addi sp, sp, 64
+; CHECK-RV32-NEXT: mret
;
+; CHECK-RV32IF-LABEL: foo_float:
+; CHECK-RV32IF: # %bb.0:
+; CHECK-RV32IF-NEXT: addi sp, sp, -16
+; CHECK-RV32IF-NEXT: sw a0, 12(sp)
+; CHECK-RV32IF-NEXT: fsw ft0, 8(sp)
+; CHECK-RV32IF-NEXT: fsw ft1, 4(sp)
+; CHECK-RV32IF-NEXT: lui a0, %hi(f)
+; CHECK-RV32IF-NEXT: flw ft0, %lo(f)(a0)
+; CHECK-RV32IF-NEXT: lui a0, %hi(e)
+; CHECK-RV32IF-NEXT: flw ft1, %lo(e)(a0)
+; CHECK-RV32IF-NEXT: fadd.s ft0, ft1, ft0
+; CHECK-RV32IF-NEXT: lui a0, %hi(d)
+; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
+; CHECK-RV32IF-NEXT: flw ft1, 4(sp)
+; CHECK-RV32IF-NEXT: flw ft0, 8(sp)
+; CHECK-RV32IF-NEXT: lw a0, 12(sp)
+; CHECK-RV32IF-NEXT: addi sp, sp, 16
+; CHECK-RV32IF-NEXT: mret
+;
+; CHECK-RV32IFD-LABEL: foo_float:
+; CHECK-RV32IFD: # %bb.0:
+; CHECK-RV32IFD-NEXT: addi sp, sp, -32
+; CHECK-RV32IFD-NEXT: sw a0, 28(sp)
+; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp)
+; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp)
+; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
+; CHECK-RV32IFD-NEXT: flw ft0, %lo(f)(a0)
+; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
+; CHECK-RV32IFD-NEXT: flw ft1, %lo(e)(a0)
+; CHECK-RV32IFD-NEXT: fadd.s ft0, ft1, ft0
+; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
+; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
+; CHECK-RV32IFD-NEXT: fld ft1, 8(sp)
+; CHECK-RV32IFD-NEXT: fld ft0, 16(sp)
+; CHECK-RV32IFD-NEXT: lw a0, 28(sp)
+; CHECK-RV32IFD-NEXT: addi sp, sp, 32
+; CHECK-RV32IFD-NEXT: mret
%1 = load float, float* @e
%2 = load float, float* @f
%add = fadd float %1, %2
@@ -116,30 +255,101 @@ define void @foo_float() nounwind #0 {
; Additionally check frame pointer and return address are properly saved.
;
define void @foo_fp_float() nounwind #1 {
-; CHECK-RV32-F-LABEL: foo_fp_float:
-; CHECK-RV32-F: # %bb.0:
-; CHECK-RV32-F-NEXT: addi sp, sp, -32
-; CHECK-RV32-F-NEXT: sw ra, 28(sp)
-; CHECK-RV32-F-NEXT: sw s0, 24(sp)
-; CHECK-RV32-F-NEXT: sw a0, 20(sp)
-; CHECK-RV32-F-NEXT: fsw ft0, 16(sp)
-; CHECK-RV32-F-NEXT: fsw ft1, 12(sp)
-; CHECK-RV32-F-NEXT: addi s0, sp, 32
-; CHECK-RV32-F-NEXT: lui a0, %hi(f)
-; CHECK-RV32-F-NEXT: flw ft0, %lo(f)(a0)
-; CHECK-RV32-F-NEXT: lui a0, %hi(e)
-; CHECK-RV32-F-NEXT: flw ft1, %lo(e)(a0)
-; CHECK-RV32-F-NEXT: fadd.s ft0, ft1, ft0
-; CHECK-RV32-F-NEXT: lui a0, %hi(d)
-; CHECK-RV32-F-NEXT: fsw ft0, %lo(d)(a0)
-; CHECK-RV32-F-NEXT: flw ft1, 12(sp)
-; CHECK-RV32-F-NEXT: flw ft0, 16(sp)
-; CHECK-RV32-F-NEXT: lw a0, 20(sp)
-; CHECK-RV32-F-NEXT: lw s0, 24(sp)
-; CHECK-RV32-F-NEXT: lw ra, 28(sp)
-; CHECK-RV32-F-NEXT: addi sp, sp, 32
-; CHECK-RV32-F-NEXT: mret
+; CHECK-RV32-LABEL: foo_fp_float:
+; CHECK-RV32: # %bb.0:
+; CHECK-RV32-NEXT: addi sp, sp, -80
+; CHECK-RV32-NEXT: sw ra, 76(sp)
+; CHECK-RV32-NEXT: sw t0, 72(sp)
+; CHECK-RV32-NEXT: sw t1, 68(sp)
+; CHECK-RV32-NEXT: sw t2, 64(sp)
+; CHECK-RV32-NEXT: sw s0, 60(sp)
+; CHECK-RV32-NEXT: sw a0, 56(sp)
+; CHECK-RV32-NEXT: sw a1, 52(sp)
+; CHECK-RV32-NEXT: sw a2, 48(sp)
+; CHECK-RV32-NEXT: sw a3, 44(sp)
+; CHECK-RV32-NEXT: sw a4, 40(sp)
+; CHECK-RV32-NEXT: sw a5, 36(sp)
+; CHECK-RV32-NEXT: sw a6, 32(sp)
+; CHECK-RV32-NEXT: sw a7, 28(sp)
+; CHECK-RV32-NEXT: sw t3, 24(sp)
+; CHECK-RV32-NEXT: sw t4, 20(sp)
+; CHECK-RV32-NEXT: sw t5, 16(sp)
+; CHECK-RV32-NEXT: sw t6, 12(sp)
+; CHECK-RV32-NEXT: addi s0, sp, 80
+; CHECK-RV32-NEXT: lui a0, %hi(e)
+; CHECK-RV32-NEXT: lw a0, %lo(e)(a0)
+; CHECK-RV32-NEXT: lui a1, %hi(f)
+; CHECK-RV32-NEXT: lw a1, %lo(f)(a1)
+; CHECK-RV32-NEXT: call __addsf3
+; CHECK-RV32-NEXT: lui a1, %hi(d)
+; CHECK-RV32-NEXT: sw a0, %lo(d)(a1)
+; CHECK-RV32-NEXT: lw t6, 12(sp)
+; CHECK-RV32-NEXT: lw t5, 16(sp)
+; CHECK-RV32-NEXT: lw t4, 20(sp)
+; CHECK-RV32-NEXT: lw t3, 24(sp)
+; CHECK-RV32-NEXT: lw a7, 28(sp)
+; CHECK-RV32-NEXT: lw a6, 32(sp)
+; CHECK-RV32-NEXT: lw a5, 36(sp)
+; CHECK-RV32-NEXT: lw a4, 40(sp)
+; CHECK-RV32-NEXT: lw a3, 44(sp)
+; CHECK-RV32-NEXT: lw a2, 48(sp)
+; CHECK-RV32-NEXT: lw a1, 52(sp)
+; CHECK-RV32-NEXT: lw a0, 56(sp)
+; CHECK-RV32-NEXT: lw s0, 60(sp)
+; CHECK-RV32-NEXT: lw t2, 64(sp)
+; CHECK-RV32-NEXT: lw t1, 68(sp)
+; CHECK-RV32-NEXT: lw t0, 72(sp)
+; CHECK-RV32-NEXT: lw ra, 76(sp)
+; CHECK-RV32-NEXT: addi sp, sp, 80
+; CHECK-RV32-NEXT: mret
;
+; CHECK-RV32IF-LABEL: foo_fp_float:
+; CHECK-RV32IF: # %bb.0:
+; CHECK-RV32IF-NEXT: addi sp, sp, -32
+; CHECK-RV32IF-NEXT: sw ra, 28(sp)
+; CHECK-RV32IF-NEXT: sw s0, 24(sp)
+; CHECK-RV32IF-NEXT: sw a0, 20(sp)
+; CHECK-RV32IF-NEXT: fsw ft0, 16(sp)
+; CHECK-RV32IF-NEXT: fsw ft1, 12(sp)
+; CHECK-RV32IF-NEXT: addi s0, sp, 32
+; CHECK-RV32IF-NEXT: lui a0, %hi(f)
+; CHECK-RV32IF-NEXT: flw ft0, %lo(f)(a0)
+; CHECK-RV32IF-NEXT: lui a0, %hi(e)
+; CHECK-RV32IF-NEXT: flw ft1, %lo(e)(a0)
+; CHECK-RV32IF-NEXT: fadd.s ft0, ft1, ft0
+; CHECK-RV32IF-NEXT: lui a0, %hi(d)
+; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
+; CHECK-RV32IF-NEXT: flw ft1, 12(sp)
+; CHECK-RV32IF-NEXT: flw ft0, 16(sp)
+; CHECK-RV32IF-NEXT: lw a0, 20(sp)
+; CHECK-RV32IF-NEXT: lw s0, 24(sp)
+; CHECK-RV32IF-NEXT: lw ra, 28(sp)
+; CHECK-RV32IF-NEXT: addi sp, sp, 32
+; CHECK-RV32IF-NEXT: mret
+;
+; CHECK-RV32IFD-LABEL: foo_fp_float:
+; CHECK-RV32IFD: # %bb.0:
+; CHECK-RV32IFD-NEXT: addi sp, sp, -32
+; CHECK-RV32IFD-NEXT: sw ra, 28(sp)
+; CHECK-RV32IFD-NEXT: sw s0, 24(sp)
+; CHECK-RV32IFD-NEXT: sw a0, 20(sp)
+; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp)
+; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp)
+; CHECK-RV32IFD-NEXT: addi s0, sp, 32
+; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
+; CHECK-RV32IFD-NEXT: flw ft0, %lo(f)(a0)
+; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
+; CHECK-RV32IFD-NEXT: flw ft1, %lo(e)(a0)
+; CHECK-RV32IFD-NEXT: fadd.s ft0, ft1, ft0
+; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
+; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
+; CHECK-RV32IFD-NEXT: fld ft1, 0(sp)
+; CHECK-RV32IFD-NEXT: fld ft0, 8(sp)
+; CHECK-RV32IFD-NEXT: lw a0, 20(sp)
+; CHECK-RV32IFD-NEXT: lw s0, 24(sp)
+; CHECK-RV32IFD-NEXT: lw ra, 28(sp)
+; CHECK-RV32IFD-NEXT: addi sp, sp, 32
+; CHECK-RV32IFD-NEXT: mret
%1 = load float, float* @e
%2 = load float, float* @f
%add = fadd float %1, %2
@@ -152,25 +362,190 @@ define void @foo_fp_float() nounwind #1 {
@g = external global double
define void @foo_double() nounwind #0 {
-; CHECK-RV32-FD-LABEL: foo_double:
-; CHECK-RV32-FD: # %bb.0:
-; CHECK-RV32-FD-NEXT: addi sp, sp, -32
-; CHECK-RV32-FD-NEXT: sw a0, 28(sp)
-; CHECK-RV32-FD-NEXT: fsd ft0, 16(sp)
-; CHECK-RV32-FD-NEXT: fsd ft1, 8(sp)
-; CHECK-RV32-FD-NEXT: lui a0, %hi(i)
-; CHECK-RV32-FD-NEXT: fld ft0, %lo(i)(a0)
-; CHECK-RV32-FD-NEXT: lui a0, %hi(h)
-; CHECK-RV32-FD-NEXT: fld ft1, %lo(h)(a0)
-; CHECK-RV32-FD-NEXT: fadd.d ft0, ft1, ft0
-; CHECK-RV32-FD-NEXT: lui a0, %hi(g)
-; CHECK-RV32-FD-NEXT: fsd ft0, %lo(g)(a0)
-; CHECK-RV32-FD-NEXT: fld ft1, 8(sp)
-; CHECK-RV32-FD-NEXT: fld ft0, 16(sp)
-; CHECK-RV32-FD-NEXT: lw a0, 28(sp)
-; CHECK-RV32-FD-NEXT: addi sp, sp, 32
-; CHECK-RV32-FD-NEXT: mret
+; CHECK-RV32-LABEL: foo_double:
+; CHECK-RV32: # %bb.0:
+; CHECK-RV32-NEXT: addi sp, sp, -64
+; CHECK-RV32-NEXT: sw ra, 60(sp)
+; CHECK-RV32-NEXT: sw t0, 56(sp)
+; CHECK-RV32-NEXT: sw t1, 52(sp)
+; CHECK-RV32-NEXT: sw t2, 48(sp)
+; CHECK-RV32-NEXT: sw a0, 44(sp)
+; CHECK-RV32-NEXT: sw a1, 40(sp)
+; CHECK-RV32-NEXT: sw a2, 36(sp)
+; CHECK-RV32-NEXT: sw a3, 32(sp)
+; CHECK-RV32-NEXT: sw a4, 28(sp)
+; CHECK-RV32-NEXT: sw a5, 24(sp)
+; CHECK-RV32-NEXT: sw a6, 20(sp)
+; CHECK-RV32-NEXT: sw a7, 16(sp)
+; CHECK-RV32-NEXT: sw t3, 12(sp)
+; CHECK-RV32-NEXT: sw t4, 8(sp)
+; CHECK-RV32-NEXT: sw t5, 4(sp)
+; CHECK-RV32-NEXT: sw t6, 0(sp)
+; CHECK-RV32-NEXT: lui a1, %hi(h)
+; CHECK-RV32-NEXT: lw a0, %lo(h)(a1)
+; CHECK-RV32-NEXT: addi a1, a1, %lo(h)
+; CHECK-RV32-NEXT: lw a1, 4(a1)
+; CHECK-RV32-NEXT: lui a3, %hi(i)
+; CHECK-RV32-NEXT: lw a2, %lo(i)(a3)
+; CHECK-RV32-NEXT: addi a3, a3, %lo(i)
+; CHECK-RV32-NEXT: lw a3, 4(a3)
+; CHECK-RV32-NEXT: call __adddf3
+; CHECK-RV32-NEXT: lui a2, %hi(g)
+; CHECK-RV32-NEXT: addi a3, a2, %lo(g)
+; CHECK-RV32-NEXT: sw a1, 4(a3)
+; CHECK-RV32-NEXT: sw a0, %lo(g)(a2)
+; CHECK-RV32-NEXT: lw t6, 0(sp)
+; CHECK-RV32-NEXT: lw t5, 4(sp)
+; CHECK-RV32-NEXT: lw t4, 8(sp)
+; CHECK-RV32-NEXT: lw t3, 12(sp)
+; CHECK-RV32-NEXT: lw a7, 16(sp)
+; CHECK-RV32-NEXT: lw a6, 20(sp)
+; CHECK-RV32-NEXT: lw a5, 24(sp)
+; CHECK-RV32-NEXT: lw a4, 28(sp)
+; CHECK-RV32-NEXT: lw a3, 32(sp)
+; CHECK-RV32-NEXT: lw a2, 36(sp)
+; CHECK-RV32-NEXT: lw a1, 40(sp)
+; CHECK-RV32-NEXT: lw a0, 44(sp)
+; CHECK-RV32-NEXT: lw t2, 48(sp)
+; CHECK-RV32-NEXT: lw t1, 52(sp)
+; CHECK-RV32-NEXT: lw t0, 56(sp)
+; CHECK-RV32-NEXT: lw ra, 60(sp)
+; CHECK-RV32-NEXT: addi sp, sp, 64
+; CHECK-RV32-NEXT: mret
+;
+; CHECK-RV32IF-LABEL: foo_double:
+; CHECK-RV32IF: # %bb.0:
+; CHECK-RV32IF-NEXT: addi sp, sp, -192
+; CHECK-RV32IF-NEXT: sw ra, 188(sp)
+; CHECK-RV32IF-NEXT: sw t0, 184(sp)
+; CHECK-RV32IF-NEXT: sw t1, 180(sp)
+; CHECK-RV32IF-NEXT: sw t2, 176(sp)
+; CHECK-RV32IF-NEXT: sw a0, 172(sp)
+; CHECK-RV32IF-NEXT: sw a1, 168(sp)
+; CHECK-RV32IF-NEXT: sw a2, 164(sp)
+; CHECK-RV32IF-NEXT: sw a3, 160(sp)
+; CHECK-RV32IF-NEXT: sw a4, 156(sp)
+; CHECK-RV32IF-NEXT: sw a5, 152(sp)
+; CHECK-RV32IF-NEXT: sw a6, 148(sp)
+; CHECK-RV32IF-NEXT: sw a7, 144(sp)
+; CHECK-RV32IF-NEXT: sw t3, 140(sp)
+; CHECK-RV32IF-NEXT: sw t4, 136(sp)
+; CHECK-RV32IF-NEXT: sw t5, 132(sp)
+; CHECK-RV32IF-NEXT: sw t6, 128(sp)
+; CHECK-RV32IF-NEXT: fsw ft0, 124(sp)
+; CHECK-RV32IF-NEXT: fsw ft1, 120(sp)
+; CHECK-RV32IF-NEXT: fsw ft2, 116(sp)
+; CHECK-RV32IF-NEXT: fsw ft3, 112(sp)
+; CHECK-RV32IF-NEXT: fsw ft4, 108(sp)
+; CHECK-RV32IF-NEXT: fsw ft5, 104(sp)
+; CHECK-RV32IF-NEXT: fsw ft6, 100(sp)
+; CHECK-RV32IF-NEXT: fsw ft7, 96(sp)
+; CHECK-RV32IF-NEXT: fsw fa0, 92(sp)
+; CHECK-RV32IF-NEXT: fsw fa1, 88(sp)
+; CHECK-RV32IF-NEXT: fsw fa2, 84(sp)
+; CHECK-RV32IF-NEXT: fsw fa3, 80(sp)
+; CHECK-RV32IF-NEXT: fsw fa4, 76(sp)
+; CHECK-RV32IF-NEXT: fsw fa5, 72(sp)
+; CHECK-RV32IF-NEXT: fsw fa6, 68(sp)
+; CHECK-RV32IF-NEXT: fsw fa7, 64(sp)
+; CHECK-RV32IF-NEXT: fsw ft8, 60(sp)
+; CHECK-RV32IF-NEXT: fsw ft9, 56(sp)
+; CHECK-RV32IF-NEXT: fsw ft10, 52(sp)
+; CHECK-RV32IF-NEXT: fsw ft11, 48(sp)
+; CHECK-RV32IF-NEXT: fsw fs0, 44(sp)
+; CHECK-RV32IF-NEXT: fsw fs1, 40(sp)
+; CHECK-RV32IF-NEXT: fsw fs2, 36(sp)
+; CHECK-RV32IF-NEXT: fsw fs3, 32(sp)
+; CHECK-RV32IF-NEXT: fsw fs4, 28(sp)
+; CHECK-RV32IF-NEXT: fsw fs5, 24(sp)
+; CHECK-RV32IF-NEXT: fsw fs6, 20(sp)
+; CHECK-RV32IF-NEXT: fsw fs7, 16(sp)
+; CHECK-RV32IF-NEXT: fsw fs8, 12(sp)
+; CHECK-RV32IF-NEXT: fsw fs9, 8(sp)
+; CHECK-RV32IF-NEXT: fsw fs10, 4(sp)
+; CHECK-RV32IF-NEXT: fsw fs11, 0(sp)
+; CHECK-RV32IF-NEXT: lui a1, %hi(h)
+; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1)
+; CHECK-RV32IF-NEXT: addi a1, a1, %lo(h)
+; CHECK-RV32IF-NEXT: lw a1, 4(a1)
+; CHECK-RV32IF-NEXT: lui a3, %hi(i)
+; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3)
+; CHECK-RV32IF-NEXT: addi a3, a3, %lo(i)
+; CHECK-RV32IF-NEXT: lw a3, 4(a3)
+; CHECK-RV32IF-NEXT: call __adddf3
+; CHECK-RV32IF-NEXT: lui a2, %hi(g)
+; CHECK-RV32IF-NEXT: addi a3, a2, %lo(g)
+; CHECK-RV32IF-NEXT: sw a1, 4(a3)
+; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2)
+; CHECK-RV32IF-NEXT: flw fs11, 0(sp)
+; CHECK-RV32IF-NEXT: flw fs10, 4(sp)
+; CHECK-RV32IF-NEXT: flw fs9, 8(sp)
+; CHECK-RV32IF-NEXT: flw fs8, 12(sp)
+; CHECK-RV32IF-NEXT: flw fs7, 16(sp)
+; CHECK-RV32IF-NEXT: flw fs6, 20(sp)
+; CHECK-RV32IF-NEXT: flw fs5, 24(sp)
+; CHECK-RV32IF-NEXT: flw fs4, 28(sp)
+; CHECK-RV32IF-NEXT: flw fs3, 32(sp)
+; CHECK-RV32IF-NEXT: flw fs2, 36(sp)
+; CHECK-RV32IF-NEXT: flw fs1, 40(sp)
+; CHECK-RV32IF-NEXT: flw fs0, 44(sp)
+; CHECK-RV32IF-NEXT: flw ft11, 48(sp)
+; CHECK-RV32IF-NEXT: flw ft10, 52(sp)
+; CHECK-RV32IF-NEXT: flw ft9, 56(sp)
+; CHECK-RV32IF-NEXT: flw ft8, 60(sp)
+; CHECK-RV32IF-NEXT: flw fa7, 64(sp)
+; CHECK-RV32IF-NEXT: flw fa6, 68(sp)
+; CHECK-RV32IF-NEXT: flw fa5, 72(sp)
+; CHECK-RV32IF-NEXT: flw fa4, 76(sp)
+; CHECK-RV32IF-NEXT: flw fa3, 80(sp)
+; CHECK-RV32IF-NEXT: flw fa2, 84(sp)
+; CHECK-RV32IF-NEXT: flw fa1, 88(sp)
+; CHECK-RV32IF-NEXT: flw fa0, 92(sp)
+; CHECK-RV32IF-NEXT: flw ft7, 96(sp)
+; CHECK-RV32IF-NEXT: flw ft6, 100(sp)
+; CHECK-RV32IF-NEXT: flw ft5, 104(sp)
+; CHECK-RV32IF-NEXT: flw ft4, 108(sp)
+; CHECK-RV32IF-NEXT: flw ft3, 112(sp)
+; CHECK-RV32IF-NEXT: flw ft2, 116(sp)
+; CHECK-RV32IF-NEXT: flw ft1, 120(sp)
+; CHECK-RV32IF-NEXT: flw ft0, 124(sp)
+; CHECK-RV32IF-NEXT: lw t6, 128(sp)
+; CHECK-RV32IF-NEXT: lw t5, 132(sp)
+; CHECK-RV32IF-NEXT: lw t4, 136(sp)
+; CHECK-RV32IF-NEXT: lw t3, 140(sp)
+; CHECK-RV32IF-NEXT: lw a7, 144(sp)
+; CHECK-RV32IF-NEXT: lw a6, 148(sp)
+; CHECK-RV32IF-NEXT: lw a5, 152(sp)
+; CHECK-RV32IF-NEXT: lw a4, 156(sp)
+; CHECK-RV32IF-NEXT: lw a3, 160(sp)
+; CHECK-RV32IF-NEXT: lw a2, 164(sp)
+; CHECK-RV32IF-NEXT: lw a1, 168(sp)
+; CHECK-RV32IF-NEXT: lw a0, 172(sp)
+; CHECK-RV32IF-NEXT: lw t2, 176(sp)
+; CHECK-RV32IF-NEXT: lw t1, 180(sp)
+; CHECK-RV32IF-NEXT: lw t0, 184(sp)
+; CHECK-RV32IF-NEXT: lw ra, 188(sp)
+; CHECK-RV32IF-NEXT: addi sp, sp, 192
+; CHECK-RV32IF-NEXT: mret
;
+; CHECK-RV32IFD-LABEL: foo_double:
+; CHECK-RV32IFD: # %bb.0:
+; CHECK-RV32IFD-NEXT: addi sp, sp, -32
+; CHECK-RV32IFD-NEXT: sw a0, 28(sp)
+; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp)
+; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp)
+; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
+; CHECK-RV32IFD-NEXT: fld ft0, %lo(i)(a0)
+; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
+; CHECK-RV32IFD-NEXT: fld ft1, %lo(h)(a0)
+; CHECK-RV32IFD-NEXT: fadd.d ft0, ft1, ft0
+; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
+; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
+; CHECK-RV32IFD-NEXT: fld ft1, 8(sp)
+; CHECK-RV32IFD-NEXT: fld ft0, 16(sp)
+; CHECK-RV32IFD-NEXT: lw a0, 28(sp)
+; CHECK-RV32IFD-NEXT: addi sp, sp, 32
+; CHECK-RV32IFD-NEXT: mret
%1 = load double, double* @h
%2 = load double, double* @i
%add = fadd double %1, %2
@@ -182,30 +557,201 @@ define void @foo_double() nounwind #0 {
; Additionally check frame pointer and return address are properly saved.
;
define void @foo_fp_double() nounwind #1 {
-; CHECK-RV32-FD-LABEL: foo_fp_double:
-; CHECK-RV32-FD: # %bb.0:
-; CHECK-RV32-FD-NEXT: addi sp, sp, -32
-; CHECK-RV32-FD-NEXT: sw ra, 28(sp)
-; CHECK-RV32-FD-NEXT: sw s0, 24(sp)
-; CHECK-RV32-FD-NEXT: sw a0, 20(sp)
-; CHECK-RV32-FD-NEXT: fsd ft0, 8(sp)
-; CHECK-RV32-FD-NEXT: fsd ft1, 0(sp)
-; CHECK-RV32-FD-NEXT: addi s0, sp, 32
-; CHECK-RV32-FD-NEXT: lui a0, %hi(i)
-; CHECK-RV32-FD-NEXT: fld ft0, %lo(i)(a0)
-; CHECK-RV32-FD-NEXT: lui a0, %hi(h)
-; CHECK-RV32-FD-NEXT: fld ft1, %lo(h)(a0)
-; CHECK-RV32-FD-NEXT: fadd.d ft0, ft1, ft0
-; CHECK-RV32-FD-NEXT: lui a0, %hi(g)
-; CHECK-RV32-FD-NEXT: fsd ft0, %lo(g)(a0)
-; CHECK-RV32-FD-NEXT: fld ft1, 0(sp)
-; CHECK-RV32-FD-NEXT: fld ft0, 8(sp)
-; CHECK-RV32-FD-NEXT: lw a0, 20(sp)
-; CHECK-RV32-FD-NEXT: lw s0, 24(sp)
-; CHECK-RV32-FD-NEXT: lw ra, 28(sp)
-; CHECK-RV32-FD-NEXT: addi sp, sp, 32
-; CHECK-RV32-FD-NEXT: mret
+; CHECK-RV32-LABEL: foo_fp_double:
+; CHECK-RV32: # %bb.0:
+; CHECK-RV32-NEXT: addi sp, sp, -80
+; CHECK-RV32-NEXT: sw ra, 76(sp)
+; CHECK-RV32-NEXT: sw t0, 72(sp)
+; CHECK-RV32-NEXT: sw t1, 68(sp)
+; CHECK-RV32-NEXT: sw t2, 64(sp)
+; CHECK-RV32-NEXT: sw s0, 60(sp)
+; CHECK-RV32-NEXT: sw a0, 56(sp)
+; CHECK-RV32-NEXT: sw a1, 52(sp)
+; CHECK-RV32-NEXT: sw a2, 48(sp)
+; CHECK-RV32-NEXT: sw a3, 44(sp)
+; CHECK-RV32-NEXT: sw a4, 40(sp)
+; CHECK-RV32-NEXT: sw a5, 36(sp)
+; CHECK-RV32-NEXT: sw a6, 32(sp)
+; CHECK-RV32-NEXT: sw a7, 28(sp)
+; CHECK-RV32-NEXT: sw t3, 24(sp)
+; CHECK-RV32-NEXT: sw t4, 20(sp)
+; CHECK-RV32-NEXT: sw t5, 16(sp)
+; CHECK-RV32-NEXT: sw t6, 12(sp)
+; CHECK-RV32-NEXT: addi s0, sp, 80
+; CHECK-RV32-NEXT: lui a1, %hi(h)
+; CHECK-RV32-NEXT: lw a0, %lo(h)(a1)
+; CHECK-RV32-NEXT: addi a1, a1, %lo(h)
+; CHECK-RV32-NEXT: lw a1, 4(a1)
+; CHECK-RV32-NEXT: lui a3, %hi(i)
+; CHECK-RV32-NEXT: lw a2, %lo(i)(a3)
+; CHECK-RV32-NEXT: addi a3, a3, %lo(i)
+; CHECK-RV32-NEXT: lw a3, 4(a3)
+; CHECK-RV32-NEXT: call __adddf3
+; CHECK-RV32-NEXT: lui a2, %hi(g)
+; CHECK-RV32-NEXT: addi a3, a2, %lo(g)
+; CHECK-RV32-NEXT: sw a1, 4(a3)
+; CHECK-RV32-NEXT: sw a0, %lo(g)(a2)
+; CHECK-RV32-NEXT: lw t6, 12(sp)
+; CHECK-RV32-NEXT: lw t5, 16(sp)
+; CHECK-RV32-NEXT: lw t4, 20(sp)
+; CHECK-RV32-NEXT: lw t3, 24(sp)
+; CHECK-RV32-NEXT: lw a7, 28(sp)
+; CHECK-RV32-NEXT: lw a6, 32(sp)
+; CHECK-RV32-NEXT: lw a5, 36(sp)
+; CHECK-RV32-NEXT: lw a4, 40(sp)
+; CHECK-RV32-NEXT: lw a3, 44(sp)
+; CHECK-RV32-NEXT: lw a2, 48(sp)
+; CHECK-RV32-NEXT: lw a1, 52(sp)
+; CHECK-RV32-NEXT: lw a0, 56(sp)
+; CHECK-RV32-NEXT: lw s0, 60(sp)
+; CHECK-RV32-NEXT: lw t2, 64(sp)
+; CHECK-RV32-NEXT: lw t1, 68(sp)
+; CHECK-RV32-NEXT: lw t0, 72(sp)
+; CHECK-RV32-NEXT: lw ra, 76(sp)
+; CHECK-RV32-NEXT: addi sp, sp, 80
+; CHECK-RV32-NEXT: mret
+;
+; CHECK-RV32IF-LABEL: foo_fp_double:
+; CHECK-RV32IF: # %bb.0:
+; CHECK-RV32IF-NEXT: addi sp, sp, -208
+; CHECK-RV32IF-NEXT: sw ra, 204(sp)
+; CHECK-RV32IF-NEXT: sw t0, 200(sp)
+; CHECK-RV32IF-NEXT: sw t1, 196(sp)
+; CHECK-RV32IF-NEXT: sw t2, 192(sp)
+; CHECK-RV32IF-NEXT: sw s0, 188(sp)
+; CHECK-RV32IF-NEXT: sw a0, 184(sp)
+; CHECK-RV32IF-NEXT: sw a1, 180(sp)
+; CHECK-RV32IF-NEXT: sw a2, 176(sp)
+; CHECK-RV32IF-NEXT: sw a3, 172(sp)
+; CHECK-RV32IF-NEXT: sw a4, 168(sp)
+; CHECK-RV32IF-NEXT: sw a5, 164(sp)
+; CHECK-RV32IF-NEXT: sw a6, 160(sp)
+; CHECK-RV32IF-NEXT: sw a7, 156(sp)
+; CHECK-RV32IF-NEXT: sw t3, 152(sp)
+; CHECK-RV32IF-NEXT: sw t4, 148(sp)
+; CHECK-RV32IF-NEXT: sw t5, 144(sp)
+; CHECK-RV32IF-NEXT: sw t6, 140(sp)
+; CHECK-RV32IF-NEXT: fsw ft0, 136(sp)
+; CHECK-RV32IF-NEXT: fsw ft1, 132(sp)
+; CHECK-RV32IF-NEXT: fsw ft2, 128(sp)
+; CHECK-RV32IF-NEXT: fsw ft3, 124(sp)
+; CHECK-RV32IF-NEXT: fsw ft4, 120(sp)
+; CHECK-RV32IF-NEXT: fsw ft5, 116(sp)
+; CHECK-RV32IF-NEXT: fsw ft6, 112(sp)
+; CHECK-RV32IF-NEXT: fsw ft7, 108(sp)
+; CHECK-RV32IF-NEXT: fsw fa0, 104(sp)
+; CHECK-RV32IF-NEXT: fsw fa1, 100(sp)
+; CHECK-RV32IF-NEXT: fsw fa2, 96(sp)
+; CHECK-RV32IF-NEXT: fsw fa3, 92(sp)
+; CHECK-RV32IF-NEXT: fsw fa4, 88(sp)
+; CHECK-RV32IF-NEXT: fsw fa5, 84(sp)
+; CHECK-RV32IF-NEXT: fsw fa6, 80(sp)
+; CHECK-RV32IF-NEXT: fsw fa7, 76(sp)
+; CHECK-RV32IF-NEXT: fsw ft8, 72(sp)
+; CHECK-RV32IF-NEXT: fsw ft9, 68(sp)
+; CHECK-RV32IF-NEXT: fsw ft10, 64(sp)
+; CHECK-RV32IF-NEXT: fsw ft11, 60(sp)
+; CHECK-RV32IF-NEXT: fsw fs0, 56(sp)
+; CHECK-RV32IF-NEXT: fsw fs1, 52(sp)
+; CHECK-RV32IF-NEXT: fsw fs2, 48(sp)
+; CHECK-RV32IF-NEXT: fsw fs3, 44(sp)
+; CHECK-RV32IF-NEXT: fsw fs4, 40(sp)
+; CHECK-RV32IF-NEXT: fsw fs5, 36(sp)
+; CHECK-RV32IF-NEXT: fsw fs6, 32(sp)
+; CHECK-RV32IF-NEXT: fsw fs7, 28(sp)
+; CHECK-RV32IF-NEXT: fsw fs8, 24(sp)
+; CHECK-RV32IF-NEXT: fsw fs9, 20(sp)
+; CHECK-RV32IF-NEXT: fsw fs10, 16(sp)
+; CHECK-RV32IF-NEXT: fsw fs11, 12(sp)
+; CHECK-RV32IF-NEXT: addi s0, sp, 208
+; CHECK-RV32IF-NEXT: lui a1, %hi(h)
+; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1)
+; CHECK-RV32IF-NEXT: addi a1, a1, %lo(h)
+; CHECK-RV32IF-NEXT: lw a1, 4(a1)
+; CHECK-RV32IF-NEXT: lui a3, %hi(i)
+; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3)
+; CHECK-RV32IF-NEXT: addi a3, a3, %lo(i)
+; CHECK-RV32IF-NEXT: lw a3, 4(a3)
+; CHECK-RV32IF-NEXT: call __adddf3
+; CHECK-RV32IF-NEXT: lui a2, %hi(g)
+; CHECK-RV32IF-NEXT: addi a3, a2, %lo(g)
+; CHECK-RV32IF-NEXT: sw a1, 4(a3)
+; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2)
+; CHECK-RV32IF-NEXT: flw fs11, 12(sp)
+; CHECK-RV32IF-NEXT: flw fs10, 16(sp)
+; CHECK-RV32IF-NEXT: flw fs9, 20(sp)
+; CHECK-RV32IF-NEXT: flw fs8, 24(sp)
+; CHECK-RV32IF-NEXT: flw fs7, 28(sp)
+; CHECK-RV32IF-NEXT: flw fs6, 32(sp)
+; CHECK-RV32IF-NEXT: flw fs5, 36(sp)
+; CHECK-RV32IF-NEXT: flw fs4, 40(sp)
+; CHECK-RV32IF-NEXT: flw fs3, 44(sp)
+; CHECK-RV32IF-NEXT: flw fs2, 48(sp)
+; CHECK-RV32IF-NEXT: flw fs1, 52(sp)
+; CHECK-RV32IF-NEXT: flw fs0, 56(sp)
+; CHECK-RV32IF-NEXT: flw ft11, 60(sp)
+; CHECK-RV32IF-NEXT: flw ft10, 64(sp)
+; CHECK-RV32IF-NEXT: flw ft9, 68(sp)
+; CHECK-RV32IF-NEXT: flw ft8, 72(sp)
+; CHECK-RV32IF-NEXT: flw fa7, 76(sp)
+; CHECK-RV32IF-NEXT: flw fa6, 80(sp)
+; CHECK-RV32IF-NEXT: flw fa5, 84(sp)
+; CHECK-RV32IF-NEXT: flw fa4, 88(sp)
+; CHECK-RV32IF-NEXT: flw fa3, 92(sp)
+; CHECK-RV32IF-NEXT: flw fa2, 96(sp)
+; CHECK-RV32IF-NEXT: flw fa1, 100(sp)
+; CHECK-RV32IF-NEXT: flw fa0, 104(sp)
+; CHECK-RV32IF-NEXT: flw ft7, 108(sp)
+; CHECK-RV32IF-NEXT: flw ft6, 112(sp)
+; CHECK-RV32IF-NEXT: flw ft5, 116(sp)
+; CHECK-RV32IF-NEXT: flw ft4, 120(sp)
+; CHECK-RV32IF-NEXT: flw ft3, 124(sp)
+; CHECK-RV32IF-NEXT: flw ft2, 128(sp)
+; CHECK-RV32IF-NEXT: flw ft1, 132(sp)
+; CHECK-RV32IF-NEXT: flw ft0, 136(sp)
+; CHECK-RV32IF-NEXT: lw t6, 140(sp)
+; CHECK-RV32IF-NEXT: lw t5, 144(sp)
+; CHECK-RV32IF-NEXT: lw t4, 148(sp)
+; CHECK-RV32IF-NEXT: lw t3, 152(sp)
+; CHECK-RV32IF-NEXT: lw a7, 156(sp)
+; CHECK-RV32IF-NEXT: lw a6, 160(sp)
+; CHECK-RV32IF-NEXT: lw a5, 164(sp)
+; CHECK-RV32IF-NEXT: lw a4, 168(sp)
+; CHECK-RV32IF-NEXT: lw a3, 172(sp)
+; CHECK-RV32IF-NEXT: lw a2, 176(sp)
+; CHECK-RV32IF-NEXT: lw a1, 180(sp)
+; CHECK-RV32IF-NEXT: lw a0, 184(sp)
+; CHECK-RV32IF-NEXT: lw s0, 188(sp)
+; CHECK-RV32IF-NEXT: lw t2, 192(sp)
+; CHECK-RV32IF-NEXT: lw t1, 196(sp)
+; CHECK-RV32IF-NEXT: lw t0, 200(sp)
+; CHECK-RV32IF-NEXT: lw ra, 204(sp)
+; CHECK-RV32IF-NEXT: addi sp, sp, 208
+; CHECK-RV32IF-NEXT: mret
;
+; CHECK-RV32IFD-LABEL: foo_fp_double:
+; CHECK-RV32IFD: # %bb.0:
+; CHECK-RV32IFD-NEXT: addi sp, sp, -32
+; CHECK-RV32IFD-NEXT: sw ra, 28(sp)
+; CHECK-RV32IFD-NEXT: sw s0, 24(sp)
+; CHECK-RV32IFD-NEXT: sw a0, 20(sp)
+; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp)
+; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp)
+; CHECK-RV32IFD-NEXT: addi s0, sp, 32
+; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
+; CHECK-RV32IFD-NEXT: fld ft0, %lo(i)(a0)
+; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
+; CHECK-RV32IFD-NEXT: fld ft1, %lo(h)(a0)
+; CHECK-RV32IFD-NEXT: fadd.d ft0, ft1, ft0
+; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
+; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
+; CHECK-RV32IFD-NEXT: fld ft1, 0(sp)
+; CHECK-RV32IFD-NEXT: fld ft0, 8(sp)
+; CHECK-RV32IFD-NEXT: lw a0, 20(sp)
+; CHECK-RV32IFD-NEXT: lw s0, 24(sp)
+; CHECK-RV32IFD-NEXT: lw ra, 28(sp)
+; CHECK-RV32IFD-NEXT: addi sp, sp, 32
+; CHECK-RV32IFD-NEXT: mret
%1 = load double, double* @h
%2 = load double, double* @i
%add = fadd double %1, %2
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