diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86.td | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86Subtarget.h | 7 |
3 files changed, 12 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 100e192f181..94da74225b1 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -98,6 +98,9 @@ def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", "SHLD instruction is slow">; def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true", "PMULLD instruction is slow">; +def FeatureSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow", + "true", + "PMADDWD is slower than PMULLD">; // FIXME: This should not apply to CPUs that do not have SSE. def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", "IsUAMem16Slow", "true", @@ -460,8 +463,6 @@ def ProcIntelGLP : SubtargetFeature<"glp", "X86ProcFamily", "IntelGLP", "Intel Goldmont Plus processors">; def ProcIntelTRM : SubtargetFeature<"tremont", "X86ProcFamily", "IntelTRM", "Intel Tremont processors">; -def ProcIntelKNL : SubtargetFeature<"knl", "X86ProcFamily", - "IntelKNL", "Intel Knights Landing processors">; class Proc<string Name, list<SubtargetFeature> Features> : ProcessorModel<Name, GenericModel, Features>; @@ -845,19 +846,19 @@ def KNLFeatures : ProcessorFeatures<[], [ // FIXME: define KNL model class KnightsLandingProc<string Name> : ProcModel<Name, HaswellModel, KNLFeatures.Value, [ - ProcIntelKNL, FeatureSlowTwoMemOps, FeatureFastPartialYMMorZMMWrite, - FeatureHasFastGather + FeatureHasFastGather, + FeatureSlowPMADDWD ]>; def : KnightsLandingProc<"knl">; class KnightsMillProc<string Name> : ProcModel<Name, HaswellModel, KNLFeatures.Value, [ - ProcIntelKNL, FeatureSlowTwoMemOps, FeatureFastPartialYMMorZMMWrite, FeatureHasFastGather, + FeatureSlowPMADDWD, FeatureVPOPCNTDQ ]>; def : KnightsMillProc<"knm">; // TODO Add AVX5124FMAPS/AVX5124VNNIW features diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index f9f8fb4a419..1664a312aef 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -34361,7 +34361,7 @@ static SDValue combineMulToPMADDWD(SDNode *N, SelectionDAG &DAG, if (!Subtarget.hasSSE2()) return SDValue(); - if (Subtarget.getProcFamily() == X86Subtarget::IntelKNL) + if (Subtarget.isPMADDWDSlow()) return SDValue(); EVT VT = N->getValueType(0); diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index 47b51376e5e..b1103f823e7 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -60,8 +60,7 @@ public: IntelSLM, IntelGLM, IntelGLP, - IntelTRM, - IntelKNL, + IntelTRM }; protected: @@ -224,6 +223,9 @@ protected: // PMULUDQ. bool IsPMULLDSlow = false; + /// True if the PMADDWD instruction is slow compared to PMULLD. + bool IsPMADDWDSlow = false; + /// True if unaligned memory accesses of 16-bytes are slow. bool IsUAMem16Slow = false; @@ -613,6 +615,7 @@ public: bool hasPTWRITE() const { return HasPTWRITE; } bool isSHLDSlow() const { return IsSHLDSlow; } bool isPMULLDSlow() const { return IsPMULLDSlow; } + bool isPMADDWDSlow() const { return IsPMADDWDSlow; } bool isUnalignedMem16Slow() const { return IsUAMem16Slow; } bool isUnalignedMem32Slow() const { return IsUAMem32Slow; } int getGatherOverhead() const { return GatherOverhead; } |
