diff options
| -rw-r--r-- | llvm/lib/CodeGen/MIRParser/MIParser.cpp | 28 | ||||
| -rw-r--r-- | llvm/test/CodeGen/MIR/X86/register-operand-class.mir | 3 |
2 files changed, 19 insertions, 12 deletions
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index ff6d3097959..e302de26d1f 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -883,8 +883,8 @@ bool MIParser::parseRegister(unsigned &Reg, VRegInfo *&Info) { } bool MIParser::parseRegisterClassOrBank(VRegInfo &RegInfo) { - if (Token.isNot(MIToken::Identifier)) - return error("expected a register class or register bank name"); + if (Token.isNot(MIToken::Identifier) && Token.isNot(MIToken::underscore)) + return error("expected '_', register class, or register bank name"); StringRef::iterator Loc = Token.location(); StringRef Name = Token.stringValue(); @@ -914,26 +914,30 @@ bool MIParser::parseRegisterClassOrBank(VRegInfo &RegInfo) { llvm_unreachable("Unexpected register kind"); } - // Should be a register bank. - auto RBNameI = PFS.Names2RegBanks.find(Name); + // Should be a register bank or a generic register. + const RegisterBank *RegBank = nullptr; + if (Name != "_") { + auto RBNameI = PFS.Names2RegBanks.find(Name); + if (RBNameI == PFS.Names2RegBanks.end()) + return error(Loc, "expected '_', register class, or register bank name"); + RegBank = RBNameI->getValue(); + } + lex(); - if (RBNameI == PFS.Names2RegBanks.end()) - return error(Loc, "expected a register class or register bank name"); - const RegisterBank &RegBank = *RBNameI->getValue(); switch (RegInfo.Kind) { case VRegInfo::UNKNOWN: case VRegInfo::GENERIC: case VRegInfo::REGBANK: - RegInfo.Kind = VRegInfo::REGBANK; - if (RegInfo.Explicit && RegInfo.D.RegBank != &RegBank) - return error(Loc, "conflicting register banks"); - RegInfo.D.RegBank = &RegBank; + RegInfo.Kind = RegBank ? VRegInfo::REGBANK : VRegInfo::GENERIC; + if (RegInfo.Explicit && RegInfo.D.RegBank != RegBank) + return error(Loc, "conflicting generic register banks"); + RegInfo.D.RegBank = RegBank; RegInfo.Explicit = true; return false; case VRegInfo::NORMAL: - return error(Loc, "register class specification on normal register"); + return error(Loc, "register bank specification on normal register"); } llvm_unreachable("Unexpected register kind"); } diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir index d21622b68a4..63019daad7a 100644 --- a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir +++ b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir @@ -10,6 +10,7 @@ # CHECK: - { id: 1, class: gr64 } # CHECK: - { id: 2, class: gr32 } # CHECK: - { id: 3, class: gr16 } +# CHECK: - { id: 4, class: _ } name: func body: | bb.0: @@ -21,4 +22,6 @@ body: | %3 : gr16 = COPY %bx %bx = COPY %3 : gr16 + + %4 : _(s32) = COPY %edx ... |
