diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 8 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/trn1-diagnostics.s | 43 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/trn1.s | 56 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/trn2-diagnostics.s | 43 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/trn2.s | 56 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/uzp1-diagnostics.s | 43 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/uzp1.s | 56 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/uzp2-diagnostics.s | 43 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/uzp2.s | 56 |
9 files changed, 404 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index a6067af111a..87617de9fc2 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -536,9 +536,17 @@ let Predicates = [HasSVE] in { defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">; defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">; + defm UZP1_ZZZ : sve_int_perm_bin_perm_zz<0b010, "uzp1">; + defm UZP2_ZZZ : sve_int_perm_bin_perm_zz<0b011, "uzp2">; + defm TRN1_ZZZ : sve_int_perm_bin_perm_zz<0b100, "trn1">; + defm TRN2_ZZZ : sve_int_perm_bin_perm_zz<0b101, "trn2">; defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">; defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">; + defm UZP1_PPP : sve_int_perm_bin_perm_pp<0b010, "uzp1">; + defm UZP2_PPP : sve_int_perm_bin_perm_pp<0b011, "uzp2">; + defm TRN1_PPP : sve_int_perm_bin_perm_pp<0b100, "trn1">; + defm TRN2_PPP : sve_int_perm_bin_perm_pp<0b101, "trn2">; def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">; def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">; diff --git a/llvm/test/MC/AArch64/SVE/trn1-diagnostics.s b/llvm/test/MC/AArch64/SVE/trn1-diagnostics.s new file mode 100644 index 00000000000..9e318c1eacd --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/trn1-diagnostics.s @@ -0,0 +1,43 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// Invalid element kind. +trn1 z10.h, z22.h, z31.x +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: trn1 z10.h, z22.h, z31.x +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +trn1 z10.h, z3.h, z15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: trn1 z10.h, z3.h, z15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Too few operands +trn1 z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction +// CHECK-NEXT: trn1 z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// z32 is not a valid SVE data register +trn1 z1.s, z2.s, z32.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn1 z1.s, z2.s, z32.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// p16 is not a valid SVE predicate register +trn1 p1.s, p2.s, p16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn1 p1.s, p2.s, p16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining data and predicate registers as operands +trn1 z1.s, z2.s, p3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn1 z1.s, z2.s, p3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining predicate and data registers as operands +trn1 p1.s, p2.s, z3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn1 p1.s, p2.s, z3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/trn1.s b/llvm/test/MC/AArch64/SVE/trn1.s new file mode 100644 index 00000000000..b943b6d8f80 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/trn1.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +trn1 z31.b, z31.b, z31.b +// CHECK-INST: trn1 z31.b, z31.b, z31.b +// CHECK-ENCODING: [0xff,0x73,0x3f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 73 3f 05 <unknown> + +trn1 z31.h, z31.h, z31.h +// CHECK-INST: trn1 z31.h, z31.h, z31.h +// CHECK-ENCODING: [0xff,0x73,0x7f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 73 7f 05 <unknown> + +trn1 z31.s, z31.s, z31.s +// CHECK-INST: trn1 z31.s, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x73,0xbf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 73 bf 05 <unknown> + +trn1 z31.d, z31.d, z31.d +// CHECK-INST: trn1 z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x73,0xff,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 73 ff 05 <unknown> + +trn1 p15.b, p15.b, p15.b +// CHECK-INST: trn1 p15.b, p15.b, p15.b +// CHECK-ENCODING: [0xef,0x51,0x2f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 51 2f 05 <unknown> + +trn1 p15.s, p15.s, p15.s +// CHECK-INST: trn1 p15.s, p15.s, p15.s +// CHECK-ENCODING: [0xef,0x51,0xaf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 51 af 05 <unknown> + +trn1 p15.h, p15.h, p15.h +// CHECK-INST: trn1 p15.h, p15.h, p15.h +// CHECK-ENCODING: [0xef,0x51,0x6f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 51 6f 05 <unknown> + +trn1 p15.d, p15.d, p15.d +// CHECK-INST: trn1 p15.d, p15.d, p15.d +// CHECK-ENCODING: [0xef,0x51,0xef,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 51 ef 05 <unknown> diff --git a/llvm/test/MC/AArch64/SVE/trn2-diagnostics.s b/llvm/test/MC/AArch64/SVE/trn2-diagnostics.s new file mode 100644 index 00000000000..48b37bf3a18 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/trn2-diagnostics.s @@ -0,0 +1,43 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// Invalid element kind. +trn2 z6.h, z23.h, z31.x +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: trn2 z6.h, z23.h, z31.x +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +trn2 z0.h, z30.h, z24.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: trn2 z0.h, z30.h, z24.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Too few operands +trn2 z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction +// CHECK-NEXT: trn2 z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// z32 is not a valid SVE data register +trn2 z1.s, z2.s, z32.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn2 z1.s, z2.s, z32.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// p16 is not a valid SVE predicate register +trn2 p1.s, p2.s, p16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn2 p1.s, p2.s, p16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining data and predicate registers as operands +trn2 z1.s, z2.s, p3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn2 z1.s, z2.s, p3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining predicate and data registers as operands +trn2 p1.s, p2.s, z3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: trn2 p1.s, p2.s, z3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/trn2.s b/llvm/test/MC/AArch64/SVE/trn2.s new file mode 100644 index 00000000000..213d3b6ca83 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/trn2.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +trn2 z31.b, z31.b, z31.b +// CHECK-INST: trn2 z31.b, z31.b, z31.b +// CHECK-ENCODING: [0xff,0x77,0x3f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 77 3f 05 <unknown> + +trn2 z31.h, z31.h, z31.h +// CHECK-INST: trn2 z31.h, z31.h, z31.h +// CHECK-ENCODING: [0xff,0x77,0x7f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 77 7f 05 <unknown> + +trn2 z31.s, z31.s, z31.s +// CHECK-INST: trn2 z31.s, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x77,0xbf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 77 bf 05 <unknown> + +trn2 z31.d, z31.d, z31.d +// CHECK-INST: trn2 z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x77,0xff,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 77 ff 05 <unknown> + +trn2 p15.b, p15.b, p15.b +// CHECK-INST: trn2 p15.b, p15.b, p15.b +// CHECK-ENCODING: [0xef,0x55,0x2f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 55 2f 05 <unknown> + +trn2 p15.s, p15.s, p15.s +// CHECK-INST: trn2 p15.s, p15.s, p15.s +// CHECK-ENCODING: [0xef,0x55,0xaf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 55 af 05 <unknown> + +trn2 p15.h, p15.h, p15.h +// CHECK-INST: trn2 p15.h, p15.h, p15.h +// CHECK-ENCODING: [0xef,0x55,0x6f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 55 6f 05 <unknown> + +trn2 p15.d, p15.d, p15.d +// CHECK-INST: trn2 p15.d, p15.d, p15.d +// CHECK-ENCODING: [0xef,0x55,0xef,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 55 ef 05 <unknown> diff --git a/llvm/test/MC/AArch64/SVE/uzp1-diagnostics.s b/llvm/test/MC/AArch64/SVE/uzp1-diagnostics.s new file mode 100644 index 00000000000..3842d60a291 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/uzp1-diagnostics.s @@ -0,0 +1,43 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// Invalid element kind. +uzp1 z10.h, z22.h, z31.x +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: uzp1 z10.h, z22.h, z31.x +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +uzp1 z10.h, z3.h, z15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uzp1 z10.h, z3.h, z15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Too few operands +uzp1 z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction +// CHECK-NEXT: uzp1 z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// z32 is not a valid SVE data register +uzp1 z1.s, z2.s, z32.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uzp1 z1.s, z2.s, z32.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// p16 is not a valid SVE predicate register +uzp1 p1.s, p2.s, p16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uzp1 p1.s, p2.s, p16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining data and predicate registers as operands +uzp1 z1.s, z2.s, p3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uzp1 z1.s, z2.s, p3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining predicate and data registers as operands +uzp1 p1.s, p2.s, z3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uzp1 p1.s, p2.s, z3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uzp1.s b/llvm/test/MC/AArch64/SVE/uzp1.s new file mode 100644 index 00000000000..a8eeaa29ca3 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/uzp1.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uzp1 z31.b, z31.b, z31.b +// CHECK-INST: uzp1 z31.b, z31.b, z31.b +// CHECK-ENCODING: [0xff,0x6b,0x3f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 6b 3f 05 <unknown> + +uzp1 z31.h, z31.h, z31.h +// CHECK-INST: uzp1 z31.h, z31.h, z31.h +// CHECK-ENCODING: [0xff,0x6b,0x7f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 6b 7f 05 <unknown> + +uzp1 z31.s, z31.s, z31.s +// CHECK-INST: uzp1 z31.s, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x6b,0xbf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 6b bf 05 <unknown> + +uzp1 z31.d, z31.d, z31.d +// CHECK-INST: uzp1 z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x6b,0xff,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 6b ff 05 <unknown> + +uzp1 p15.b, p15.b, p15.b +// CHECK-INST: uzp1 p15.b, p15.b, p15.b +// CHECK-ENCODING: [0xef,0x49,0x2f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 49 2f 05 <unknown> + +uzp1 p15.s, p15.s, p15.s +// CHECK-INST: uzp1 p15.s, p15.s, p15.s +// CHECK-ENCODING: [0xef,0x49,0xaf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 49 af 05 <unknown> + +uzp1 p15.h, p15.h, p15.h +// CHECK-INST: uzp1 p15.h, p15.h, p15.h +// CHECK-ENCODING: [0xef,0x49,0x6f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 49 6f 05 <unknown> + +uzp1 p15.d, p15.d, p15.d +// CHECK-INST: uzp1 p15.d, p15.d, p15.d +// CHECK-ENCODING: [0xef,0x49,0xef,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 49 ef 05 <unknown> diff --git a/llvm/test/MC/AArch64/SVE/uzp2-diagnostics.s b/llvm/test/MC/AArch64/SVE/uzp2-diagnostics.s new file mode 100644 index 00000000000..ecb8b33ccba --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/uzp2-diagnostics.s @@ -0,0 +1,43 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// Invalid element kind. +uzp2 z6.h, z23.h, z31.x +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier +// CHECK-NEXT: uzp2 z6.h, z23.h, z31.x +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +uzp2 z0.h, z30.h, z24.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uzp2 z0.h, z30.h, z24.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Too few operands +uzp2 z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction +// CHECK-NEXT: uzp2 z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// z32 is not a valid SVE data register +uzp2 z1.s, z2.s, z32.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uzp2 z1.s, z2.s, z32.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// p16 is not a valid SVE predicate register +uzp2 p1.s, p2.s, p16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uzp2 p1.s, p2.s, p16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining data and predicate registers as operands +uzp2 z1.s, z2.s, p3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uzp2 z1.s, z2.s, p3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining predicate and data registers as operands +uzp2 p1.s, p2.s, z3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uzp2 p1.s, p2.s, z3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/uzp2.s b/llvm/test/MC/AArch64/SVE/uzp2.s new file mode 100644 index 00000000000..49573f1370c --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/uzp2.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +uzp2 z31.b, z31.b, z31.b +// CHECK-INST: uzp2 z31.b, z31.b, z31.b +// CHECK-ENCODING: [0xff,0x6f,0x3f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 6f 3f 05 <unknown> + +uzp2 z31.h, z31.h, z31.h +// CHECK-INST: uzp2 z31.h, z31.h, z31.h +// CHECK-ENCODING: [0xff,0x6f,0x7f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 6f 7f 05 <unknown> + +uzp2 z31.s, z31.s, z31.s +// CHECK-INST: uzp2 z31.s, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x6f,0xbf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 6f bf 05 <unknown> + +uzp2 z31.d, z31.d, z31.d +// CHECK-INST: uzp2 z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x6f,0xff,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 6f ff 05 <unknown> + +uzp2 p15.b, p15.b, p15.b +// CHECK-INST: uzp2 p15.b, p15.b, p15.b +// CHECK-ENCODING: [0xef,0x4d,0x2f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 4d 2f 05 <unknown> + +uzp2 p15.s, p15.s, p15.s +// CHECK-INST: uzp2 p15.s, p15.s, p15.s +// CHECK-ENCODING: [0xef,0x4d,0xaf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 4d af 05 <unknown> + +uzp2 p15.h, p15.h, p15.h +// CHECK-INST: uzp2 p15.h, p15.h, p15.h +// CHECK-ENCODING: [0xef,0x4d,0x6f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 4d 6f 05 <unknown> + +uzp2 p15.d, p15.d, p15.d +// CHECK-INST: uzp2 p15.d, p15.d, p15.d +// CHECK-ENCODING: [0xef,0x4d,0xef,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 4d ef 05 <unknown> |
