diff options
| -rw-r--r-- | llvm/include/llvm/Support/TargetOpcodes.def | 6 | ||||
| -rw-r--r-- | llvm/include/llvm/Target/GenericOpcodes.td | 15 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 20 |
4 files changed, 0 insertions, 51 deletions
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index dfd15ac22d9..9143e5b9dd9 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -268,12 +268,6 @@ HANDLE_TARGET_OPCODE(G_INTTOPTR) /// COPY is the relevant instruction. HANDLE_TARGET_OPCODE(G_BITCAST) -/// INTRINSIC trunc intrinsic. -HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) - -/// INTRINSIC round intrinsic. -HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) - /// Generic load (including anyext load) HANDLE_TARGET_OPCODE(G_LOAD) diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td index 2a2bef2fb38..90c121dfe3a 100644 --- a/llvm/include/llvm/Target/GenericOpcodes.td +++ b/llvm/include/llvm/Target/GenericOpcodes.td @@ -513,21 +513,6 @@ def G_FLOG2 : GenericInstruction { } //------------------------------------------------------------------------------ -// Opcodes for LLVM Intrinsics -//------------------------------------------------------------------------------ -def G_INTRINSIC_TRUNC : GenericInstruction { - let OutOperandList = (outs type0:$dst); - let InOperandList = (ins type0:$src1); - let hasSideEffects = 0; -} - -def G_INTRINSIC_ROUND : GenericInstruction { - let OutOperandList = (outs type0:$dst); - let InOperandList = (ins type0:$src1); - let hasSideEffects = 0; -} - -//------------------------------------------------------------------------------ // Memory ops //------------------------------------------------------------------------------ diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 3fda5cb9007..74f51cc7292 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -850,16 +850,6 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, .addDef(getOrCreateVReg(CI)) .addUse(getOrCreateVReg(*CI.getArgOperand(0))); return true; - case Intrinsic::trunc: - MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC) - .addDef(getOrCreateVReg(CI)) - .addUse(getOrCreateVReg(*CI.getArgOperand(0))); - return true; - case Intrinsic::round: - MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND) - .addDef(getOrCreateVReg(CI)) - .addUse(getOrCreateVReg(*CI.getArgOperand(0))); - return true; case Intrinsic::fma: MIRBuilder.buildInstr(TargetOpcode::G_FMA) .addDef(getOrCreateVReg(CI)) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index cf30558d5d6..75615e9d6c1 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1408,26 +1408,6 @@ define float @test_fabs_intrin(float %a) { ret float %res } -declare float @llvm.trunc.f32(float) -define float @test_intrinsic_trunc(float %a) { -; CHECK-LABEL: name: test_intrinsic_trunc -; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0 -; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[A]] -; CHECK: $s0 = COPY [[RES]] - %res = call float @llvm.trunc.f32(float %a) - ret float %res -} - -declare float @llvm.round.f32(float) -define float @test_intrinsic_round(float %a) { -; CHECK-LABEL: name: test_intrinsic_round -; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0 -; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[A]] -; CHECK: $s0 = COPY [[RES]] - %res = call float @llvm.round.f32(float %a) - ret float %res -} - declare i32 @llvm.ctlz.i32(i32, i1) define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) { ; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef |
