diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MipsMachineFunction.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/mul.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/srem.ll | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/udiv.ll | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/urem.ll | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/micromips-gp-rc.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/mips64fpldst.ll | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/tailcall/tailcall.ll | 4 |
9 files changed, 20 insertions, 46 deletions
diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/llvm/lib/Target/Mips/MipsMachineFunction.cpp index ddd3564c460..63034ecab93 100644 --- a/llvm/lib/Target/Mips/MipsMachineFunction.cpp +++ b/llvm/lib/Target/Mips/MipsMachineFunction.cpp @@ -40,11 +40,7 @@ unsigned MipsFunctionInfo::getGlobalBaseReg() { const TargetRegisterClass *RC = STI.inMips16Mode() ? &Mips::CPU16RegsRegClass - : STI.inMicroMipsMode() - ? STI.hasMips64() - ? &Mips::GPRMM16_64RegClass - : &Mips::GPRMM16RegClass - : static_cast<const MipsTargetMachine &>(MF.getTarget()) + : static_cast<const MipsTargetMachine &>(MF.getTarget()) .getABI() .IsN64() ? &Mips::GPR64RegClass diff --git a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll index 1562372ce9a..20853073dfa 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll @@ -268,7 +268,7 @@ entry: ; MM64R6: daddu $2, $[[T1]], $[[T0]] ; MM64R6-DAG: dmul $3, $5, $7 - ; MM32: lw $25, %call16(__multi3)($16) + ; MM32: lw $25, %call16(__multi3)($gp) %r = mul i128 %a, %b ret i128 %r diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll index defd25bb41a..ee2b212a9f2 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll @@ -172,7 +172,7 @@ entry: ; 64R6: ddiv $2, $4, $5 ; 64R6: teq $5, $zero, 7 - ; MM32: lw $25, %call16(__divdi3)($2) + ; MM32: lw $25, %call16(__divdi3)($gp) ; MM64: ddiv $2, $4, $5 ; MM64: teq $5, $zero, 7 @@ -184,15 +184,7 @@ entry: define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: sdiv_i128: - - ; GP32: lw $25, %call16(__divti3)($gp) - - ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) - ; 64R6: ld $25, %call16(__divti3)($gp) - - ; MM32: lw $25, %call16(__divti3)($16) - - ; MM64: ld $25, %call16(__divti3)($2) + ; ALL: l{{w|d}} $25, %call16(__divti3)($gp) %r = sdiv i128 %a, %b ret i128 %r diff --git a/llvm/test/CodeGen/Mips/llvm-ir/srem.ll b/llvm/test/CodeGen/Mips/llvm-ir/srem.ll index 42664d7457e..812c1056697 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/srem.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/srem.ll @@ -164,7 +164,7 @@ entry: ; 64R6: dmod $2, $4, $5 ; 64R6: teq $5, $zero, 7 - ; MM32: lw $25, %call16(__moddi3)($2) + ; MM32: lw $25, %call16(__moddi3)($gp) ; MM64: dmod $2, $4, $5 ; MM64: teq $5, $zero, 7 @@ -177,14 +177,7 @@ define signext i128 @srem_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: srem_i128: - ; GP32: lw $25, %call16(__modti3)($gp) - - ; GP64-NOT-R6: ld $25, %call16(__modti3)($gp) - ; 64R6: ld $25, %call16(__modti3)($gp) - - ; MM32: lw $25, %call16(__modti3)($16) - - ; MM64: ld $25, %call16(__modti3)($2) + ; ALL: l{{w|d}} $25, %call16(__modti3)($gp) %r = srem i128 %a, %b ret i128 %r diff --git a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll index 78ab36442a9..6e078fdedfc 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll @@ -134,7 +134,7 @@ entry: ; 64R6: ddivu $2, $4, $5 ; 64R6: teq $5, $zero, 7 - ; MM32: lw $25, %call16(__udivdi3)($2) + ; MM32: lw $25, %call16(__udivdi3)($gp) ; MM64: ddivu $2, $4, $5 ; MM64: teq $5, $zero, 7 @@ -147,14 +147,7 @@ define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: udiv_i128: - ; GP32: lw $25, %call16(__udivti3)($gp) - - ; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp) - ; 64-R6: ld $25, %call16(__udivti3)($gp) - - ; MM32: lw $25, %call16(__udivti3)($16) - - ; MM64: ld $25, %call16(__udivti3)($2) + ; ALL: l{{w|d}} $25, %call16(__udivti3)($gp) %r = udiv i128 %a, %b ret i128 %r diff --git a/llvm/test/CodeGen/Mips/llvm-ir/urem.ll b/llvm/test/CodeGen/Mips/llvm-ir/urem.ll index 160c126c7e3..3bc82ceecd2 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/urem.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/urem.ll @@ -190,7 +190,7 @@ entry: ; 64R6: dmodu $2, $4, $5 ; 64R6: teq $5, $zero, 7 - ; MM32: lw $25, %call16(__umoddi3)($2) + ; MM32: lw $25, %call16(__umoddi3)($gp) ; MM64: dmodu $2, $4, $5 ; MM64: teq $5, $zero, 7 @@ -208,9 +208,9 @@ entry: ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) ; 64R6: ld $25, %call16(__umodti3)($gp) - ; MM32: lw $25, %call16(__umodti3)($16) + ; MM32: lw $25, %call16(__umodti3)($gp) - ; MM64: ld $25, %call16(__umodti3)($2) + ; MM64: ld $25, %call16(__umodti3)($gp) %r = urem i128 %a, %b ret i128 %r diff --git a/llvm/test/CodeGen/Mips/micromips-gp-rc.ll b/llvm/test/CodeGen/Mips/micromips-gp-rc.ll index f139f7a8486..16e55c357db 100644 --- a/llvm/test/CodeGen/Mips/micromips-gp-rc.ll +++ b/llvm/test/CodeGen/Mips/micromips-gp-rc.ll @@ -14,5 +14,5 @@ entry: ; Function Attrs: noreturn declare void @exit(i32 signext) -; CHECK: move $gp, ${{[0-9]+}} +; CHECK: addu $gp, ${{[0-9]+}} diff --git a/llvm/test/CodeGen/Mips/mips64fpldst.ll b/llvm/test/CodeGen/Mips/mips64fpldst.ll index 564ffdd2f69..6fa506849ee 100644 --- a/llvm/test/CodeGen/Mips/mips64fpldst.ll +++ b/llvm/test/CodeGen/Mips/mips64fpldst.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 -; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 -; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64 @f0 = common global float 0.000000e+00, align 4 @d0 = common global double 0.000000e+00, align 8 diff --git a/llvm/test/CodeGen/Mips/tailcall/tailcall.ll b/llvm/test/CodeGen/Mips/tailcall/tailcall.ll index 3f04e1cf305..01a9b64ba63 100644 --- a/llvm/test/CodeGen/Mips/tailcall/tailcall.ll +++ b/llvm/test/CodeGen/Mips/tailcall/tailcall.ll @@ -176,7 +176,7 @@ entry: ; ALL-LABEL: caller8_1: ; PIC32: jalr $25 ; PIC32R6: jalr $25 -; PIC32MM: jalr $25 +; PIC32MM: jalr{{.*}} $25 ; STATIC32: jal ; PIC64: jalr $25 ; STATIC64: jal @@ -288,7 +288,7 @@ entry: ; ALL-LABEL: caller13: ; PIC32: jalr $25 ; PIC32R6: jalr $25 -; PIC32MM: jalr $25 +; PIC32MM: jalr{{.*}} $25 ; STATIC32: jal ; STATIC64: jal ; PIC64R6: jalr $25 |
