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-rw-r--r--llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp10
-rw-r--r--llvm/lib/Target/Mips/MicroMipsInstrInfo.td3
-rw-r--r--llvm/lib/Target/Mips/Mips32r6InstrInfo.td6
-rw-r--r--llvm/lib/Target/Mips/MipsInstrInfo.td16
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt2
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt2
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt10
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt10
-rw-r--r--llvm/test/MC/Mips/micromips/invalid-wrong-error.s1
-rw-r--r--llvm/test/MC/Mips/micromips/invalid.s4
-rw-r--r--llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s3
-rw-r--r--llvm/test/MC/Mips/micromips32r6/invalid.s16
-rw-r--r--llvm/test/MC/Mips/micromips32r6/valid.s22
-rw-r--r--llvm/test/MC/Mips/micromips64r6/invalid-wrong-error.s3
-rw-r--r--llvm/test/MC/Mips/micromips64r6/invalid.s16
-rw-r--r--llvm/test/MC/Mips/micromips64r6/valid.s22
16 files changed, 9 insertions, 137 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 9c121e56a84..cb3a5918c7e 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -1144,15 +1144,7 @@ public:
(R0 == Mips::A0 && R1 == Mips::S6) ||
(R0 == Mips::A0 && R1 == Mips::A1) ||
(R0 == Mips::A0 && R1 == Mips::A2) ||
- (R0 == Mips::A0 && R1 == Mips::A3) ||
- (R0 == Mips::A1_64 && R1 == Mips::A2_64) ||
- (R0 == Mips::A1_64 && R1 == Mips::A3_64) ||
- (R0 == Mips::A2_64 && R1 == Mips::A3_64) ||
- (R0 == Mips::A0_64 && R1 == Mips::S5_64) ||
- (R0 == Mips::A0_64 && R1 == Mips::S6_64) ||
- (R0 == Mips::A0_64 && R1 == Mips::A1_64) ||
- (R0 == Mips::A0_64 && R1 == Mips::A2_64) ||
- (R0 == Mips::A0_64 && R1 == Mips::A3_64))
+ (R0 == Mips::A0 && R1 == Mips::A3))
return true;
return false;
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index 1ae9b791980..4e92e1a9ad0 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -1025,9 +1025,6 @@ def : MipsInstAlias<"tltu $rs, $rt",
(TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tne $rs, $rt",
(TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
-def : MipsInstAlias<"rotr $rt, $imm",
- (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
-def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
def : MipsInstAlias<"slt $rs, $rt, $imm",
(SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
}
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index f249ff2d610..ea75cc5bba2 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -757,9 +757,7 @@ def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
-let AdditionalPredicates = [NotInMicroMips] in {
- def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
-}
+def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
@@ -793,9 +791,9 @@ def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
- def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
}
+def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
let AdditionalPredicates = [NotInMicroMips] in {
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index a16ca0f0241..ee92118a2ab 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -1707,13 +1707,11 @@ def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
SRLV_FM<7, 0>;
// Rotate Instructions
-let AdditionalPredicates = [NotInMicroMips] in {
- def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
- immZExt5>,
- SRA_FM<2, 1>, ISA_MIPS32R2;
- def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
- SRLV_FM<6, 1>, ISA_MIPS32R2;
-}
+def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
+ immZExt5>,
+ SRA_FM<2, 1>, ISA_MIPS32R2;
+def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
+ SRLV_FM<6, 1>, ISA_MIPS32R2;
/// Load and Store Instructions
/// aligned
@@ -2230,9 +2228,7 @@ def : MipsInstAlias<"beqz $rs,$offset",
(BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"beqzl $rs,$offset",
(BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
-let AdditionalPredicates = [NotInMicroMips] in {
- def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
-}
+def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
index bc81fc65b1a..d6c7de4e3a5 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
@@ -189,5 +189,3 @@
0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4)
0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4)
0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4)
-0x00 0x00 0x7c 0x8b # CHECK: syscall
-0x8c 0x01 0x7c 0x8b # CHECK: syscall 396
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
index 70fd8500b64..030afb36723 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
@@ -189,5 +189,3 @@
0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4)
0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4)
0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4)
-0x00 0x00 0x8b 0x7c # CHECK: syscall
-0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt
index 0d94e0385ca..b433305d88e 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt
@@ -21,7 +21,6 @@
0x29 0x82 # CHECK: lhu16 $3, 4($16)
0x09 0x94 # CHECK: lbu16 $3, 4($17)
0x09 0x9f # CHECK: lbu16 $3, -1($17)
-0x84 0x34 # CHECK: movep $5, $6, $2, $3
0x04 0xcc # CHECK: addu16 $6, $17, $4
0x44 0x21 # CHECK: and16 $16, $2
0x2e 0x56 # CHECK: andi16 $4, $5, 8
@@ -70,15 +69,6 @@
0x00 0x01 0xf3 0x7c # CHECK: eretnc
0x80 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xa0 0x05 0x01 0x00 # CHECK: jic $5, 256
-0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
-0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
-0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
-0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
-0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
-0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
-0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
-0x00 0x00 0x8b 0x7c # CHECK: syscall
-0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
0x78 0x48 0x00 0x43 # CHECK: lwpc $2, 268
0x00 0x43 0x26 0x0f # CHECK: lsa $2, $3, $4, 4
0x00 0xa4 0x19 0x58 # CHECK: mod $3, $4, $5
diff --git a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt
index f53747878a1..b7a84ebab6b 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt
@@ -21,16 +21,6 @@
0x45 0x2b # CHECK: jalr $9
0x45 0x23 # CHECK: jrc16 $9
0x44 0xb3 # CHECK: jrcaddiusp 20
-0x84 0x34 # CHECK: movep $5, $6, $2, $3
-0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
-0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
-0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
-0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
-0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
-0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
-0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
-0x00 0x00 0x8b 0x7c # CHECK: syscall
-0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4
0x42 0x03 0x00 0x04 # CHECK: dati $3, 4
diff --git a/llvm/test/MC/Mips/micromips/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips/invalid-wrong-error.s
index 8d39498bf90..36edaa63cb0 100644
--- a/llvm/test/MC/Mips/micromips/invalid-wrong-error.s
+++ b/llvm/test/MC/Mips/micromips/invalid-wrong-error.s
@@ -9,5 +9,4 @@
sdbbp -1 # CHECK: :[[@LINE]]:9: error: expected 20-bit unsigned immediate
sdbbp 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
- syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/micromips/invalid.s b/llvm/test/MC/Mips/micromips/invalid.s
index 19fe9cb9449..1141c1886b3 100644
--- a/llvm/test/MC/Mips/micromips/invalid.s
+++ b/llvm/test/MC/Mips/micromips/invalid.s
@@ -39,11 +39,7 @@
pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
prefe 0, -513($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset
prefe 0, 512($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset
- rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
- rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
- rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
- rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
sdbbp16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sdbbp16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sll $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
diff --git a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s
index 39f1731862c..df441ead705 100644
--- a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s
+++ b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s
@@ -25,6 +25,3 @@
tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
- syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
- syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
- syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s
index 1cbf251c0f0..7283ca18e2d 100644
--- a/llvm/test/MC/Mips/micromips32r6/invalid.s
+++ b/llvm/test/MC/Mips/micromips32r6/invalid.s
@@ -121,22 +121,6 @@
mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
- lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
- lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
- lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
- lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
- movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
- rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
- rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
- rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
- rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
- swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
- swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s
index 24344dad747..e4e307ff42a 100644
--- a/llvm/test/MC/Mips/micromips32r6/valid.s
+++ b/llvm/test/MC/Mips/micromips32r6/valid.s
@@ -65,28 +65,6 @@
lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0x78,0x48,0x00,0x43]
lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
- ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
- lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
- lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
- lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
- lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
- lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
- lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08]
- lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
- lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
- lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
- movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
- rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
- rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
- rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
- sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
- swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
- swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
- swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
- swm32 $16, $17, $ra, 64($sp) # CHECK: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40]
- swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
- syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c]
- syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58]
modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8]
mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]
diff --git a/llvm/test/MC/Mips/micromips64r6/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips64r6/invalid-wrong-error.s
index 90ded86f58a..88f73d3651f 100644
--- a/llvm/test/MC/Mips/micromips64r6/invalid-wrong-error.s
+++ b/llvm/test/MC/Mips/micromips64r6/invalid-wrong-error.s
@@ -27,6 +27,3 @@
tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
dins $2, $3, 32, 1 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
- syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
- syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
- syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/micromips64r6/invalid.s b/llvm/test/MC/Mips/micromips64r6/invalid.s
index c76f1d396fa..a6efc52ae95 100644
--- a/llvm/test/MC/Mips/micromips64r6/invalid.s
+++ b/llvm/test/MC/Mips/micromips64r6/invalid.s
@@ -146,22 +146,6 @@
dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
- lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
- lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
- lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
- lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
- movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
- rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
- rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
- rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
- rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
- swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
- swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
- swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
diff --git a/llvm/test/MC/Mips/micromips64r6/valid.s b/llvm/test/MC/Mips/micromips64r6/valid.s
index cf4eaf1308b..8cdc448405e 100644
--- a/llvm/test/MC/Mips/micromips64r6/valid.s
+++ b/llvm/test/MC/Mips/micromips64r6/valid.s
@@ -28,28 +28,6 @@ a:
lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
- movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
- ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
- lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
- lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
- lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
- lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
- lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
- lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08]
- lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
- lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
- lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
- rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
- rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
- rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
- sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
- swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
- swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
- swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
- swm32 $16, $17, $ra, 64($sp) # CHECK: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40]
- swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
- syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c]
- syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x18]
dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x58]
ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0xa4,0x19,0x98]
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