diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 19 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/sve2-intrinsics-while.ll | 309 |
2 files changed, 318 insertions, 10 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index e374ce4edd7..571dc775e87 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1521,16 +1521,15 @@ let Predicates = [HasSVE2] in { defm TBX_ZZZ : sve2_int_perm_tbx<"tbx">; // SVE2 integer compare scalar count and limit - defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege", null_frag>; - defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt", null_frag>; - defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs", null_frag>; - defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi", null_frag>; - - defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege", null_frag>; - defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt", null_frag>; - defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs", null_frag>; - defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi", null_frag>; - + defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege", int_aarch64_sve_whilege>; + defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt", int_aarch64_sve_whilegt>; + defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs", int_aarch64_sve_whilehs>; + defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi", int_aarch64_sve_whilehi>; + + defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege", int_aarch64_sve_whilege>; + defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt", int_aarch64_sve_whilegt>; + defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs", int_aarch64_sve_whilehs>; + defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi", int_aarch64_sve_whilehi>; // SVE2 pointer conflict compare defm WHILEWR_PXX : sve2_int_while_rr<0b0, "whilewr">; diff --git a/llvm/test/CodeGen/AArch64/sve2-intrinsics-while.ll b/llvm/test/CodeGen/AArch64/sve2-intrinsics-while.ll new file mode 100644 index 00000000000..e53c981b64d --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve2-intrinsics-while.ll @@ -0,0 +1,309 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s + +; +; WHILEGE +; + +define <vscale x 16 x i1> @whilege_b_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilege_b_ww: +; CHECK: whilege p0.b, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilege.nxv16i1.i32(i32 %a, i32 %b) + ret <vscale x 16 x i1> %out +} + +define <vscale x 16 x i1> @whilege_b_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilege_b_xx: +; CHECK: whilege p0.b, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilege.nxv16i1.i64(i64 %a, i64 %b) + ret <vscale x 16 x i1> %out +} + +define <vscale x 8 x i1> @whilege_h_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilege_h_ww: +; CHECK: whilege p0.h, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilege.nxv8i1.i32(i32 %a, i32 %b) + ret <vscale x 8 x i1> %out +} + +define <vscale x 8 x i1> @whilege_h_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilege_h_xx: +; CHECK: whilege p0.h, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilege.nxv8i1.i64(i64 %a, i64 %b) + ret <vscale x 8 x i1> %out +} + +define <vscale x 4 x i1> @whilege_s_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilege_s_ww: +; CHECK: whilege p0.s, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i32(i32 %a, i32 %b) + ret <vscale x 4 x i1> %out +} + +define <vscale x 4 x i1> @whilege_s_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilege_s_xx: +; CHECK: whilege p0.s, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i64(i64 %a, i64 %b) + ret <vscale x 4 x i1> %out +} + +define <vscale x 2 x i1> @whilege_d_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilege_d_ww: +; CHECK: whilege p0.d, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilege.nxv2i1.i32(i32 %a, i32 %b) + ret <vscale x 2 x i1> %out +} + +define <vscale x 2 x i1> @whilege_d_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilege_d_xx: +; CHECK: whilege p0.d, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilege.nxv2i1.i64(i64 %a, i64 %b) + ret <vscale x 2 x i1> %out +} + +; +; WHILEHS +; + +define <vscale x 16 x i1> @whilehs_b_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilehs_b_ww: +; CHECK: whilehs p0.b, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehs.nxv16i1.i32(i32 %a, i32 %b) + ret <vscale x 16 x i1> %out +} + +define <vscale x 16 x i1> @whilehs_b_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilehs_b_xx: +; CHECK: whilehs p0.b, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehs.nxv16i1.i64(i64 %a, i64 %b) + ret <vscale x 16 x i1> %out +} + +define <vscale x 8 x i1> @whilehs_h_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilehs_h_ww: +; CHECK: whilehs p0.h, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehs.nxv8i1.i32(i32 %a, i32 %b) + ret <vscale x 8 x i1> %out +} + +define <vscale x 8 x i1> @whilehs_h_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilehs_h_xx: +; CHECK: whilehs p0.h, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehs.nxv8i1.i64(i64 %a, i64 %b) + ret <vscale x 8 x i1> %out +} + +define <vscale x 4 x i1> @whilehs_s_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilehs_s_ww: +; CHECK: whilehs p0.s, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i32(i32 %a, i32 %b) + ret <vscale x 4 x i1> %out +} + +define <vscale x 4 x i1> @whilehs_s_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilehs_s_xx: +; CHECK: whilehs p0.s, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i64(i64 %a, i64 %b) + ret <vscale x 4 x i1> %out +} + +define <vscale x 2 x i1> @whilehs_d_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilehs_d_ww: +; CHECK: whilehs p0.d, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehs.nxv2i1.i32(i32 %a, i32 %b) + ret <vscale x 2 x i1> %out +} + +define <vscale x 2 x i1> @whilehs_d_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilehs_d_xx: +; CHECK: whilehs p0.d, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehs.nxv2i1.i64(i64 %a, i64 %b) + ret <vscale x 2 x i1> %out +} + +; +; WHILEGT +; + +define <vscale x 16 x i1> @whilegt_b_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilegt_b_ww: +; CHECK: whilegt p0.b, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilegt.nxv16i1.i32(i32 %a, i32 %b) + ret <vscale x 16 x i1> %out +} + +define <vscale x 16 x i1> @whilegt_b_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilegt_b_xx: +; CHECK: whilegt p0.b, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilegt.nxv16i1.i64(i64 %a, i64 %b) + ret <vscale x 16 x i1> %out +} + +define <vscale x 8 x i1> @whilegt_h_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilegt_h_ww: +; CHECK: whilegt p0.h, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilegt.nxv8i1.i32(i32 %a, i32 %b) + ret <vscale x 8 x i1> %out +} + +define <vscale x 8 x i1> @whilegt_h_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilegt_h_xx: +; CHECK: whilegt p0.h, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilegt.nxv8i1.i64(i64 %a, i64 %b) + ret <vscale x 8 x i1> %out +} + +define <vscale x 4 x i1> @whilegt_s_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilegt_s_ww: +; CHECK: whilegt p0.s, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i32(i32 %a, i32 %b) + ret <vscale x 4 x i1> %out +} + +define <vscale x 4 x i1> @whilegt_s_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilegt_s_xx: +; CHECK: whilegt p0.s, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i64(i64 %a, i64 %b) + ret <vscale x 4 x i1> %out +} + +define <vscale x 2 x i1> @whilegt_d_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilegt_d_ww: +; CHECK: whilegt p0.d, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilegt.nxv2i1.i32(i32 %a, i32 %b) + ret <vscale x 2 x i1> %out +} + +define <vscale x 2 x i1> @whilegt_d_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilegt_d_xx: +; CHECK: whilegt p0.d, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilegt.nxv2i1.i64(i64 %a, i64 %b) + ret <vscale x 2 x i1> %out +} + +; +; WHILEHI +; + +define <vscale x 16 x i1> @whilehi_b_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilehi_b_ww: +; CHECK: whilehi p0.b, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehi.nxv16i1.i32(i32 %a, i32 %b) + ret <vscale x 16 x i1> %out +} + +define <vscale x 16 x i1> @whilehi_b_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilehi_b_xx: +; CHECK: whilehi p0.b, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehi.nxv16i1.i64(i64 %a, i64 %b) + ret <vscale x 16 x i1> %out +} + +define <vscale x 8 x i1> @whilehi_h_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilehi_h_ww: +; CHECK: whilehi p0.h, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehi.nxv8i1.i32(i32 %a, i32 %b) + ret <vscale x 8 x i1> %out +} + +define <vscale x 8 x i1> @whilehi_h_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilehi_h_xx: +; CHECK: whilehi p0.h, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehi.nxv8i1.i64(i64 %a, i64 %b) + ret <vscale x 8 x i1> %out +} + +define <vscale x 4 x i1> @whilehi_s_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilehi_s_ww: +; CHECK: whilehi p0.s, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i32(i32 %a, i32 %b) + ret <vscale x 4 x i1> %out +} + +define <vscale x 4 x i1> @whilehi_s_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilehi_s_xx: +; CHECK: whilehi p0.s, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i64(i64 %a, i64 %b) + ret <vscale x 4 x i1> %out +} + +define <vscale x 2 x i1> @whilehi_d_ww(i32 %a, i32 %b) { +; CHECK-LABEL: whilehi_d_ww: +; CHECK: whilehi p0.d, w0, w1 +; CHECK-NEXT: ret + %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehi.nxv2i1.i32(i32 %a, i32 %b) + ret <vscale x 2 x i1> %out +} + +define <vscale x 2 x i1> @whilehi_d_xx(i64 %a, i64 %b) { +; CHECK-LABEL: whilehi_d_xx: +; CHECK: whilehi p0.d, x0, x1 +; CHECK-NEXT: ret + %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehi.nxv2i1.i64(i64 %a, i64 %b) + ret <vscale x 2 x i1> %out +} + +declare <vscale x 16 x i1> @llvm.aarch64.sve.whilege.nxv16i1.i32(i32, i32) +declare <vscale x 16 x i1> @llvm.aarch64.sve.whilege.nxv16i1.i64(i64, i64) +declare <vscale x 8 x i1> @llvm.aarch64.sve.whilege.nxv8i1.i32(i32, i32) +declare <vscale x 8 x i1> @llvm.aarch64.sve.whilege.nxv8i1.i64(i64, i64) +declare <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i32(i32, i32) +declare <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i64(i64, i64) +declare <vscale x 2 x i1> @llvm.aarch64.sve.whilege.nxv2i1.i32(i32, i32) +declare <vscale x 2 x i1> @llvm.aarch64.sve.whilege.nxv2i1.i64(i64, i64) + +declare <vscale x 16 x i1> @llvm.aarch64.sve.whilehs.nxv16i1.i32(i32, i32) +declare <vscale x 16 x i1> @llvm.aarch64.sve.whilehs.nxv16i1.i64(i64, i64) +declare <vscale x 8 x i1> @llvm.aarch64.sve.whilehs.nxv8i1.i32(i32, i32) +declare <vscale x 8 x i1> @llvm.aarch64.sve.whilehs.nxv8i1.i64(i64, i64) +declare <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i32(i32, i32) +declare <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i64(i64, i64) +declare <vscale x 2 x i1> @llvm.aarch64.sve.whilehs.nxv2i1.i32(i32, i32) +declare <vscale x 2 x i1> @llvm.aarch64.sve.whilehs.nxv2i1.i64(i64, i64) + +declare <vscale x 16 x i1> @llvm.aarch64.sve.whilegt.nxv16i1.i32(i32, i32) +declare <vscale x 16 x i1> @llvm.aarch64.sve.whilegt.nxv16i1.i64(i64, i64) +declare <vscale x 8 x i1> @llvm.aarch64.sve.whilegt.nxv8i1.i32(i32, i32) +declare <vscale x 8 x i1> @llvm.aarch64.sve.whilegt.nxv8i1.i64(i64, i64) +declare <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i32(i32, i32) +declare <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i64(i64, i64) +declare <vscale x 2 x i1> @llvm.aarch64.sve.whilegt.nxv2i1.i32(i32, i32) +declare <vscale x 2 x i1> @llvm.aarch64.sve.whilegt.nxv2i1.i64(i64, i64) + +declare <vscale x 16 x i1> @llvm.aarch64.sve.whilehi.nxv16i1.i32(i32, i32) +declare <vscale x 16 x i1> @llvm.aarch64.sve.whilehi.nxv16i1.i64(i64, i64) +declare <vscale x 8 x i1> @llvm.aarch64.sve.whilehi.nxv8i1.i32(i32, i32) +declare <vscale x 8 x i1> @llvm.aarch64.sve.whilehi.nxv8i1.i64(i64, i64) +declare <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i32(i32, i32) +declare <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i64(i64, i64) +declare <vscale x 2 x i1> @llvm.aarch64.sve.whilehi.nxv2i1.i32(i32, i32) +declare <vscale x 2 x i1> @llvm.aarch64.sve.whilehi.nxv2i1.i64(i64, i64) |
