diff options
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 20 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll | 19 |
2 files changed, 34 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 7999d0fca0e..3f2826cda63 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -890,9 +890,11 @@ bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) { MachinePointerInfo Ptr(LI.getPointerOperand(), Offsets[i] / 8); unsigned BaseAlign = getMemOpAlignment(LI); + AAMDNodes AAMetadata; + LI.getAAMetadata(AAMetadata); auto MMO = MF->getMachineMemOperand( Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8, - MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), Ranges, + MinAlign(BaseAlign, Offsets[i] / 8), AAMetadata, Ranges, LI.getSyncScopeID(), LI.getOrdering()); MIRBuilder.buildLoad(Regs[i], Addr, *MMO); } @@ -931,9 +933,11 @@ bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) { MachinePointerInfo Ptr(SI.getPointerOperand(), Offsets[i] / 8); unsigned BaseAlign = getMemOpAlignment(SI); + AAMDNodes AAMetadata; + SI.getAAMetadata(AAMetadata); auto MMO = MF->getMachineMemOperand( Ptr, Flags, (MRI->getType(Vals[i]).getSizeInBits() + 7) / 8, - MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr, + MinAlign(BaseAlign, Offsets[i] / 8), AAMetadata, nullptr, SI.getSyncScopeID(), SI.getOrdering()); MIRBuilder.buildStore(Vals[i], Addr, *MMO); } @@ -1959,11 +1963,14 @@ bool IRTranslator::translateAtomicCmpXchg(const User &U, Register Cmp = getOrCreateVReg(*I.getCompareOperand()); Register NewVal = getOrCreateVReg(*I.getNewValOperand()); + AAMDNodes AAMetadata; + I.getAAMetadata(AAMetadata); + MIRBuilder.buildAtomicCmpXchgWithSuccess( OldValRes, SuccessRes, Addr, Cmp, NewVal, *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()), Flags, DL->getTypeStoreSize(ValType), - getMemOpAlignment(I), AAMDNodes(), nullptr, + getMemOpAlignment(I), AAMetadata, nullptr, I.getSyncScopeID(), I.getSuccessOrdering(), I.getFailureOrdering())); return true; @@ -2028,12 +2035,15 @@ bool IRTranslator::translateAtomicRMW(const User &U, break; } + AAMDNodes AAMetadata; + I.getAAMetadata(AAMetadata); + MIRBuilder.buildAtomicRMW( Opcode, Res, Addr, Val, *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()), Flags, DL->getTypeStoreSize(ResType), - getMemOpAlignment(I), AAMDNodes(), nullptr, - I.getSyncScopeID(), I.getOrdering())); + getMemOpAlignment(I), AAMetadata, + nullptr, I.getSyncScopeID(), I.getOrdering())); return true; } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll new file mode 100644 index 00000000000..bbf57470397 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll @@ -0,0 +1,19 @@ +; RUN: llc -O0 -mtriple=aarch64-unknown-unknown -stop-after=irtranslator -o - %s | FileCheck %s + +target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + +define void @snork() { +bb: + %tmp1 = getelementptr i16, i16* null, i64 0 + %tmp5 = getelementptr i16, i16* null, i64 2 + %tmp6 = load i16, i16* %tmp1, align 2, !tbaa !0 + store i16 %tmp6, i16* %tmp5, align 2, !tbaa !0 + ; CHECK: %5:_(s16) = G_LOAD %2(p0) :: (load 2 from %ir.tmp1, !tbaa !0) + ; CHECK: G_STORE %5(s16), %4(p0) :: (store 2 into %ir.tmp5, !tbaa !0) + ret void +} + +!0 = !{!1, !1, i64 0} +!1 = !{!"short", !2, i64 0} +!2 = !{!"omnipotent char", !3, i64 0} +!3 = !{!"Simple C/C++ TBAA"} |
