diff options
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 18 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/RISCV/invalid-instruction.txt | 13 |
3 files changed, 33 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 69afa4b9831..d5b8b389ae3 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -212,6 +212,15 @@ static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, } template <unsigned N> +static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + if (Imm == 0) + return MCDisassembler::Fail; + return decodeUImmOperand<N>(Inst, Imm, Address, Decoder); +} + +template <unsigned N> static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { assert(isUInt<N>(Imm) && "Invalid immediate"); @@ -222,6 +231,15 @@ static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, } template <unsigned N> +static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm, + int64_t Address, + const void *Decoder) { + if (Imm == 0) + return MCDisassembler::Fail; + return decodeSImmOperand<N>(Inst, Imm, Address, Decoder); +} + +template <unsigned N> static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td index eae94419772..c85a634fc5b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -167,7 +167,7 @@ def uimm10_lsb00nonzero : Operand<XLenVT>, [{return isShiftedUInt<8, 2>(Imm) && (Imm != 0);}]> { let ParserMatchClass = UImmAsmOperand<10, "Lsb00NonZero">; let EncoderMethod = "getImmOpValue"; - let DecoderMethod = "decodeUImmOperand<10>"; + let DecoderMethod = "decodeUImmNonZeroOperand<10>"; let MCOperandPredicate = [{ int64_t Imm; if (!MCOp.evaluateAsConstantImm(Imm)) @@ -182,7 +182,7 @@ def simm10_lsb0000nonzero : Operand<XLenVT>, [{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> { let ParserMatchClass = SImmAsmOperand<10, "Lsb0000NonZero">; let EncoderMethod = "getImmOpValue"; - let DecoderMethod = "decodeSImmOperand<10>"; + let DecoderMethod = "decodeSImmNonZeroOperand<10>"; let MCOperandPredicate = [{ int64_t Imm; if (!MCOp.evaluateAsConstantImm(Imm)) diff --git a/llvm/test/MC/Disassembler/RISCV/invalid-instruction.txt b/llvm/test/MC/Disassembler/RISCV/invalid-instruction.txt new file mode 100644 index 00000000000..1bf033cbe3e --- /dev/null +++ b/llvm/test/MC/Disassembler/RISCV/invalid-instruction.txt @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+c < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -disassemble -triple=riscv64 -mattr=+c < %s 2>&1 | FileCheck %s +# +# Test generated by a LLVM MC Disassembler Protocol Buffer Fuzzer +# for the RISC-V assembly language. + +# This should not decode as c.addi4spn with 0 imm when compression is enabled. +[0x00 0x00] +# CHECK: warning: invalid instruction encoding + +# This should not decode as c.addi16sp with 0 imm when compression is enabled. +[0x01 0x61] +# CHECK: warning: invalid instruction encoding |
