diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h | 1 |
2 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index 5f70c4b94a1..07a29ebb364 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -51,6 +51,15 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) assert(RBFPR.getSize() == 512 && "FPRs should hold up to 512-bit via QQQQ sequence"); + // Initialize the CCR bank. + createRegisterBank(AArch64::CCRRegBankID, "CCR"); + addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI); + const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID); + (void)RBCCR; + assert(RBCCR.contains(*TRI.getRegClass(AArch64::CCRRegClassID)) && + "Class not added?"); + assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit"); + verify(TRI); } @@ -94,6 +103,8 @@ const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass( case AArch64::WSeqPairsClassRegClassID: case AArch64::XSeqPairsClassRegClassID: return getRegBank(AArch64::FPRRegBankID); + case AArch64::CCRRegClassID: + return getRegBank(AArch64::CCRRegBankID); default: llvm_unreachable("Register class not supported"); } diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h index c58d4520c09..156f9a0b7d5 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.h @@ -24,6 +24,7 @@ namespace AArch64 { enum { GPRRegBankID = 0, /// General Purpose Registers: W, X. FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q. + CCRRegBankID = 2, /// Conditional register: NZCV. NumRegisterBanks }; } // End AArch64 namespace. |
