diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 3 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/alu32_alu.txt | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt | 20 |
3 files changed, 15 insertions, 14 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 1399480c1d7..ab05ec51b3f 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -610,7 +610,8 @@ def C2_cmovenewif : T_TFRI_Pred<1, 1>; let InputType = "imm", isExtendable = 1, isExtentSigned = 1, CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0, isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1, - isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in + isPredicated = 0, isPredicable = 1, isReMaterializable = 1, + isCodeGenOnly = 0 in def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16", [(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredRel { diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_alu.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_alu.txt index 4ae3f9693e0..b5aaffe480e 100644 --- a/llvm/test/MC/Disassembler/Hexagon/alu32_alu.txt +++ b/llvm/test/MC/Disassembler/Hexagon/alu32_alu.txt @@ -31,10 +31,10 @@ 0x15 0xc0 0x31 0x71 # CHECK: r17.l = #21 0xf1 0xff 0x5f 0x78 -# CHECK: { r17 = #32767 } +# CHECK: r17 = #32767 0xf1 0xff 0xdf 0x78 -# CHECK: { r17 = #-1 } +# CHECK: r17 = ##65535 0x11 0xc0 0x75 0x70 -# CHECK: { r17 = r21 } +# CHECK: r17 = r21 0x11 0xc0 0xd5 0x70 # CHECK: r17 = zxth(r21) diff --git a/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt b/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt index c671760e6d3..869a429da73 100644 --- a/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt +++ b/llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt @@ -17,11 +17,11 @@ # CHECK: p3 = r5 # CHECK-NEXT: if (!p3.new) r17:16 = combine(r21, r31) 0x03 0x40 0x45 0x85 0x70 0xff 0x15 0xfd -# CHECK: { p3 = r5 -# CHECK-NEXT: if (p3.new) r17:16 = combine(r21, r31) } +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17:16 = combine(r21, r31) 0x03 0x40 0x45 0x85 0xf0 0xff 0x15 0xfd -# CHECK: { p3 = r5 -# CHECK-NEXT: if (!p3.new) r17:16 = combine(r21, r31) } +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17:16 = combine(r21, r31) 0x71 0xdf 0x15 0xf9 # CHECK: if (p3) r17 = and(r21, r31) 0x71 0xdf 0x35 0xf9 @@ -35,15 +35,15 @@ 0x11 0xe3 0xf5 0x70 # CHECK: if (p3) r17 = sxth(r21) 0xb1 0xc2 0x60 0x7e -# CHECK: { if (p3) r17 = #21 } +# CHECK: if (p3) r17 = #21 0xb1 0xc2 0xe0 0x7e -# CHECK: { if (!p3) r17 = #21 } +# CHECK: if (!p3) r17 = #21 0x03 0x40 0x45 0x85 0xb1 0xe2 0x60 0x7e -# CHECK: { p3 = r5 -# CHECK-NEXT: if (p3.new) r17 = #21 } +# CHECK: p3 = r5 +# CHECK-NEXT: if (p3.new) r17 = #21 0x03 0x40 0x45 0x85 0xb1 0xe2 0xe0 0x7e -# CHECK: { p3 = r5 -# CHECK-NEXT: if (!p3.new) r17 = #21 } +# CHECK: p3 = r5 +# CHECK-NEXT: if (!p3.new) r17 = #21 0x11 0xe3 0x95 0x70 # CHECK: if (p3) r17 = zxtb(r21) 0x11 0xe3 0xd5 0x70 |
