diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index 40d04e7658d..5576ce643c8 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -159,8 +159,6 @@ getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); - using RegIter = TargetRegisterClass::const_iterator; - for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I) Reserved.set(ReservedGPR32[I]); @@ -182,14 +180,12 @@ getReservedRegs(const MachineFunction &MF) const { if (Subtarget.isFP64bit()) { // Reserve all registers in AFGR64. - for (RegIter Reg = Mips::AFGR64RegClass.begin(), - EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) - Reserved.set(*Reg); + for (MCPhysReg Reg : Mips::AFGR64RegClass) + Reserved.set(Reg); } else { // Reserve all registers in FGR64. - for (RegIter Reg = Mips::FGR64RegClass.begin(), - EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg) - Reserved.set(*Reg); + for (MCPhysReg Reg : Mips::FGR64RegClass) + Reserved.set(Reg); } // Reserve FP if this function should have a dedicated frame pointer register. if (Subtarget.getFrameLowering()->hasFP(MF)) { |
