diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZShortenInst.cpp | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index b9e1a268626..a55f4499122 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -9848,7 +9848,7 @@ SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N, std::list<HandleSDNode> PromOpHandles; for (auto &PromOp : PromOps) - PromOpHandles.emplace_back(PromOp); + PromOpHandles.emplace_back(PromOp); // Replace all operations (these are all the same, but have a different // (i1) return type). DAG.getNode will validate that the types of @@ -10102,7 +10102,7 @@ SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N, std::list<HandleSDNode> PromOpHandles; for (auto &PromOp : PromOps) - PromOpHandles.emplace_back(PromOp); + PromOpHandles.emplace_back(PromOp); // Replace all operations (these are all the same, but have a different // (promoted) return type). DAG.getNode will validate that the types of @@ -10555,7 +10555,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, if (Bitcast->getOpcode() != ISD::BITCAST || Bitcast->getValueType(0) != MVT::f32) return false; - if (Bitcast2->getOpcode() != ISD::BITCAST || + if (Bitcast2->getOpcode() != ISD::BITCAST || Bitcast2->getValueType(0) != MVT::f32) return false; diff --git a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp index 65bd3f0a214..7f26a3519e5 100644 --- a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp +++ b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp @@ -72,9 +72,9 @@ static void tieOpsIfNeeded(MachineInstr &MI) { // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH // are the halfword immediate loads for the same word. Try to use one of them -// instead of IIxF. -bool SystemZShortenInst::shortenIIF(MachineInstr &MI, - unsigned LLIxL, unsigned LLIxH) { +// instead of IIxF. +bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned LLIxL, + unsigned LLIxH) { unsigned Reg = MI.getOperand(0).getReg(); // The new opcode will clear the other half of the GR64 reg, so // cancel if that is live. |
