diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFPU.td | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll | 13 |
2 files changed, 5 insertions, 15 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index d1a72494433..9b9d5f6cc2e 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -353,8 +353,11 @@ def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; -def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, - II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; +let AdditionalPredicates = [NotInMicroMips] in { +def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>, + ABSS_FM<0x4, 16>, ISA_MIPS2; +} + defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; // The odd-numbered registers are only referenced when doing loads, diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll b/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll deleted file mode 100644 index 1a8892de0ee..00000000000 --- a/llvm/test/CodeGen/Mips/llvm-ir/sqrt.ll +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s -; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s -; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s - -define float @sqrt_fn(float %value) #0 { -entry: - %sqrtf = tail call float @sqrtf(float %value) #0 - ret float %sqrtf -} - -declare float @sqrtf(float) - -; CHECK: sqrt.s $f0, $f12 |
