diff options
| -rw-r--r-- | llvm/test/CodeGen/ARM/signext-inreg.ll | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/signext-inreg.ll b/llvm/test/CodeGen/ARM/signext-inreg.ll new file mode 100644 index 00000000000..06836286bfd --- /dev/null +++ b/llvm/test/CodeGen/ARM/signext-inreg.ll @@ -0,0 +1,17 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=armv8 -mattr=+mve | FileCheck %s +define <4 x i32> @test(<4 x i32> %m) { +; CHECK-LABEL: test: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmov d1, r2, r3 +; CHECK-NEXT: vmov d0, r0, r1 +; CHECK-NEXT: vshl.i32 q0, q0, #24 +; CHECK-NEXT: vshr.s32 q0, q0, #24 +; CHECK-NEXT: vmov r0, r1, d0 +; CHECK-NEXT: vmov r2, r3, d1 +; CHECK-NEXT: bx lr +entry: + %shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24> + %shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24> + ret <4 x i32> %shr +} |
