diff options
| -rw-r--r-- | llvm/test/Transforms/InstSimplify/icmp-constant.ll | 238 |
1 files changed, 238 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstSimplify/icmp-constant.ll b/llvm/test/Transforms/InstSimplify/icmp-constant.ll index 74e0456dd7a..084cc9ec550 100644 --- a/llvm/test/Transforms/InstSimplify/icmp-constant.ll +++ b/llvm/test/Transforms/InstSimplify/icmp-constant.ll @@ -11,6 +11,15 @@ define i1 @tautological_ule(i8 %x) { ret i1 %cmp } +define <2 x i1> @tautological_ule_vec(<2 x i8> %x) { +; CHECK-LABEL: @tautological_ule_vec( +; CHECK-NEXT: [[CMP:%.*]] = icmp ule <2 x i8> %x, <i8 -1, i8 -1> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %cmp = icmp ule <2 x i8> %x, <i8 255, i8 255> + ret <2 x i1> %cmp +} + define i1 @tautological_ugt(i8 %x) { ; CHECK-LABEL: @tautological_ugt( ; CHECK-NEXT: ret i1 false @@ -19,6 +28,15 @@ define i1 @tautological_ugt(i8 %x) { ret i1 %cmp } +define <2 x i1> @tautological_ugt_vec(<2 x i8> %x) { +; CHECK-LABEL: @tautological_ugt_vec( +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i8> %x, <i8 -1, i8 -1> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %cmp = icmp ugt <2 x i8> %x, <i8 255, i8 255> + ret <2 x i1> %cmp +} + ; 'urem x, C2' produces [0, C2) define i1 @urem3(i32 %X) { ; CHECK-LABEL: @urem3( @@ -29,6 +47,17 @@ define i1 @urem3(i32 %X) { ret i1 %B } +define <2 x i1> @urem3_vec(<2 x i32> %X) { +; CHECK-LABEL: @urem3_vec( +; CHECK-NEXT: [[A:%.*]] = urem <2 x i32> %X, <i32 10, i32 10> +; CHECK-NEXT: [[B:%.*]] = icmp ult <2 x i32> [[A]], <i32 15, i32 15> +; CHECK-NEXT: ret <2 x i1> [[B]] +; + %A = urem <2 x i32> %X, <i32 10, i32 10> + %B = icmp ult <2 x i32> %A, <i32 15, i32 15> + ret <2 x i1> %B +} + ;'srem x, C2' produces (-|C2|, |C2|) define i1 @srem1(i32 %X) { ; CHECK-LABEL: @srem1( @@ -39,6 +68,17 @@ define i1 @srem1(i32 %X) { ret i1 %B } +define <2 x i1> @srem1_vec(<2 x i32> %X) { +; CHECK-LABEL: @srem1_vec( +; CHECK-NEXT: [[A:%.*]] = srem <2 x i32> %X, <i32 -5, i32 -5> +; CHECK-NEXT: [[B:%.*]] = icmp sgt <2 x i32> [[A]], <i32 5, i32 5> +; CHECK-NEXT: ret <2 x i1> [[B]] +; + %A = srem <2 x i32> %X, <i32 -5, i32 -5> + %B = icmp sgt <2 x i32> %A, <i32 5, i32 5> + ret <2 x i1> %B +} + ;'udiv C2, x' produces [0, C2] define i1 @udiv5(i32 %X) { ; CHECK-LABEL: @udiv5( @@ -49,6 +89,17 @@ define i1 @udiv5(i32 %X) { ret i1 %C } +define <2 x i1> @udiv5_vec(<2 x i32> %X) { +; CHECK-LABEL: @udiv5_vec( +; CHECK-NEXT: [[A:%.*]] = udiv <2 x i32> <i32 123, i32 123>, %X +; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> [[A]], <i32 124, i32 124> +; CHECK-NEXT: ret <2 x i1> [[C]] +; + %A = udiv <2 x i32> <i32 123, i32 123>, %X + %C = icmp ugt <2 x i32> %A, <i32 124, i32 124> + ret <2 x i1> %C +} + ; 'udiv x, C2' produces [0, UINT_MAX / C2] define i1 @udiv1(i32 %X) { ; CHECK-LABEL: @udiv1( @@ -59,6 +110,17 @@ define i1 @udiv1(i32 %X) { ret i1 %B } +define <2 x i1> @udiv1_vec(<2 x i32> %X) { +; CHECK-LABEL: @udiv1_vec( +; CHECK-NEXT: [[A:%.*]] = udiv <2 x i32> %X, <i32 1000000, i32 1000000> +; CHECK-NEXT: [[B:%.*]] = icmp ult <2 x i32> [[A]], <i32 5000, i32 5000> +; CHECK-NEXT: ret <2 x i1> [[B]] +; + %A = udiv <2 x i32> %X, <i32 1000000, i32 1000000> + %B = icmp ult <2 x i32> %A, <i32 5000, i32 5000> + ret <2 x i1> %B +} + ; 'sdiv C2, x' produces [-|C2|, |C2|] define i1 @compare_dividend(i32 %a) { ; CHECK-LABEL: @compare_dividend( @@ -69,6 +131,17 @@ define i1 @compare_dividend(i32 %a) { ret i1 %cmp } +define <2 x i1> @compare_dividend_vec(<2 x i32> %a) { +; CHECK-LABEL: @compare_dividend_vec( +; CHECK-NEXT: [[DIV:%.*]] = sdiv <2 x i32> <i32 2, i32 2>, %a +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[DIV]], <i32 3, i32 3> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %div = sdiv <2 x i32> <i32 2, i32 2>, %a + %cmp = icmp eq <2 x i32> %div, <i32 3, i32 3> + ret <2 x i1> %cmp +} + ; 'sdiv x, C2' produces [INT_MIN / C2, INT_MAX / C2] ; where C2 != -1 and C2 != 0 and C2 != 1 define i1 @sdiv1(i32 %X) { @@ -80,6 +153,17 @@ define i1 @sdiv1(i32 %X) { ret i1 %B } +define <2 x i1> @sdiv1_vec(<2 x i32> %X) { +; CHECK-LABEL: @sdiv1_vec( +; CHECK-NEXT: [[A:%.*]] = sdiv <2 x i32> %X, <i32 1000000, i32 1000000> +; CHECK-NEXT: [[B:%.*]] = icmp slt <2 x i32> [[A]], <i32 3000, i32 3000> +; CHECK-NEXT: ret <2 x i1> [[B]] +; + %A = sdiv <2 x i32> %X, <i32 1000000, i32 1000000> + %B = icmp slt <2 x i32> %A, <i32 3000, i32 3000> + ret <2 x i1> %B +} + ; 'shl nuw C2, x' produces [C2, C2 << CLZ(C2)] define i1 @shl5(i32 %X) { ; CHECK-LABEL: @shl5( @@ -90,6 +174,17 @@ define i1 @shl5(i32 %X) { ret i1 %cmp } +define <2 x i1> @shl5_vec(<2 x i32> %X) { +; CHECK-LABEL: @shl5_vec( +; CHECK-NEXT: [[SUB:%.*]] = shl nuw <2 x i32> <i32 4, i32 4>, %X +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[SUB]], <i32 3, i32 3> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %sub = shl nuw <2 x i32> <i32 4, i32 4>, %X + %cmp = icmp ugt <2 x i32> %sub, <i32 3, i32 3> + ret <2 x i1> %cmp +} + ; 'shl nsw C2, x' produces [C2 << CLO(C2)-1, C2] define i1 @shl2(i32 %X) { ; CHECK-LABEL: @shl2( @@ -100,6 +195,17 @@ define i1 @shl2(i32 %X) { ret i1 %cmp } +define <2 x i1> @shl2_vec(<2 x i32> %X) { +; CHECK-LABEL: @shl2_vec( +; CHECK-NEXT: [[SUB:%.*]] = shl nsw <2 x i32> <i32 -1, i32 -1>, %X +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[SUB]], <i32 31, i32 31> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %sub = shl nsw <2 x i32> <i32 -1, i32 -1>, %X + %cmp = icmp eq <2 x i32> %sub, <i32 31, i32 31> + ret <2 x i1> %cmp +} + ; 'shl nsw C2, x' produces [C2 << CLO(C2)-1, C2] define i1 @shl4(i32 %X) { ; CHECK-LABEL: @shl4( @@ -110,6 +216,17 @@ define i1 @shl4(i32 %X) { ret i1 %cmp } +define <2 x i1> @shl4_vec(<2 x i32> %X) { +; CHECK-LABEL: @shl4_vec( +; CHECK-NEXT: [[SUB:%.*]] = shl nsw <2 x i32> <i32 -1, i32 -1>, %X +; CHECK-NEXT: [[CMP:%.*]] = icmp sle <2 x i32> [[SUB]], <i32 -1, i32 -1> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %sub = shl nsw <2 x i32> <i32 -1, i32 -1>, %X + %cmp = icmp sle <2 x i32> %sub, <i32 -1, i32 -1> + ret <2 x i1> %cmp +} + ; 'shl nsw C2, x' produces [C2, C2 << CLZ(C2)-1] define i1 @icmp_shl_nsw_1(i64 %a) { ; CHECK-LABEL: @icmp_shl_nsw_1( @@ -120,6 +237,17 @@ define i1 @icmp_shl_nsw_1(i64 %a) { ret i1 %cmp } +define <2 x i1> @icmp_shl_nsw_1_vec(<2 x i64> %a) { +; CHECK-LABEL: @icmp_shl_nsw_1_vec( +; CHECK-NEXT: [[SHL:%.*]] = shl nsw <2 x i64> <i64 1, i64 1>, %a +; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i64> [[SHL]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %shl = shl nsw <2 x i64> <i64 1, i64 1>, %a + %cmp = icmp sge <2 x i64> %shl, zeroinitializer + ret <2 x i1> %cmp +} + ; 'shl nsw C2, x' produces [C2 << CLO(C2)-1, C2] define i1 @icmp_shl_nsw_neg1(i64 %a) { ; CHECK-LABEL: @icmp_shl_nsw_neg1( @@ -130,6 +258,17 @@ define i1 @icmp_shl_nsw_neg1(i64 %a) { ret i1 %cmp } +define <2 x i1> @icmp_shl_nsw_neg1_vec(<2 x i64> %a) { +; CHECK-LABEL: @icmp_shl_nsw_neg1_vec( +; CHECK-NEXT: [[SHL:%.*]] = shl nsw <2 x i64> <i64 -1, i64 -1>, %a +; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i64> [[SHL]], <i64 3, i64 3> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %shl = shl nsw <2 x i64> <i64 -1, i64 -1>, %a + %cmp = icmp sge <2 x i64> %shl, <i64 3, i64 3> + ret <2 x i1> %cmp +} + ; 'lshr x, C2' produces [0, UINT_MAX >> C2] define i1 @lshr2(i32 %x) { ; CHECK-LABEL: @lshr2( @@ -140,6 +279,17 @@ define i1 @lshr2(i32 %x) { ret i1 %c } +define <2 x i1> @lshr2_vec(<2 x i32> %x) { +; CHECK-LABEL: @lshr2_vec( +; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> %x, <i32 30, i32 30> +; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> [[S]], <i32 8, i32 8> +; CHECK-NEXT: ret <2 x i1> [[C]] +; + %s = lshr <2 x i32> %x, <i32 30, i32 30> + %c = icmp ugt <2 x i32> %s, <i32 8, i32 8> + ret <2 x i1> %c +} + ; 'lshr C2, x' produces [C2 >> (Width-1), C2] define i1 @exact_lshr_ugt_false(i32 %a) { ; CHECK-LABEL: @exact_lshr_ugt_false( @@ -150,6 +300,17 @@ define i1 @exact_lshr_ugt_false(i32 %a) { ret i1 %cmp } +define <2 x i1> @exact_lshr_ugt_false_vec(<2 x i32> %a) { +; CHECK-LABEL: @exact_lshr_ugt_false_vec( +; CHECK-NEXT: [[SHR:%.*]] = lshr exact <2 x i32> <i32 30, i32 30>, %a +; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[SHR]], <i32 15, i32 15> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %shr = lshr exact <2 x i32> <i32 30, i32 30>, %a + %cmp = icmp ult <2 x i32> %shr, <i32 15, i32 15> + ret <2 x i1> %cmp +} + ; 'lshr C2, x' produces [C2 >> (Width-1), C2] define i1 @lshr_sgt_false(i32 %a) { ; CHECK-LABEL: @lshr_sgt_false( @@ -160,6 +321,17 @@ define i1 @lshr_sgt_false(i32 %a) { ret i1 %cmp } +define <2 x i1> @lshr_sgt_false_vec(<2 x i32> %a) { +; CHECK-LABEL: @lshr_sgt_false_vec( +; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i32> <i32 1, i32 1>, %a +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[SHR]], <i32 1, i32 1> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %shr = lshr <2 x i32> <i32 1, i32 1>, %a + %cmp = icmp sgt <2 x i32> %shr, <i32 1, i32 1> + ret <2 x i1> %cmp +} + ; 'ashr x, C2' produces [INT_MIN >> C2, INT_MAX >> C2] define i1 @ashr2(i32 %x) { ; CHECK-LABEL: @ashr2( @@ -170,6 +342,17 @@ define i1 @ashr2(i32 %x) { ret i1 %c } +define <2 x i1> @ashr2_vec(<2 x i32> %x) { +; CHECK-LABEL: @ashr2_vec( +; CHECK-NEXT: [[S:%.*]] = ashr <2 x i32> %x, <i32 30, i32 30> +; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i32> [[S]], <i32 -5, i32 -5> +; CHECK-NEXT: ret <2 x i1> [[C]] +; + %s = ashr <2 x i32> %x, <i32 30, i32 30> + %c = icmp slt <2 x i32> %s, <i32 -5, i32 -5> + ret <2 x i1> %c +} + ; 'ashr C2, x' produces [C2, C2 >> (Width-1)] define i1 @ashr_sgt_false(i32 %a) { ; CHECK-LABEL: @ashr_sgt_false( @@ -180,6 +363,17 @@ define i1 @ashr_sgt_false(i32 %a) { ret i1 %cmp } +define <2 x i1> @ashr_sgt_false_vec(<2 x i32> %a) { +; CHECK-LABEL: @ashr_sgt_false_vec( +; CHECK-NEXT: [[SHR:%.*]] = ashr <2 x i32> <i32 -30, i32 -30>, %a +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[SHR]], <i32 -1, i32 -1> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %shr = ashr <2 x i32> <i32 -30, i32 -30>, %a + %cmp = icmp sgt <2 x i32> %shr, <i32 -1, i32 -1> + ret <2 x i1> %cmp +} + ; 'ashr C2, x' produces [C2, C2 >> (Width-1)] define i1 @exact_ashr_sgt_false(i32 %a) { ; CHECK-LABEL: @exact_ashr_sgt_false( @@ -190,6 +384,17 @@ define i1 @exact_ashr_sgt_false(i32 %a) { ret i1 %cmp } +define <2 x i1> @exact_ashr_sgt_false_vec(<2 x i32> %a) { +; CHECK-LABEL: @exact_ashr_sgt_false_vec( +; CHECK-NEXT: [[SHR:%.*]] = ashr exact <2 x i32> <i32 -30, i32 -30>, %a +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[SHR]], <i32 -15, i32 -15> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %shr = ashr exact <2 x i32> <i32 -30, i32 -30>, %a + %cmp = icmp sgt <2 x i32> %shr, <i32 -15, i32 -15> + ret <2 x i1> %cmp +} + ; 'or x, C2' produces [C2, UINT_MAX] define i1 @or1(i32 %X) { ; CHECK-LABEL: @or1( @@ -200,6 +405,17 @@ define i1 @or1(i32 %X) { ret i1 %B } +define <2 x i1> @or1_vec(<2 x i32> %X) { +; CHECK-LABEL: @or1_vec( +; CHECK-NEXT: [[A:%.*]] = or <2 x i32> %X, <i32 62, i32 62> +; CHECK-NEXT: [[B:%.*]] = icmp ult <2 x i32> [[A]], <i32 50, i32 50> +; CHECK-NEXT: ret <2 x i1> [[B]] +; + %A = or <2 x i32> %X, <i32 62, i32 62> + %B = icmp ult <2 x i32> %A, <i32 50, i32 50> + ret <2 x i1> %B +} + ; 'and x, C2' produces [0, C2] define i1 @and1(i32 %X) { ; CHECK-LABEL: @and1( @@ -210,6 +426,17 @@ define i1 @and1(i32 %X) { ret i1 %B } +define <2 x i1> @and1_vec(<2 x i32> %X) { +; CHECK-LABEL: @and1_vec( +; CHECK-NEXT: [[A:%.*]] = and <2 x i32> %X, <i32 62, i32 62> +; CHECK-NEXT: [[B:%.*]] = icmp ugt <2 x i32> [[A]], <i32 70, i32 70> +; CHECK-NEXT: ret <2 x i1> [[B]] +; + %A = and <2 x i32> %X, <i32 62, i32 62> + %B = icmp ugt <2 x i32> %A, <i32 70, i32 70> + ret <2 x i1> %B +} + ; 'add nuw x, C2' produces [C2, UINT_MAX] define i1 @tautological9(i32 %x) { ; CHECK-LABEL: @tautological9( @@ -220,3 +447,14 @@ define i1 @tautological9(i32 %x) { ret i1 %cmp } +define <2 x i1> @tautological9_vec(<2 x i32> %x) { +; CHECK-LABEL: @tautological9_vec( +; CHECK-NEXT: [[ADD:%.*]] = add nuw <2 x i32> %x, <i32 13, i32 13> +; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[ADD]], <i32 12, i32 12> +; CHECK-NEXT: ret <2 x i1> [[CMP]] +; + %add = add nuw <2 x i32> %x, <i32 13, i32 13> + %cmp = icmp ne <2 x i32> %add, <i32 12, i32 12> + ret <2 x i1> %cmp +} + |
