diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 20 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 31 |
2 files changed, 47 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index f5a742b1e22..e57478b00ee 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -130,6 +130,26 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const { I.eraseFromParent(); return true; } + + const TargetRegisterClass *RC = + TRI.getConstrainedRegClassForOperand(Dst, MRI); + if (RC && !RBI.constrainGenericRegister(DstReg, *RC, MRI)) + return false; + + // Don't constrain the source register to a class so the def instruction + // handles it (unless it's undef). + // + // FIXME: This is a hack. When selecting the def, we neeed to know + // specifically know that the result is VCCRegBank, and not just an SGPR + // with size 1. An SReg_32 with size 1 is ambiguous with wave32. + if (Src.isUndef()) { + const TargetRegisterClass *SrcRC = + TRI.getConstrainedRegClassForOperand(Src, MRI); + if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI)) + return false; + } + + return true; } for (const MachineOperand &MO : I.operands()) { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir index 81ffcd5464c..2f2ad31cd0a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir @@ -282,13 +282,15 @@ body: | ; WAVE64-LABEL: name: copy_s1_vcc_to_vcc ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0 - ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec - ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]] + ; WAVE64: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec + ; WAVE64: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[V_CMP_NE_U32_e64_]] + ; WAVE64: S_ENDPGM 0, implicit [[COPY1]] ; WAVE32-LABEL: name: copy_s1_vcc_to_vcc ; WAVE32: $vcc_hi = IMPLICIT_DEF ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0 - ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec - ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NE_U32_e64_]] + ; WAVE32: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NE_U32_e64 0, [[COPY]], implicit $exec + ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[V_CMP_NE_U32_e64_]] + ; WAVE32: S_ENDPGM 0, implicit [[COPY1]] %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s1) = G_TRUNC %0 %2:vcc(s1) = COPY %1 @@ -296,3 +298,24 @@ body: | S_ENDPGM 0, implicit %3 ... + +--- + +name: copy_s1_vcc_to_vcc_undef +legalized: true +regBankSelected: true + + +body: | + bb.0: + liveins: $sgpr0_sgpr1 + + ; WAVE64-LABEL: name: copy_s1_vcc_to_vcc_undef + ; WAVE64: S_ENDPGM 0, implicit %1:sreg_64_xexec + ; WAVE32-LABEL: name: copy_s1_vcc_to_vcc_undef + ; WAVE32: $vcc_hi = IMPLICIT_DEF + ; WAVE32: S_ENDPGM 0, implicit %1:sreg_32_xm0_xexec + %1:vcc(s1) = COPY undef %0:vcc(s1) + S_ENDPGM 0, implicit %1 + +... |
