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-rw-r--r--llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp64
-rw-r--r--llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp66
-rw-r--r--llvm/lib/Target/RISCV/RISCVCallingConv.td28
-rw-r--r--llvm/lib/Target/RISCV/RISCVISelLowering.cpp74
-rw-r--r--llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp9
-rw-r--r--llvm/lib/Target/RISCV/RISCVRegisterInfo.td94
6 files changed, 136 insertions, 199 deletions
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 5f93db484b3..300ba8dc675 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -741,46 +741,9 @@ public:
#define GET_MATCHER_IMPLEMENTATION
#include "RISCVGenAsmMatcher.inc"
-// Return the matching FPR64 register for the given FPR32.
-// FIXME: Ideally this function could be removed in favour of using
-// information from TableGen.
-static Register convertFPR32ToFPR64(Register Reg) {
- switch (Reg) {
- default:
- llvm_unreachable("Not a recognised FPR32 register");
- case RISCV::F0_32: return RISCV::F0_64;
- case RISCV::F1_32: return RISCV::F1_64;
- case RISCV::F2_32: return RISCV::F2_64;
- case RISCV::F3_32: return RISCV::F3_64;
- case RISCV::F4_32: return RISCV::F4_64;
- case RISCV::F5_32: return RISCV::F5_64;
- case RISCV::F6_32: return RISCV::F6_64;
- case RISCV::F7_32: return RISCV::F7_64;
- case RISCV::F8_32: return RISCV::F8_64;
- case RISCV::F9_32: return RISCV::F9_64;
- case RISCV::F10_32: return RISCV::F10_64;
- case RISCV::F11_32: return RISCV::F11_64;
- case RISCV::F12_32: return RISCV::F12_64;
- case RISCV::F13_32: return RISCV::F13_64;
- case RISCV::F14_32: return RISCV::F14_64;
- case RISCV::F15_32: return RISCV::F15_64;
- case RISCV::F16_32: return RISCV::F16_64;
- case RISCV::F17_32: return RISCV::F17_64;
- case RISCV::F18_32: return RISCV::F18_64;
- case RISCV::F19_32: return RISCV::F19_64;
- case RISCV::F20_32: return RISCV::F20_64;
- case RISCV::F21_32: return RISCV::F21_64;
- case RISCV::F22_32: return RISCV::F22_64;
- case RISCV::F23_32: return RISCV::F23_64;
- case RISCV::F24_32: return RISCV::F24_64;
- case RISCV::F25_32: return RISCV::F25_64;
- case RISCV::F26_32: return RISCV::F26_64;
- case RISCV::F27_32: return RISCV::F27_64;
- case RISCV::F28_32: return RISCV::F28_64;
- case RISCV::F29_32: return RISCV::F29_64;
- case RISCV::F30_32: return RISCV::F30_64;
- case RISCV::F31_32: return RISCV::F31_64;
- }
+static Register convertFPR64ToFPR32(Register Reg) {
+ assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register");
+ return Reg - RISCV::F0_D + RISCV::F0_F;
}
unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
@@ -790,16 +753,16 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
return Match_InvalidOperand;
Register Reg = Op.getReg();
- bool IsRegFPR32 =
- RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(Reg);
- bool IsRegFPR32C =
- RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(Reg);
+ bool IsRegFPR64 =
+ RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(Reg);
+ bool IsRegFPR64C =
+ RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg);
// As the parser couldn't differentiate an FPR32 from an FPR64, coerce the
- // register from FPR32 to FPR64 or FPR32C to FPR64C if necessary.
- if ((IsRegFPR32 && Kind == MCK_FPR64) ||
- (IsRegFPR32C && Kind == MCK_FPR64C)) {
- Op.Reg.RegNum = convertFPR32ToFPR64(Reg);
+ // register from FPR64 to FPR32 or FPR64C to FPR32C if necessary.
+ if ((IsRegFPR64 && Kind == MCK_FPR32) ||
+ (IsRegFPR64C && Kind == MCK_FPR32C)) {
+ Op.Reg.RegNum = convertFPR64ToFPR32(Reg);
return Match_Success;
}
return Match_InvalidOperand;
@@ -986,6 +949,11 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
static bool matchRegisterNameHelper(bool IsRV32E, Register &RegNo,
StringRef Name) {
RegNo = MatchRegisterName(Name);
+ // The 32- and 64-bit FPRs have the same asm name. Check that the initial
+ // match always matches the 64-bit variant, and not the 32-bit one.
+ assert(!(RegNo >= RISCV::F0_F && RegNo <= RISCV::F31_F));
+ // The default FPR register class is based on the tablegen enum ordering.
+ static_assert(RISCV::F0_D < RISCV::F0_F, "FPR matching must be updated");
if (RegNo == RISCV::NoRegister)
RegNo = MatchRegisterAltName(Name);
if (IsRV32E && RegNo >= RISCV::X16 && RegNo <= RISCV::X31)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 4b85955a97b..15943ba4215 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -57,17 +57,6 @@ extern "C" void LLVMInitializeRISCVDisassembler() {
createRISCVDisassembler);
}
-static const Register GPRDecoderTable[] = {
- RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3,
- RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7,
- RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11,
- RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15,
- RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19,
- RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23,
- RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27,
- RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31
-};
-
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
@@ -77,38 +66,21 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
.getFeatureBits();
bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
- if (RegNo > array_lengthof(GPRDecoderTable) || (IsRV32E && RegNo > 15))
+ if (RegNo >= 32 || (IsRV32E && RegNo >= 16))
return MCDisassembler::Fail;
- // We must define our own mapping from RegNo to register identifier.
- // Accessing index RegNo in the register class will work in the case that
- // registers were added in ascending order, but not in general.
- Register Reg = GPRDecoderTable[RegNo];
+ Register Reg = RISCV::X0 + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
-static const Register FPR32DecoderTable[] = {
- RISCV::F0_32, RISCV::F1_32, RISCV::F2_32, RISCV::F3_32,
- RISCV::F4_32, RISCV::F5_32, RISCV::F6_32, RISCV::F7_32,
- RISCV::F8_32, RISCV::F9_32, RISCV::F10_32, RISCV::F11_32,
- RISCV::F12_32, RISCV::F13_32, RISCV::F14_32, RISCV::F15_32,
- RISCV::F16_32, RISCV::F17_32, RISCV::F18_32, RISCV::F19_32,
- RISCV::F20_32, RISCV::F21_32, RISCV::F22_32, RISCV::F23_32,
- RISCV::F24_32, RISCV::F25_32, RISCV::F26_32, RISCV::F27_32,
- RISCV::F28_32, RISCV::F29_32, RISCV::F30_32, RISCV::F31_32
-};
-
static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo > array_lengthof(FPR32DecoderTable))
+ if (RegNo >= 32)
return MCDisassembler::Fail;
- // We must define our own mapping from RegNo to register identifier.
- // Accessing index RegNo in the register class will work in the case that
- // registers were added in ascending order, but not in general.
- Register Reg = FPR32DecoderTable[RegNo];
+ Register Reg = RISCV::F0_F + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -116,35 +88,21 @@ static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo,
static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo > 8) {
+ if (RegNo >= 8) {
return MCDisassembler::Fail;
}
- Register Reg = FPR32DecoderTable[RegNo + 8];
+ Register Reg = RISCV::F8_F + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
-static const Register FPR64DecoderTable[] = {
- RISCV::F0_64, RISCV::F1_64, RISCV::F2_64, RISCV::F3_64,
- RISCV::F4_64, RISCV::F5_64, RISCV::F6_64, RISCV::F7_64,
- RISCV::F8_64, RISCV::F9_64, RISCV::F10_64, RISCV::F11_64,
- RISCV::F12_64, RISCV::F13_64, RISCV::F14_64, RISCV::F15_64,
- RISCV::F16_64, RISCV::F17_64, RISCV::F18_64, RISCV::F19_64,
- RISCV::F20_64, RISCV::F21_64, RISCV::F22_64, RISCV::F23_64,
- RISCV::F24_64, RISCV::F25_64, RISCV::F26_64, RISCV::F27_64,
- RISCV::F28_64, RISCV::F29_64, RISCV::F30_64, RISCV::F31_64
-};
-
static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo > array_lengthof(FPR64DecoderTable))
+ if (RegNo >= 32)
return MCDisassembler::Fail;
- // We must define our own mapping from RegNo to register identifier.
- // Accessing index RegNo in the register class will work in the case that
- // registers were added in ascending order, but not in general.
- Register Reg = FPR64DecoderTable[RegNo];
+ Register Reg = RISCV::F0_D + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -152,10 +110,10 @@ static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo,
static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo > 8) {
+ if (RegNo >= 8) {
return MCDisassembler::Fail;
}
- Register Reg = FPR64DecoderTable[RegNo + 8];
+ Register Reg = RISCV::F8_D + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -183,10 +141,10 @@ static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo,
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo > 8)
+ if (RegNo >= 8)
return MCDisassembler::Fail;
- Register Reg = GPRDecoderTable[RegNo + 8];
+ Register Reg = RISCV::X8 + RegNo;
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.td b/llvm/lib/Target/RISCV/RISCVCallingConv.td
index db13e6e8bec..025454f8fcc 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.td
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.td
@@ -18,11 +18,11 @@ def CSR_ILP32_LP64
def CSR_ILP32F_LP64F
: CalleeSavedRegs<(add CSR_ILP32_LP64,
- F8_32, F9_32, (sequence "F%u_32", 18, 27))>;
+ F8_F, F9_F, (sequence "F%u_F", 18, 27))>;
def CSR_ILP32D_LP64D
: CalleeSavedRegs<(add CSR_ILP32_LP64,
- F8_64, F9_64, (sequence "F%u_64", 18, 27))>;
+ F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
def CSR_NoRegs : CalleeSavedRegs<(add)>;
@@ -43,12 +43,12 @@ def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add X1,
(sequence "X%u", 12, 17),
(sequence "X%u", 18, 27),
(sequence "X%u", 28, 31),
- (sequence "F%u_32", 0, 7),
- (sequence "F%u_32", 10, 11),
- (sequence "F%u_32", 12, 17),
- (sequence "F%u_32", 28, 31),
- (sequence "F%u_32", 8, 9),
- (sequence "F%u_32", 18, 27))>;
+ (sequence "F%u_F", 0, 7),
+ (sequence "F%u_F", 10, 11),
+ (sequence "F%u_F", 12, 17),
+ (sequence "F%u_F", 28, 31),
+ (sequence "F%u_F", 8, 9),
+ (sequence "F%u_F", 18, 27))>;
// Same as CSR_Interrupt, but including all 64-bit FP registers.
def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add X1,
@@ -57,9 +57,9 @@ def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add X1,
(sequence "X%u", 12, 17),
(sequence "X%u", 18, 27),
(sequence "X%u", 28, 31),
- (sequence "F%u_64", 0, 7),
- (sequence "F%u_64", 10, 11),
- (sequence "F%u_64", 12, 17),
- (sequence "F%u_64", 28, 31),
- (sequence "F%u_64", 8, 9),
- (sequence "F%u_64", 18, 27))>;
+ (sequence "F%u_D", 0, 7),
+ (sequence "F%u_D", 10, 11),
+ (sequence "F%u_D", 12, 17),
+ (sequence "F%u_D", 28, 31),
+ (sequence "F%u_D", 8, 9),
+ (sequence "F%u_D", 18, 27))>;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f459497164f..5c20057c999 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1389,12 +1389,12 @@ static const MCPhysReg ArgGPRs[] = {
RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
};
static const MCPhysReg ArgFPR32s[] = {
- RISCV::F10_32, RISCV::F11_32, RISCV::F12_32, RISCV::F13_32,
- RISCV::F14_32, RISCV::F15_32, RISCV::F16_32, RISCV::F17_32
+ RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F,
+ RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F
};
static const MCPhysReg ArgFPR64s[] = {
- RISCV::F10_64, RISCV::F11_64, RISCV::F12_64, RISCV::F13_64,
- RISCV::F14_64, RISCV::F15_64, RISCV::F16_64, RISCV::F17_64
+ RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D,
+ RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D
};
// Pass a 2*XLEN argument that has been split into two XLEN values through
@@ -2107,6 +2107,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo()));
} else {
// Second half of f64 is passed in another GPR.
+ assert(RegLo < RISCV::X31 && "Invalid register pair");
Register RegHigh = RegLo + 1;
RegsToPass.push_back(std::make_pair(RegHigh, Hi));
}
@@ -2323,6 +2324,7 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
SDValue Lo = SplitF64.getValue(0);
SDValue Hi = SplitF64.getValue(1);
Register RegLo = VA.getLocReg();
+ assert(RegLo < RISCV::X31 && "Invalid register pair");
Register RegHi = RegLo + 1;
Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);
Glue = Chain.getValue(1);
@@ -2510,38 +2512,38 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (Subtarget.hasStdExtF() || Subtarget.hasStdExtD()) {
std::pair<Register, Register> FReg =
StringSwitch<std::pair<Register, Register>>(Constraint.lower())
- .Cases("{f0}", "{ft0}", {RISCV::F0_32, RISCV::F0_64})
- .Cases("{f1}", "{ft1}", {RISCV::F1_32, RISCV::F1_64})
- .Cases("{f2}", "{ft2}", {RISCV::F2_32, RISCV::F2_64})
- .Cases("{f3}", "{ft3}", {RISCV::F3_32, RISCV::F3_64})
- .Cases("{f4}", "{ft4}", {RISCV::F4_32, RISCV::F4_64})
- .Cases("{f5}", "{ft5}", {RISCV::F5_32, RISCV::F5_64})
- .Cases("{f6}", "{ft6}", {RISCV::F6_32, RISCV::F6_64})
- .Cases("{f7}", "{ft7}", {RISCV::F7_32, RISCV::F7_64})
- .Cases("{f8}", "{fs0}", {RISCV::F8_32, RISCV::F8_64})
- .Cases("{f9}", "{fs1}", {RISCV::F9_32, RISCV::F9_64})
- .Cases("{f10}", "{fa0}", {RISCV::F10_32, RISCV::F10_64})
- .Cases("{f11}", "{fa1}", {RISCV::F11_32, RISCV::F11_64})
- .Cases("{f12}", "{fa2}", {RISCV::F12_32, RISCV::F12_64})
- .Cases("{f13}", "{fa3}", {RISCV::F13_32, RISCV::F13_64})
- .Cases("{f14}", "{fa4}", {RISCV::F14_32, RISCV::F14_64})
- .Cases("{f15}", "{fa5}", {RISCV::F15_32, RISCV::F15_64})
- .Cases("{f16}", "{fa6}", {RISCV::F16_32, RISCV::F16_64})
- .Cases("{f17}", "{fa7}", {RISCV::F17_32, RISCV::F17_64})
- .Cases("{f18}", "{fs2}", {RISCV::F18_32, RISCV::F18_64})
- .Cases("{f19}", "{fs3}", {RISCV::F19_32, RISCV::F19_64})
- .Cases("{f20}", "{fs4}", {RISCV::F20_32, RISCV::F20_64})
- .Cases("{f21}", "{fs5}", {RISCV::F21_32, RISCV::F21_64})
- .Cases("{f22}", "{fs6}", {RISCV::F22_32, RISCV::F22_64})
- .Cases("{f23}", "{fs7}", {RISCV::F23_32, RISCV::F23_64})
- .Cases("{f24}", "{fs8}", {RISCV::F24_32, RISCV::F24_64})
- .Cases("{f25}", "{fs9}", {RISCV::F25_32, RISCV::F25_64})
- .Cases("{f26}", "{fs10}", {RISCV::F26_32, RISCV::F26_64})
- .Cases("{f27}", "{fs11}", {RISCV::F27_32, RISCV::F27_64})
- .Cases("{f28}", "{ft8}", {RISCV::F28_32, RISCV::F28_64})
- .Cases("{f29}", "{ft9}", {RISCV::F29_32, RISCV::F29_64})
- .Cases("{f30}", "{ft10}", {RISCV::F30_32, RISCV::F30_64})
- .Cases("{f31}", "{ft11}", {RISCV::F31_32, RISCV::F31_64})
+ .Cases("{f0}", "{ft0}", {RISCV::F0_F, RISCV::F0_D})
+ .Cases("{f1}", "{ft1}", {RISCV::F1_F, RISCV::F1_D})
+ .Cases("{f2}", "{ft2}", {RISCV::F2_F, RISCV::F2_D})
+ .Cases("{f3}", "{ft3}", {RISCV::F3_F, RISCV::F3_D})
+ .Cases("{f4}", "{ft4}", {RISCV::F4_F, RISCV::F4_D})
+ .Cases("{f5}", "{ft5}", {RISCV::F5_F, RISCV::F5_D})
+ .Cases("{f6}", "{ft6}", {RISCV::F6_F, RISCV::F6_D})
+ .Cases("{f7}", "{ft7}", {RISCV::F7_F, RISCV::F7_D})
+ .Cases("{f8}", "{fs0}", {RISCV::F8_F, RISCV::F8_D})
+ .Cases("{f9}", "{fs1}", {RISCV::F9_F, RISCV::F9_D})
+ .Cases("{f10}", "{fa0}", {RISCV::F10_F, RISCV::F10_D})
+ .Cases("{f11}", "{fa1}", {RISCV::F11_F, RISCV::F11_D})
+ .Cases("{f12}", "{fa2}", {RISCV::F12_F, RISCV::F12_D})
+ .Cases("{f13}", "{fa3}", {RISCV::F13_F, RISCV::F13_D})
+ .Cases("{f14}", "{fa4}", {RISCV::F14_F, RISCV::F14_D})
+ .Cases("{f15}", "{fa5}", {RISCV::F15_F, RISCV::F15_D})
+ .Cases("{f16}", "{fa6}", {RISCV::F16_F, RISCV::F16_D})
+ .Cases("{f17}", "{fa7}", {RISCV::F17_F, RISCV::F17_D})
+ .Cases("{f18}", "{fs2}", {RISCV::F18_F, RISCV::F18_D})
+ .Cases("{f19}", "{fs3}", {RISCV::F19_F, RISCV::F19_D})
+ .Cases("{f20}", "{fs4}", {RISCV::F20_F, RISCV::F20_D})
+ .Cases("{f21}", "{fs5}", {RISCV::F21_F, RISCV::F21_D})
+ .Cases("{f22}", "{fs6}", {RISCV::F22_F, RISCV::F22_D})
+ .Cases("{f23}", "{fs7}", {RISCV::F23_F, RISCV::F23_D})
+ .Cases("{f24}", "{fs8}", {RISCV::F24_F, RISCV::F24_D})
+ .Cases("{f25}", "{fs9}", {RISCV::F25_F, RISCV::F25_D})
+ .Cases("{f26}", "{fs10}", {RISCV::F26_F, RISCV::F26_D})
+ .Cases("{f27}", "{fs11}", {RISCV::F27_F, RISCV::F27_D})
+ .Cases("{f28}", "{ft8}", {RISCV::F28_F, RISCV::F28_D})
+ .Cases("{f29}", "{ft9}", {RISCV::F29_F, RISCV::F29_D})
+ .Cases("{f30}", "{ft10}", {RISCV::F30_F, RISCV::F30_D})
+ .Cases("{f31}", "{ft11}", {RISCV::F31_F, RISCV::F31_D})
.Default({RISCV::NoRegister, RISCV::NoRegister});
if (FReg.first != RISCV::NoRegister)
return Subtarget.hasStdExtD()
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index aa6d06d3d41..66557687c0b 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -26,6 +26,15 @@
using namespace llvm;
+static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
+static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
+static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
+static_assert(RISCV::F31_F == RISCV::F0_F + 31,
+ "Register list not consecutive");
+static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
+static_assert(RISCV::F31_D == RISCV::F0_D + 31,
+ "Register list not consecutive");
+
RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
: RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
/*PC*/0, HwMode) {}
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 9b039212b4d..82b37afd080 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -165,41 +165,41 @@ def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {
// Floating point registers
let RegAltNameIndices = [ABIRegAltName] in {
- def F0_32 : RISCVReg32<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
- def F1_32 : RISCVReg32<1, "f1", ["ft1"]>, DwarfRegNum<[33]>;
- def F2_32 : RISCVReg32<2, "f2", ["ft2"]>, DwarfRegNum<[34]>;
- def F3_32 : RISCVReg32<3, "f3", ["ft3"]>, DwarfRegNum<[35]>;
- def F4_32 : RISCVReg32<4, "f4", ["ft4"]>, DwarfRegNum<[36]>;
- def F5_32 : RISCVReg32<5, "f5", ["ft5"]>, DwarfRegNum<[37]>;
- def F6_32 : RISCVReg32<6, "f6", ["ft6"]>, DwarfRegNum<[38]>;
- def F7_32 : RISCVReg32<7, "f7", ["ft7"]>, DwarfRegNum<[39]>;
- def F8_32 : RISCVReg32<8, "f8", ["fs0"]>, DwarfRegNum<[40]>;
- def F9_32 : RISCVReg32<9, "f9", ["fs1"]>, DwarfRegNum<[41]>;
- def F10_32 : RISCVReg32<10,"f10", ["fa0"]>, DwarfRegNum<[42]>;
- def F11_32 : RISCVReg32<11,"f11", ["fa1"]>, DwarfRegNum<[43]>;
- def F12_32 : RISCVReg32<12,"f12", ["fa2"]>, DwarfRegNum<[44]>;
- def F13_32 : RISCVReg32<13,"f13", ["fa3"]>, DwarfRegNum<[45]>;
- def F14_32 : RISCVReg32<14,"f14", ["fa4"]>, DwarfRegNum<[46]>;
- def F15_32 : RISCVReg32<15,"f15", ["fa5"]>, DwarfRegNum<[47]>;
- def F16_32 : RISCVReg32<16,"f16", ["fa6"]>, DwarfRegNum<[48]>;
- def F17_32 : RISCVReg32<17,"f17", ["fa7"]>, DwarfRegNum<[49]>;
- def F18_32 : RISCVReg32<18,"f18", ["fs2"]>, DwarfRegNum<[50]>;
- def F19_32 : RISCVReg32<19,"f19", ["fs3"]>, DwarfRegNum<[51]>;
- def F20_32 : RISCVReg32<20,"f20", ["fs4"]>, DwarfRegNum<[52]>;
- def F21_32 : RISCVReg32<21,"f21", ["fs5"]>, DwarfRegNum<[53]>;
- def F22_32 : RISCVReg32<22,"f22", ["fs6"]>, DwarfRegNum<[54]>;
- def F23_32 : RISCVReg32<23,"f23", ["fs7"]>, DwarfRegNum<[55]>;
- def F24_32 : RISCVReg32<24,"f24", ["fs8"]>, DwarfRegNum<[56]>;
- def F25_32 : RISCVReg32<25,"f25", ["fs9"]>, DwarfRegNum<[57]>;
- def F26_32 : RISCVReg32<26,"f26", ["fs10"]>, DwarfRegNum<[58]>;
- def F27_32 : RISCVReg32<27,"f27", ["fs11"]>, DwarfRegNum<[59]>;
- def F28_32 : RISCVReg32<28,"f28", ["ft8"]>, DwarfRegNum<[60]>;
- def F29_32 : RISCVReg32<29,"f29", ["ft9"]>, DwarfRegNum<[61]>;
- def F30_32 : RISCVReg32<30,"f30", ["ft10"]>, DwarfRegNum<[62]>;
- def F31_32 : RISCVReg32<31,"f31", ["ft11"]>, DwarfRegNum<[63]>;
+ def F0_F : RISCVReg32<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
+ def F1_F : RISCVReg32<1, "f1", ["ft1"]>, DwarfRegNum<[33]>;
+ def F2_F : RISCVReg32<2, "f2", ["ft2"]>, DwarfRegNum<[34]>;
+ def F3_F : RISCVReg32<3, "f3", ["ft3"]>, DwarfRegNum<[35]>;
+ def F4_F : RISCVReg32<4, "f4", ["ft4"]>, DwarfRegNum<[36]>;
+ def F5_F : RISCVReg32<5, "f5", ["ft5"]>, DwarfRegNum<[37]>;
+ def F6_F : RISCVReg32<6, "f6", ["ft6"]>, DwarfRegNum<[38]>;
+ def F7_F : RISCVReg32<7, "f7", ["ft7"]>, DwarfRegNum<[39]>;
+ def F8_F : RISCVReg32<8, "f8", ["fs0"]>, DwarfRegNum<[40]>;
+ def F9_F : RISCVReg32<9, "f9", ["fs1"]>, DwarfRegNum<[41]>;
+ def F10_F : RISCVReg32<10,"f10", ["fa0"]>, DwarfRegNum<[42]>;
+ def F11_F : RISCVReg32<11,"f11", ["fa1"]>, DwarfRegNum<[43]>;
+ def F12_F : RISCVReg32<12,"f12", ["fa2"]>, DwarfRegNum<[44]>;
+ def F13_F : RISCVReg32<13,"f13", ["fa3"]>, DwarfRegNum<[45]>;
+ def F14_F : RISCVReg32<14,"f14", ["fa4"]>, DwarfRegNum<[46]>;
+ def F15_F : RISCVReg32<15,"f15", ["fa5"]>, DwarfRegNum<[47]>;
+ def F16_F : RISCVReg32<16,"f16", ["fa6"]>, DwarfRegNum<[48]>;
+ def F17_F : RISCVReg32<17,"f17", ["fa7"]>, DwarfRegNum<[49]>;
+ def F18_F : RISCVReg32<18,"f18", ["fs2"]>, DwarfRegNum<[50]>;
+ def F19_F : RISCVReg32<19,"f19", ["fs3"]>, DwarfRegNum<[51]>;
+ def F20_F : RISCVReg32<20,"f20", ["fs4"]>, DwarfRegNum<[52]>;
+ def F21_F : RISCVReg32<21,"f21", ["fs5"]>, DwarfRegNum<[53]>;
+ def F22_F : RISCVReg32<22,"f22", ["fs6"]>, DwarfRegNum<[54]>;
+ def F23_F : RISCVReg32<23,"f23", ["fs7"]>, DwarfRegNum<[55]>;
+ def F24_F : RISCVReg32<24,"f24", ["fs8"]>, DwarfRegNum<[56]>;
+ def F25_F : RISCVReg32<25,"f25", ["fs9"]>, DwarfRegNum<[57]>;
+ def F26_F : RISCVReg32<26,"f26", ["fs10"]>, DwarfRegNum<[58]>;
+ def F27_F : RISCVReg32<27,"f27", ["fs11"]>, DwarfRegNum<[59]>;
+ def F28_F : RISCVReg32<28,"f28", ["ft8"]>, DwarfRegNum<[60]>;
+ def F29_F : RISCVReg32<29,"f29", ["ft9"]>, DwarfRegNum<[61]>;
+ def F30_F : RISCVReg32<30,"f30", ["ft10"]>, DwarfRegNum<[62]>;
+ def F31_F : RISCVReg32<31,"f31", ["ft11"]>, DwarfRegNum<[63]>;
foreach Index = 0-31 in {
- def F#Index#_64 : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_32")>,
+ def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>,
DwarfRegNum<[!add(Index, 32)]>;
}
}
@@ -207,29 +207,29 @@ let RegAltNameIndices = [ABIRegAltName] in {
// The order of registers represents the preferred allocation sequence,
// meaning caller-save regs are listed before callee-save.
def FPR32 : RegisterClass<"RISCV", [f32], 32, (add
- (sequence "F%u_32", 0, 7),
- (sequence "F%u_32", 10, 17),
- (sequence "F%u_32", 28, 31),
- (sequence "F%u_32", 8, 9),
- (sequence "F%u_32", 18, 27)
+ (sequence "F%u_F", 0, 7),
+ (sequence "F%u_F", 10, 17),
+ (sequence "F%u_F", 28, 31),
+ (sequence "F%u_F", 8, 9),
+ (sequence "F%u_F", 18, 27)
)>;
def FPR32C : RegisterClass<"RISCV", [f32], 32, (add
- (sequence "F%u_32", 10, 15),
- (sequence "F%u_32", 8, 9)
+ (sequence "F%u_F", 10, 15),
+ (sequence "F%u_F", 8, 9)
)>;
// The order of registers represents the preferred allocation sequence,
// meaning caller-save regs are listed before callee-save.
def FPR64 : RegisterClass<"RISCV", [f64], 64, (add
- (sequence "F%u_64", 0, 7),
- (sequence "F%u_64", 10, 17),
- (sequence "F%u_64", 28, 31),
- (sequence "F%u_64", 8, 9),
- (sequence "F%u_64", 18, 27)
+ (sequence "F%u_D", 0, 7),
+ (sequence "F%u_D", 10, 17),
+ (sequence "F%u_D", 28, 31),
+ (sequence "F%u_D", 8, 9),
+ (sequence "F%u_D", 18, 27)
)>;
def FPR64C : RegisterClass<"RISCV", [f64], 64, (add
- (sequence "F%u_64", 10, 15),
- (sequence "F%u_64", 8, 9)
+ (sequence "F%u_D", 10, 15),
+ (sequence "F%u_D", 8, 9)
)>;
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