diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/shrink-carry.mir | 101 |
2 files changed, 103 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index c5f121757e6..96a18544f02 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -92,6 +92,8 @@ static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, case AMDGPU::V_ADDC_U32_e64: case AMDGPU::V_SUBB_U32_e64: + if (TII->getNamedOperand(MI, AMDGPU::OpName::src1)->isImm()) + return false; // Additional verification is needed for sdst/src2. return true; diff --git a/llvm/test/CodeGen/AMDGPU/shrink-carry.mir b/llvm/test/CodeGen/AMDGPU/shrink-carry.mir new file mode 100644 index 00000000000..ce0cec75403 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/shrink-carry.mir @@ -0,0 +1,101 @@ +# RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s + +# GCN-LABEL: name: subbrev{{$}} +# GCN: V_SUBBREV_U32_e64 0, undef %vgpr0, killed %vcc, implicit %exec + +--- +name: subbrev +tracksRegLiveness: true +registers: + - { id: 0, class: vgpr_32 } + - { id: 1, class: vgpr_32 } + - { id: 2, class: vgpr_32 } + - { id: 3, class: sreg_64 } + - { id: 4, class: vgpr_32 } + - { id: 5, class: sreg_64 } +body: | + bb.0: + + %0 = IMPLICIT_DEF + %1 = IMPLICIT_DEF + %2 = IMPLICIT_DEF + %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec + %4, %5 = V_SUBBREV_U32_e64 0, %0, %3, implicit %exec + S_ENDPGM + +... + +# GCN-LABEL: name: subb{{$}} +# GCN: V_SUBB_U32_e64 undef %vgpr0, 0, killed %vcc, implicit %exec + +--- +name: subb +tracksRegLiveness: true +registers: + - { id: 0, class: vgpr_32 } + - { id: 1, class: vgpr_32 } + - { id: 2, class: vgpr_32 } + - { id: 3, class: sreg_64 } + - { id: 4, class: vgpr_32 } + - { id: 5, class: sreg_64 } +body: | + bb.0: + + %0 = IMPLICIT_DEF + %1 = IMPLICIT_DEF + %2 = IMPLICIT_DEF + %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec + %4, %5 = V_SUBB_U32_e64 %0, 0, %3, implicit %exec + S_ENDPGM + +... + +# GCN-LABEL: name: addc{{$}} +# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec + +--- +name: addc +tracksRegLiveness: true +registers: + - { id: 0, class: vgpr_32 } + - { id: 1, class: vgpr_32 } + - { id: 2, class: vgpr_32 } + - { id: 3, class: sreg_64 } + - { id: 4, class: vgpr_32 } + - { id: 5, class: sreg_64 } +body: | + bb.0: + + %0 = IMPLICIT_DEF + %1 = IMPLICIT_DEF + %2 = IMPLICIT_DEF + %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec + %4, %5 = V_ADDC_U32_e64 0, %0, %3, implicit %exec + S_ENDPGM + +... + +# GCN-LABEL: name: addc2{{$}} +# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec + +--- +name: addc2 +tracksRegLiveness: true +registers: + - { id: 0, class: vgpr_32 } + - { id: 1, class: vgpr_32 } + - { id: 2, class: vgpr_32 } + - { id: 3, class: sreg_64 } + - { id: 4, class: vgpr_32 } + - { id: 5, class: sreg_64 } +body: | + bb.0: + + %0 = IMPLICIT_DEF + %1 = IMPLICIT_DEF + %2 = IMPLICIT_DEF + %3 = V_CMP_GT_U32_e64 %0, %1, implicit %exec + %4, %5 = V_ADDC_U32_e64 %0, 0, %3, implicit %exec + S_ENDPGM + +... |
