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-rw-r--r--llvm/lib/Target/PowerPC/PPC.td55
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp6
-rw-r--r--llvm/lib/Target/PowerPC/PPCSubtarget.cpp2
-rw-r--r--llvm/lib/Target/PowerPC/PPCSubtarget.h4
-rw-r--r--llvm/lib/Target/PowerPC/PPCTargetMachine.cpp2
-rw-r--r--llvm/test/CodeGen/PowerPC/ppcsoftops.ll2
6 files changed, 45 insertions, 26 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 279c430e1ce..ee3d6501fae 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -53,40 +53,52 @@ def DirectivePwr9: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR9", "">;
def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
"Enable 64-bit instructions">;
-def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
- "Use software emulation for floating point">;
+def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
+ "Enable floating-point instructions">;
def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
"Enable 64-bit registers usage for ppc32 [beta]">;
def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
"Use condition-register bits individually">;
def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
- "Enable Altivec instructions">;
+ "Enable Altivec instructions",
+ [FeatureHardFloat]>;
def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
- "Enable SPE instructions">;
+ "Enable SPE instructions",
+ [FeatureHardFloat]>;
def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
"Enable the MFOCRF instruction">;
def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
- "Enable the fsqrt instruction">;
+ "Enable the fsqrt instruction",
+ [FeatureHardFloat]>;
def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
- "Enable the fcpsgn instruction">;
+ "Enable the fcpsgn instruction",
+ [FeatureHardFloat]>;
def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
- "Enable the fre instruction">;
+ "Enable the fre instruction",
+ [FeatureHardFloat]>;
def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
- "Enable the fres instruction">;
+ "Enable the fres instruction",
+ [FeatureHardFloat]>;
def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
- "Enable the frsqrte instruction">;
+ "Enable the frsqrte instruction",
+ [FeatureHardFloat]>;
def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
- "Enable the frsqrtes instruction">;
+ "Enable the frsqrtes instruction",
+ [FeatureHardFloat]>;
def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
"Assume higher precision reciprocal estimates">;
def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
- "Enable the stfiwx instruction">;
+ "Enable the stfiwx instruction",
+ [FeatureHardFloat]>;
def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
- "Enable the lfiwax instruction">;
+ "Enable the lfiwax instruction",
+ [FeatureHardFloat]>;
def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
- "Enable the fri[mnpz] instructions">;
+ "Enable the fri[mnpz] instructions",
+ [FeatureHardFloat]>;
def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
- "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
+ "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
+ [FeatureHardFloat]>;
def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
"Enable the isel instruction">;
def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true",
@@ -112,7 +124,8 @@ def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
"Enable PPC 6xx instructions">;
def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
- "Enable QPX instructions">;
+ "Enable QPX instructions",
+ [FeatureHardFloat]>;
def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
"Enable VSX instructions",
[FeatureAltivec]>;
@@ -282,7 +295,8 @@ include "PPCInstrInfo.td"
// PowerPC processors supported.
//
-def : Processor<"generic", G3Itineraries, [Directive32, FeatureMFTB]>;
+def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat,
+ FeatureMFTB]>;
def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
FeatureFRES, FeatureFRSQRTE,
FeatureICBT, FeatureBookE,
@@ -291,8 +305,8 @@ def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
FeatureFRES, FeatureFRSQRTE,
FeatureICBT, FeatureBookE,
FeatureMSYNC, FeatureMFTB]>;
-def : Processor<"601", G3Itineraries, [Directive601]>;
-def : Processor<"602", G3Itineraries, [Directive602,
+def : Processor<"601", G3Itineraries, [Directive601, FeatureHardFloat]>;
+def : Processor<"602", G3Itineraries, [Directive602, FeatureHardFloat,
FeatureMFTB]>;
def : Processor<"603", G3Itineraries, [Directive603,
FeatureFRES, FeatureFRSQRTE,
@@ -406,7 +420,10 @@ def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
// FIXME: Same as P8 until the POWER9 scheduling info is available
def : ProcessorModel<"pwr9", P8Model, ProcessorFeatures.Power9FeatureList>;
-def : Processor<"ppc", G3Itineraries, [Directive32, FeatureMFTB]>;
+def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
+ FeatureMFTB]>;
+def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
+ FeatureMFTB]>;
def : ProcessorModel<"ppc64", G5Model,
[Directive64, FeatureAltivec,
FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index d203404659e..614f368f557 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3175,7 +3175,7 @@ SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
};
const unsigned Num_GPR_Regs = array_lengthof(GPR);
- const unsigned Num_FPR_Regs = 13;
+ const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
const unsigned Num_VR_Regs = array_lengthof(VR);
const unsigned Num_QFPR_Regs = Num_FPR_Regs;
@@ -3588,7 +3588,7 @@ SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
};
const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
- const unsigned Num_FPR_Regs = 13;
+ const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
const unsigned Num_VR_Regs = array_lengthof( VR);
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
@@ -10564,7 +10564,7 @@ SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
N->getOpcode() == ISD::UINT_TO_FP) &&
"Need an int -> FP conversion node here");
- if (!Subtarget.has64BitSupport())
+ if (useSoftFloat() || !Subtarget.has64BitSupport())
return SDValue();
SelectionDAG &DAG = DCI.DAG;
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 19570735295..e8a87e7f443 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -62,7 +62,7 @@ void PPCSubtarget::initializeEnvironment() {
Has64BitSupport = false;
Use64BitRegs = false;
UseCRBits = false;
- UseSoftFloat = false;
+ HasHardFloat = false;
HasAltivec = false;
HasSPE = false;
HasQPX = false;
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index d80a9ad8d34..7fd907990ce 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -91,7 +91,7 @@ protected:
bool Has64BitSupport;
bool Use64BitRegs;
bool UseCRBits;
- bool UseSoftFloat;
+ bool HasHardFloat;
bool IsPPC64;
bool HasAltivec;
bool HasSPE;
@@ -205,7 +205,7 @@ public:
/// instructions, regardless of whether we are in 32-bit or 64-bit mode.
bool has64BitSupport() const { return Has64BitSupport; }
// useSoftFloat - Return true if soft-float option is turned on.
- bool useSoftFloat() const { return UseSoftFloat; }
+ bool useSoftFloat() const { return !HasHardFloat; }
/// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
/// registers in 32-bit mode when possible. This can only true if
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index a4ff86cb1e2..1bb6b674081 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -268,7 +268,7 @@ PPCTargetMachine::getSubtargetImpl(const Function &F) const {
// If the soft float attribute is set on the function turn on the soft float
// subtarget feature.
if (SoftFloat)
- FS += FS.empty() ? "+soft-float" : ",+soft-float";
+ FS += FS.empty() ? "-hard-float" : ",-hard-float";
auto &I = SubtargetMap[CPU + FS];
if (!I) {
diff --git a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
index 19c241d667f..5ecfbb4414e 100644
--- a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
+++ b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
@@ -1,4 +1,6 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -O0 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O0 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O0 < %s | FileCheck %s
; Testing operations in soft-float mode
define double @foo() #0 {
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