diff options
4 files changed, 43 insertions, 43 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 24e0a03667d..d9f095b7548 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -770,7 +770,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); if (Size == 1) { OpdsMapping[0] = OpdsMapping[1] = - OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); + OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size); break; } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir index c35327ff385..9e3d0233492 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir @@ -80,9 +80,9 @@ body: | ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1) - ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1) + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP1]](s1) + ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]] ; CHECK: S_NOP 0, implicit [[AND]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 @@ -106,9 +106,7 @@ body: | ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1) - ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]] + ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] ; CHECK: S_NOP 0, implicit [[AND]](s1) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 @@ -132,9 +130,8 @@ body: | ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1) - ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[COPY2]], [[COPY3]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1) + ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP1]] ; CHECK: S_NOP 0, implicit [[AND]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 @@ -156,7 +153,9 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32) - ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) + ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]] ; CHECK: S_NOP 0, implicit [[AND]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 @@ -178,8 +177,9 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[COPY2]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1) + ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]] ; CHECK: S_NOP 0, implicit [[AND]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 @@ -200,8 +200,8 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[COPY2]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP]] ; CHECK: S_NOP 0, implicit [[AND]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir index 0939b08c827..34c7f55886f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir @@ -80,9 +80,9 @@ body: | ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1) - ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[COPY2]], [[COPY3]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1) + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP1]](s1) + ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[COPY3]] ; CHECK: S_NOP 0, implicit [[OR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 @@ -106,9 +106,7 @@ body: | ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1) - ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[COPY2]], [[COPY3]] + ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[ICMP]], [[ICMP1]] ; CHECK: S_NOP 0, implicit [[OR]](s1) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 @@ -132,9 +130,8 @@ body: | ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1) - ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[COPY2]], [[COPY3]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1) + ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[ICMP1]] ; CHECK: S_NOP 0, implicit [[OR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 @@ -156,7 +153,9 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32) - ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[TRUNC]], [[TRUNC1]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) + ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[COPY3]] ; CHECK: S_NOP 0, implicit [[OR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 @@ -178,8 +177,9 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[TRUNC]], [[COPY2]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1) + ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[COPY3]] ; CHECK: S_NOP 0, implicit [[OR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 @@ -200,8 +200,8 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[TRUNC]], [[COPY2]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[ICMP]] ; CHECK: S_NOP 0, implicit [[OR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir index 33fe4d4ca27..f6544d00312 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir @@ -80,9 +80,9 @@ body: | ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1) - ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[COPY2]], [[COPY3]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1) + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP1]](s1) + ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[COPY3]] ; CHECK: S_NOP 0, implicit [[XOR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 @@ -106,9 +106,7 @@ body: | ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1) - ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[COPY2]], [[COPY3]] + ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[ICMP]], [[ICMP1]] ; CHECK: S_NOP 0, implicit [[XOR]](s1) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 @@ -132,9 +130,8 @@ body: | ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1) - ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[COPY2]], [[COPY3]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1) + ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[ICMP1]] ; CHECK: S_NOP 0, implicit [[XOR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 @@ -156,7 +153,9 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32) - ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[TRUNC]], [[TRUNC1]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) + ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[COPY3]] ; CHECK: S_NOP 0, implicit [[XOR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 @@ -178,8 +177,9 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[TRUNC]], [[COPY2]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1) + ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[COPY3]] ; CHECK: S_NOP 0, implicit [[XOR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 @@ -200,8 +200,8 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] - ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1) - ; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[TRUNC]], [[COPY2]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[ICMP]] ; CHECK: S_NOP 0, implicit [[XOR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 |
