diff options
69 files changed, 13168 insertions, 5709 deletions
diff --git a/llvm/include/llvm/BinaryFormat/ELF.h b/llvm/include/llvm/BinaryFormat/ELF.h index 5cedd99fdc0..c902972d93b 100644 --- a/llvm/include/llvm/BinaryFormat/ELF.h +++ b/llvm/include/llvm/BinaryFormat/ELF.h @@ -584,6 +584,7 @@ enum { EF_HEXAGON_MACH_V55 = 0x00000005, // Hexagon V55 EF_HEXAGON_MACH_V60 = 0x00000060, // Hexagon V60 EF_HEXAGON_MACH_V62 = 0x00000062, // Hexagon V62 + EF_HEXAGON_MACH_V65 = 0x00000065, // Hexagon V65 // Highest ISA version flags EF_HEXAGON_ISA_MACH = 0x00000000, // Same as specified in bits[11:0] @@ -595,6 +596,7 @@ enum { EF_HEXAGON_ISA_V55 = 0x00000050, // Hexagon V55 ISA EF_HEXAGON_ISA_V60 = 0x00000060, // Hexagon V60 ISA EF_HEXAGON_ISA_V62 = 0x00000062, // Hexagon V62 ISA + EF_HEXAGON_ISA_V65 = 0x00000065, // Hexagon V65 ISA }; // Hexagon-specific section indexes for common small data diff --git a/llvm/include/llvm/IR/IntrinsicsHexagon.td b/llvm/include/llvm/IR/IntrinsicsHexagon.td index 09824534472..5c96702bca7 100644 --- a/llvm/include/llvm/IR/IntrinsicsHexagon.td +++ b/llvm/include/llvm/IR/IntrinsicsHexagon.td @@ -5044,7 +5044,6 @@ def int_hexagon_V6_vassignp_128B : Hexagon_v2048v2048_Intrinsic_T<"HEXAGON_V6_vassignp_128B">; - // // Hexagon_iii_Intrinsic<string GCCIntSuffix> // tag : S6_rol_i_r @@ -5583,54 +5582,6 @@ class Hexagon_v1024i_Intrinsic<string GCCIntSuffix> [IntrNoMem]>; // -// Hexagon_v512v512LLii_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutb -class Hexagon_v512v512LLii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty,llvm_i32_ty], - [IntrNoMem]>; - -// -// Hexagon_v1024v1024LLii_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutb_128B -class Hexagon_v1024v1024LLii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty,llvm_i32_ty], - [IntrNoMem]>; - -// -// Hexagon_v512v512v512LLii_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutb_acc -class Hexagon_v512v512v512LLii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty,llvm_i32_ty], - [IntrNoMem]>; - -// -// Hexagon_v1024v1024v1024LLii_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutb_acc_128B -class Hexagon_v1024v1024v1024LLii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty,llvm_i32_ty], - [IntrNoMem]>; - -// -// Hexagon_v2048v2048LLii_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutb_dv_128B -class Hexagon_v2048v2048LLii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i64_ty,llvm_i32_ty], - [IntrNoMem]>; - -// -// Hexagon_v2048v2048v2048LLii_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutb_dv_acc_128B -class Hexagon_v2048v2048v2048LLii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i64_ty,llvm_i32_ty], - [IntrNoMem]>; - -// // Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix> // tag : V6_vlutvvb_oracc class Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix> @@ -9167,54 +9118,6 @@ def int_hexagon_V6_vcombine_128B : Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vcombine_128B">; // -// BUILTIN_INFO(HEXAGON.V6_vlutb,VI_ftype_VIDISI,3) -// tag : V6_vlutb -def int_hexagon_V6_vlutb : -Hexagon_v512v512LLii_Intrinsic<"HEXAGON_V6_vlutb">; - -// -// BUILTIN_INFO(HEXAGON.V6_vlutb_128B,VI_ftype_VIDISI,3) -// tag : V6_vlutb_128B -def int_hexagon_V6_vlutb_128B : -Hexagon_v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_128B">; - -// -// BUILTIN_INFO(HEXAGON.V6_vlutb_acc,VI_ftype_VIVIDISI,4) -// tag : V6_vlutb_acc -def int_hexagon_V6_vlutb_acc : -Hexagon_v512v512v512LLii_Intrinsic<"HEXAGON_V6_vlutb_acc">; - -// -// BUILTIN_INFO(HEXAGON.V6_vlutb_acc_128B,VI_ftype_VIVIDISI,4) -// tag : V6_vlutb_acc_128B -def int_hexagon_V6_vlutb_acc_128B : -Hexagon_v1024v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_acc_128B">; - -// -// BUILTIN_INFO(HEXAGON.V6_vlutb_dv,VD_ftype_VDDISI,3) -// tag : V6_vlutb_dv -def int_hexagon_V6_vlutb_dv : -Hexagon_v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_dv">; - -// -// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_128B,VD_ftype_VDDISI,3) -// tag : V6_vlutb_dv_128B -def int_hexagon_V6_vlutb_dv_128B : -Hexagon_v2048v2048LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_128B">; - -// -// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_acc,VD_ftype_VDVDDISI,4) -// tag : V6_vlutb_dv_acc -def int_hexagon_V6_vlutb_dv_acc : -Hexagon_v1024v1024v1024LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_acc">; - -// -// BUILTIN_INFO(HEXAGON.V6_vlutb_dv_acc_128B,VD_ftype_VDVDDISI,4) -// tag : V6_vlutb_dv_acc_128B -def int_hexagon_V6_vlutb_dv_acc_128B : -Hexagon_v2048v2048v2048LLii_Intrinsic<"HEXAGON_V6_vlutb_dv_acc_128B">; - -// // BUILTIN_INFO(HEXAGON.V6_vdelta,VI_ftype_VIVI,2) // tag : V6_vdelta def int_hexagon_V6_vdelta : @@ -9349,6 +9252,30 @@ Hexagon_v2048v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">; // // Masked vector stores // +def int_hexagon_V6_vS32b_qpred_ai : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">; + +def int_hexagon_V6_vS32b_nqpred_ai : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">; + +def int_hexagon_V6_vS32b_nt_qpred_ai : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">; + +def int_hexagon_V6_vS32b_nt_nqpred_ai : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">; + +def int_hexagon_V6_vS32b_qpred_ai_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">; + +def int_hexagon_V6_vS32b_nqpred_ai_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">; + +def int_hexagon_V6_vS32b_nt_qpred_ai_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">; + +def int_hexagon_V6_vS32b_nt_nqpred_ai_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">; + def int_hexagon_V6_vmaskedstoreq : Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">; @@ -9642,6 +9569,20 @@ class Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix> [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], [IntrNoMem]>; +// Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix> +// tag: V6_vaddcarry +class Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty, llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty], + [IntrNoMem]>; + +// Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix> +// tag: V6_vaddcarry_128B +class Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty, llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty], + [IntrNoMem]>; + // // BUILTIN_INFO(HEXAGON.M6_vabsdiffb,DI_ftype_DIDI,2) @@ -10213,3 +10154,821 @@ Hexagon_V62_v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh_nm">; def int_hexagon_V6_vlutvwh_nm_128B : Hexagon_V62_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">; +// +// BUILTIN_INFO(HEXAGON.V6_vaddcarry,VI_ftype_VIVIQV,3) +// tag: V6_vaddcarry +def int_hexagon_V6_vaddcarry : +Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vaddcarry">; + +// +// BUILTIN_INFO(HEXAGON.V6_vaddcarry_128B,VI_ftype_VIVIQV,3) +// tag: V6_vaddcarry_128B +def int_hexagon_V6_vaddcarry_128B : +Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vaddcarry_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vsubcarry,VI_ftype_VIVIQV,3) +// tag: V6_vsubcarry +def int_hexagon_V6_vsubcarry : +Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vsubcarry">; + +// +// BUILTIN_INFO(HEXAGON.V6_vsubcarry_128B,VI_ftype_VIVIQV,3) +// tag: V6_vsubcarry_128B +def int_hexagon_V6_vsubcarry_128B : +Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vsubcarry_128B">; + + +/// +/// HexagonV65 intrinsics +/// + +// +// Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix> +// tag : A6_vcmpbeq_notany +class Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix> +// tag : V6_vrmpyub_rtt +class Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix> +// tag : V6_vrmpyub_rtt_128B +class Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix> +// tag : V6_vrmpyub_rtt_acc +class Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix> +// tag : V6_vrmpyub_rtt_acc_128B +class Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix> +// tag : V6_vasruwuhsat +class Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix> +// tag : V6_vasruwuhsat_128B +class Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix> +// tag : V6_vavguw +class Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix> +// tag : V6_vavguw_128B +class Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix> +// tag : V6_vabsb +class Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix> +// tag : V6_vabsb_128B +class Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix> +// tag : V6_vmpabuu +class Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix> +// tag : V6_vmpabuu_128B +class Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix> +// tag : V6_vmpabuu_acc_128B +class Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix> +// tag : V6_vmpyh_acc +class Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix> +// tag : V6_vmpyh_acc_128B +class Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix> +// tag : V6_vmpahhsat +class Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix> +// tag : V6_vmpahhsat_128B +class Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix> +// tag : V6_vlut4 +class Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix> +// tag : V6_vlut4_128B +class Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix> +// tag : V6_vmpyuhe +class Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix> +// tag : V6_vprefixqb +class Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v512i1_ty], + [IntrNoMem]>; + +// +// Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix> +// tag : V6_vprefixqb_128B +class Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v1024i1_ty], + [IntrNoMem]>; + +// +// BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany,QI_ftype_DIDI,2) +// tag : A6_vcmpbeq_notany +def int_hexagon_A6_vcmpbeq_notany : +Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">; + +// +// BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany_128B,QI_ftype_DIDI,2) +// tag : A6_vcmpbeq_notany_128B +def int_hexagon_A6_vcmpbeq_notany_128B : +Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt,VD_ftype_VIDI,2) +// tag : V6_vrmpyub_rtt +def int_hexagon_V6_vrmpyub_rtt : +Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">; + +// +// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_128B,VD_ftype_VIDI,2) +// tag : V6_vrmpyub_rtt_128B +def int_hexagon_V6_vrmpyub_rtt_128B : +Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc,VD_ftype_VDVIDI,3) +// tag : V6_vrmpyub_rtt_acc +def int_hexagon_V6_vrmpyub_rtt_acc : +Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">; + +// +// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc_128B,VD_ftype_VDVIDI,3) +// tag : V6_vrmpyub_rtt_acc_128B +def int_hexagon_V6_vrmpyub_rtt_acc_128B : +Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt,VD_ftype_VIDI,2) +// tag : V6_vrmpybub_rtt +def int_hexagon_V6_vrmpybub_rtt : +Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">; + +// +// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_128B,VD_ftype_VIDI,2) +// tag : V6_vrmpybub_rtt_128B +def int_hexagon_V6_vrmpybub_rtt_128B : +Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc,VD_ftype_VDVIDI,3) +// tag : V6_vrmpybub_rtt_acc +def int_hexagon_V6_vrmpybub_rtt_acc : +Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">; + +// +// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc_128B,VD_ftype_VDVIDI,3) +// tag : V6_vrmpybub_rtt_acc_128B +def int_hexagon_V6_vrmpybub_rtt_acc_128B : +Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vasruwuhsat,VI_ftype_VIVISI,3) +// tag : V6_vasruwuhsat +def int_hexagon_V6_vasruwuhsat : +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruwuhsat">; + +// +// BUILTIN_INFO(HEXAGON.V6_vasruwuhsat_128B,VI_ftype_VIVISI,3) +// tag : V6_vasruwuhsat_128B +def int_hexagon_V6_vasruwuhsat_128B : +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vasruhubsat,VI_ftype_VIVISI,3) +// tag : V6_vasruhubsat +def int_hexagon_V6_vasruhubsat : +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubsat">; + +// +// BUILTIN_INFO(HEXAGON.V6_vasruhubsat_128B,VI_ftype_VIVISI,3) +// tag : V6_vasruhubsat_128B +def int_hexagon_V6_vasruhubsat_128B : +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat,VI_ftype_VIVISI,3) +// tag : V6_vasruhubrndsat +def int_hexagon_V6_vasruhubrndsat : +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubrndsat">; + +// +// BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat_128B,VI_ftype_VIVISI,3) +// tag : V6_vasruhubrndsat_128B +def int_hexagon_V6_vasruhubrndsat_128B : +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vaslh_acc,VI_ftype_VIVISI,3) +// tag : V6_vaslh_acc +def int_hexagon_V6_vaslh_acc : +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vaslh_acc">; + +// +// BUILTIN_INFO(HEXAGON.V6_vaslh_acc_128B,VI_ftype_VIVISI,3) +// tag : V6_vaslh_acc_128B +def int_hexagon_V6_vaslh_acc_128B : +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vasrh_acc,VI_ftype_VIVISI,3) +// tag : V6_vasrh_acc +def int_hexagon_V6_vasrh_acc : +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrh_acc">; + +// +// BUILTIN_INFO(HEXAGON.V6_vasrh_acc_128B,VI_ftype_VIVISI,3) +// tag : V6_vasrh_acc_128B +def int_hexagon_V6_vasrh_acc_128B : +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vavguw,VI_ftype_VIVI,2) +// tag : V6_vavguw +def int_hexagon_V6_vavguw : +Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguw">; + +// +// BUILTIN_INFO(HEXAGON.V6_vavguw_128B,VI_ftype_VIVI,2) +// tag : V6_vavguw_128B +def int_hexagon_V6_vavguw_128B : +Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguw_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vavguwrnd,VI_ftype_VIVI,2) +// tag : V6_vavguwrnd +def int_hexagon_V6_vavguwrnd : +Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguwrnd">; + +// +// BUILTIN_INFO(HEXAGON.V6_vavguwrnd_128B,VI_ftype_VIVI,2) +// tag : V6_vavguwrnd_128B +def int_hexagon_V6_vavguwrnd_128B : +Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vavgb,VI_ftype_VIVI,2) +// tag : V6_vavgb +def int_hexagon_V6_vavgb : +Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgb">; + +// +// BUILTIN_INFO(HEXAGON.V6_vavgb_128B,VI_ftype_VIVI,2) +// tag : V6_vavgb_128B +def int_hexagon_V6_vavgb_128B : +Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgb_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vavgbrnd,VI_ftype_VIVI,2) +// tag : V6_vavgbrnd +def int_hexagon_V6_vavgbrnd : +Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgbrnd">; + +// +// BUILTIN_INFO(HEXAGON.V6_vavgbrnd_128B,VI_ftype_VIVI,2) +// tag : V6_vavgbrnd_128B +def int_hexagon_V6_vavgbrnd_128B : +Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vnavgb,VI_ftype_VIVI,2) +// tag : V6_vnavgb +def int_hexagon_V6_vnavgb : +Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgb">; + +// +// BUILTIN_INFO(HEXAGON.V6_vnavgb_128B,VI_ftype_VIVI,2) +// tag : V6_vnavgb_128B +def int_hexagon_V6_vnavgb_128B : +Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgb_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vabsb,VI_ftype_VI,1) +// tag : V6_vabsb +def int_hexagon_V6_vabsb : +Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb">; + +// +// BUILTIN_INFO(HEXAGON.V6_vabsb_128B,VI_ftype_VI,1) +// tag : V6_vabsb_128B +def int_hexagon_V6_vabsb_128B : +Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vabsb_sat,VI_ftype_VI,1) +// tag : V6_vabsb_sat +def int_hexagon_V6_vabsb_sat : +Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb_sat">; + +// +// BUILTIN_INFO(HEXAGON.V6_vabsb_sat_128B,VI_ftype_VI,1) +// tag : V6_vabsb_sat_128B +def int_hexagon_V6_vabsb_sat_128B : +Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpabuu,VD_ftype_VDSI,2) +// tag : V6_vmpabuu +def int_hexagon_V6_vmpabuu : +Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpabuu_128B,VD_ftype_VDSI,2) +// tag : V6_vmpabuu_128B +def int_hexagon_V6_vmpabuu_128B : +Hexagon_V65_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc,VD_ftype_VDVDSI,3) +// tag : V6_vmpabuu_acc +def int_hexagon_V6_vmpabuu_acc : +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu_acc">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc_128B,VD_ftype_VDVDSI,3) +// tag : V6_vmpabuu_acc_128B +def int_hexagon_V6_vmpabuu_acc_128B : +Hexagon_V65_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpyh_acc,VD_ftype_VDVISI,3) +// tag : V6_vmpyh_acc +def int_hexagon_V6_vmpyh_acc : +Hexagon_V65_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyh_acc">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpyh_acc_128B,VD_ftype_VDVISI,3) +// tag : V6_vmpyh_acc_128B +def int_hexagon_V6_vmpyh_acc_128B : +Hexagon_V65_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpahhsat,VI_ftype_VIVIDI,3) +// tag : V6_vmpahhsat +def int_hexagon_V6_vmpahhsat : +Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpahhsat">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpahhsat_128B,VI_ftype_VIVIDI,3) +// tag : V6_vmpahhsat_128B +def int_hexagon_V6_vmpahhsat_128B : +Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat,VI_ftype_VIVIDI,3) +// tag : V6_vmpauhuhsat +def int_hexagon_V6_vmpauhuhsat : +Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat_128B,VI_ftype_VIVIDI,3) +// tag : V6_vmpauhuhsat_128B +def int_hexagon_V6_vmpauhuhsat_128B : +Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat,VI_ftype_VIVIDI,3) +// tag : V6_vmpsuhuhsat +def int_hexagon_V6_vmpsuhuhsat : +Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat_128B,VI_ftype_VIVIDI,3) +// tag : V6_vmpsuhuhsat_128B +def int_hexagon_V6_vmpsuhuhsat_128B : +Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vlut4,VI_ftype_VIDI,2) +// tag : V6_vlut4 +def int_hexagon_V6_vlut4 : +Hexagon_V65_v512v512LLi_Intrinsic<"HEXAGON_V6_vlut4">; + +// +// BUILTIN_INFO(HEXAGON.V6_vlut4_128B,VI_ftype_VIDI,2) +// tag : V6_vlut4_128B +def int_hexagon_V6_vlut4_128B : +Hexagon_V65_v1024v1024LLi_Intrinsic<"HEXAGON_V6_vlut4_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpyuhe,VI_ftype_VISI,2) +// tag : V6_vmpyuhe +def int_hexagon_V6_vmpyuhe : +Hexagon_V65_v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_128B,VI_ftype_VISI,2) +// tag : V6_vmpyuhe_128B +def int_hexagon_V6_vmpyuhe_128B : +Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc,VI_ftype_VIVISI,3) +// tag : V6_vmpyuhe_acc +def int_hexagon_V6_vmpyuhe_acc : +Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">; + +// +// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc_128B,VI_ftype_VIVISI,3) +// tag : V6_vmpyuhe_acc_128B +def int_hexagon_V6_vmpyuhe_acc_128B : +Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vprefixqb,VI_ftype_QV,1) +// tag : V6_vprefixqb +def int_hexagon_V6_vprefixqb : +Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqb">; + +// +// BUILTIN_INFO(HEXAGON.V6_vprefixqb_128B,VI_ftype_QV,1) +// tag : V6_vprefixqb_128B +def int_hexagon_V6_vprefixqb_128B : +Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqb_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vprefixqh,VI_ftype_QV,1) +// tag : V6_vprefixqh +def int_hexagon_V6_vprefixqh : +Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqh">; + +// +// BUILTIN_INFO(HEXAGON.V6_vprefixqh_128B,VI_ftype_QV,1) +// tag : V6_vprefixqh_128B +def int_hexagon_V6_vprefixqh_128B : +Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqh_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vprefixqw,VI_ftype_QV,1) +// tag : V6_vprefixqw +def int_hexagon_V6_vprefixqw : +Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqw">; + +// +// BUILTIN_INFO(HEXAGON.V6_vprefixqw_128B,VI_ftype_QV,1) +// tag : V6_vprefixqw_128B +def int_hexagon_V6_vprefixqw_128B : +Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqw_128B">; + + +// The scatter/gather ones below will not be generated from iset.py. Make sure +// you don't overwrite these. +class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, + llvm_v16i32_ty], + [IntrArgMemOnly]>; + +class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, + llvm_v32i32_ty], + [IntrArgMemOnly]>; + +class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, + llvm_v64i32_ty], + [IntrArgMemOnly]>; + +class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v16i32_ty], + [IntrArgMemOnly]>; + +class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v32i32_ty], + [IntrArgMemOnly]>; + +class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v32i32_ty], + [IntrArgMemOnly]>; + +class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v64i32_ty], + [IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermw : +Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">; + +def int_hexagon_V6_vgathermw_128B : +Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">; + +def int_hexagon_V6_vgathermh : +Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">; + +def int_hexagon_V6_vgathermh_128B : +Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">; + +def int_hexagon_V6_vgathermhw : +Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">; + +def int_hexagon_V6_vgathermhw_128B : +Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">; + +def int_hexagon_V6_vgathermwq : +Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">; + +def int_hexagon_V6_vgathermwq_128B : +Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">; + +def int_hexagon_V6_vgathermhq : +Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">; + +def int_hexagon_V6_vgathermhq_128B : +Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">; + +def int_hexagon_V6_vgathermhwq : +Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">; + +def int_hexagon_V6_vgathermhwq_128B : +Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">; + +class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_i32_ty,llvm_i32_ty, + llvm_v16i32_ty,llvm_v16i32_ty], + [IntrWriteMem]>; + +class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_i32_ty,llvm_i32_ty, + llvm_v32i32_ty,llvm_v32i32_ty], + [IntrWriteMem]>; + +class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_v512i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v16i32_ty, + llvm_v16i32_ty], + [IntrWriteMem]>; + +class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_v1024i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v32i32_ty, + llvm_v32i32_ty], + [IntrWriteMem]>; + +class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_i32_ty,llvm_i32_ty, + llvm_v32i32_ty,llvm_v16i32_ty], + [IntrWriteMem]>; + +class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_i32_ty,llvm_i32_ty, + llvm_v64i32_ty,llvm_v32i32_ty], + [IntrWriteMem]>; + +class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_v512i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v32i32_ty, + llvm_v16i32_ty], + [IntrWriteMem]>; + +class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [], [llvm_v1024i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v64i32_ty, + llvm_v32i32_ty], + [IntrWriteMem]>; + +class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [], + [IntrNoMem]>; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4) +// tag : V6_vscattermw +def int_hexagon_V6_vscattermw : +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4) +// tag : V6_vscattermw_128B +def int_hexagon_V6_vscattermw_128B : +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4) +// tag : V6_vscattermh +def int_hexagon_V6_vscattermh : +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4) +// tag : V6_vscattermh_128B +def int_hexagon_V6_vscattermh_128B : +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4) +// tag : V6_vscattermw_add +def int_hexagon_V6_vscattermw_add : +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4) +// tag : V6_vscattermw_add_128B +def int_hexagon_V6_vscattermw_add_128B : +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4) +// tag : V6_vscattermh_add +def int_hexagon_V6_vscattermh_add : +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4) +// tag : V6_vscattermh_add_128B +def int_hexagon_V6_vscattermh_add_128B : +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5) +// tag : V6_vscattermwq +def int_hexagon_V6_vscattermwq : +Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5) +// tag : V6_vscattermwq_128B +def int_hexagon_V6_vscattermwq_128B : +Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5) +// tag : V6_vscattermhq +def int_hexagon_V6_vscattermhq : +Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5) +// tag : V6_vscattermhq_128B +def int_hexagon_V6_vscattermhq_128B : +Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4) +// tag : V6_vscattermhw +def int_hexagon_V6_vscattermhw : +Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4) +// tag : V6_vscattermhw_128B +def int_hexagon_V6_vscattermhw_128B : +Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5) +// tag : V6_vscattermhwq +def int_hexagon_V6_vscattermhwq : +Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5) +// tag : V6_vscattermhwq_128B +def int_hexagon_V6_vscattermhwq_128B : +Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4) +// tag : V6_vscattermhw_add +def int_hexagon_V6_vscattermhw_add : +Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">; + +// +// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4) +// tag : V6_vscattermhw_add_128B +def int_hexagon_V6_vscattermhw_add_128B : +Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">; + +// +// BUILTIN_INFO(HEXAGON.V6_vdd0,VD_ftype_,0) +// tag : V6_vdd0 +def int_hexagon_V6_vdd0 : +Hexagon_v1024_Intrinsic<"HEXAGON_V6_vdd0">; + +// +// BUILTIN_INFO(HEXAGON.V6_vdd0_128B,VD_ftype_,0) +// tag : V6_vdd0_128B +def int_hexagon_V6_vdd0_128B : +Hexagon_V65_v2048_Intrinsic<"HEXAGON_V6_vdd0_128B">; diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index d0d8b39b83b..387296c69c3 100644 --- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -47,6 +47,7 @@ #include "llvm/Support/Format.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/SMLoc.h" +#include "llvm/Support/SourceMgr.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include <algorithm> @@ -60,9 +61,6 @@ using namespace llvm; -static cl::opt<bool> EnableFutureRegs("mfuture-regs", - cl::desc("Enable future registers")); - static cl::opt<bool> WarnMissingParenthesis( "mwarn-missing-parenthesis", cl::desc("Warn for missing parenthesis around predicate registers"), @@ -95,12 +93,20 @@ class HexagonAsmParser : public MCTargetAsmParser { } MCAsmParser &Parser; - MCAssembler *Assembler; MCInst MCB; bool InBrackets; MCAsmParser &getParser() const { return Parser; } - MCAssembler *getAssembler() const { return Assembler; } + MCAssembler *getAssembler() const { + MCAssembler *Assembler = nullptr; + // FIXME: need better way to detect AsmStreamer (upstream removed getKind()) + if (!Parser.getStreamer().hasRawTextSupport()) { + MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer()); + Assembler = &MES->getAssembler(); + } + return Assembler; + } + MCAsmLexer &getLexer() const { return Parser.getLexer(); } bool equalIsAsmAssignment() override { return false; } @@ -123,7 +129,7 @@ class HexagonAsmParser : public MCTargetAsmParser { bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc, OperandVector &InstOperands, uint64_t &ErrorInfo, bool MatchingInlineAsm); - + void eatToEndOfPacket(); bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, @@ -155,17 +161,11 @@ public: HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser, const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, _STI, MII), Parser(_Parser), - MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) { + InBrackets(false) { + MCB.setOpcode(Hexagon::BUNDLE); setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); MCAsmParserExtension::Initialize(_Parser); - - Assembler = nullptr; - // FIXME: need better way to detect AsmStreamer (upstream removed getKind()) - if (!Parser.getStreamer().hasRawTextSupport()) { - MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer()); - Assembler = &MES->getAssembler(); - } } bool splitIdentifier(OperandVector &Operands); @@ -190,6 +190,7 @@ public: /// instruction. struct HexagonOperand : public MCParsedAsmOperand { enum KindTy { Token, Immediate, Register } Kind; + MCContext &Context; SMLoc StartLoc, EndLoc; @@ -216,10 +217,12 @@ struct HexagonOperand : public MCParsedAsmOperand { struct ImmTy Imm; }; - HexagonOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} + HexagonOperand(KindTy K, MCContext &Context) + : MCParsedAsmOperand(), Kind(K), Context(Context) {} public: - HexagonOperand(const HexagonOperand &o) : MCParsedAsmOperand() { + HexagonOperand(const HexagonOperand &o) + : MCParsedAsmOperand(), Context(o.Context) { Kind = o.Kind; StartLoc = o.StartLoc; EndLoc = o.EndLoc; @@ -392,9 +395,13 @@ public: return; } int64_t Extended = SignExtend64(Value, 32); + HexagonMCExpr *NewExpr = HexagonMCExpr::create( + MCConstantExpr::create(Extended, Context), Context); if ((Extended < 0) != (Value < 0)) - Expr->setSignMismatch(); - Inst.addOperand(MCOperand::createExpr(Expr)); + NewExpr->setSignMismatch(); + NewExpr->setMustExtend(Expr->mustExtend()); + NewExpr->setMustNotExtend(Expr->mustNotExtend()); + Inst.addOperand(MCOperand::createExpr(NewExpr)); } void addn1ConstOperands(MCInst &Inst, unsigned N) const { @@ -408,8 +415,9 @@ public: void print(raw_ostream &OS) const override; - static std::unique_ptr<HexagonOperand> CreateToken(StringRef Str, SMLoc S) { - HexagonOperand *Op = new HexagonOperand(Token); + static std::unique_ptr<HexagonOperand> CreateToken(MCContext &Context, + StringRef Str, SMLoc S) { + HexagonOperand *Op = new HexagonOperand(Token, Context); Op->Tok.Data = Str.data(); Op->Tok.Length = Str.size(); Op->StartLoc = S; @@ -417,18 +425,18 @@ public: return std::unique_ptr<HexagonOperand>(Op); } - static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S, - SMLoc E) { - HexagonOperand *Op = new HexagonOperand(Register); + static std::unique_ptr<HexagonOperand> + CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) { + HexagonOperand *Op = new HexagonOperand(Register, Context); Op->Reg.RegNum = RegNum; Op->StartLoc = S; Op->EndLoc = E; return std::unique_ptr<HexagonOperand>(Op); } - static std::unique_ptr<HexagonOperand> CreateImm(const MCExpr *Val, SMLoc S, - SMLoc E) { - HexagonOperand *Op = new HexagonOperand(Immediate); + static std::unique_ptr<HexagonOperand> + CreateImm(MCContext &Context, const MCExpr *Val, SMLoc S, SMLoc E) { + HexagonOperand *Op = new HexagonOperand(Immediate, Context); Op->Imm.Val = Val; Op->StartLoc = S; Op->EndLoc = E; @@ -480,8 +488,8 @@ bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) { // 4 or less we have a packet that is too big. if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) { Error(IDLoc, "invalid instruction packet: out of slots"); - return true; // Error } + return true; // Error } return false; // No error @@ -493,13 +501,23 @@ bool HexagonAsmParser::matchBundleOptions() { if (!Parser.getTok().is(AsmToken::Colon)) return false; Lex(); + char const *MemNoShuffMsg = + "invalid instruction packet: mem_noshuf specifier not " + "supported with this architecture"; StringRef Option = Parser.getTok().getString(); + auto IDLoc = Parser.getTok().getLoc(); if (Option.compare_lower("endloop0") == 0) HexagonMCInstrInfo::setInnerLoop(MCB); else if (Option.compare_lower("endloop1") == 0) HexagonMCInstrInfo::setOuterLoop(MCB); + else if (Option.compare_lower("mem_noshuf") == 0) + if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf]) + HexagonMCInstrInfo::setMemReorderDisabled(MCB); + else + return getParser().Error(IDLoc, MemNoShuffMsg); else - return true; + return getParser().Error(IDLoc, llvm::Twine("'") + Option + + "' is not a valid bundle option"); Lex(); } } @@ -512,13 +530,13 @@ void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) { NewInst.setOpcode(MCI.getOpcode()); for (MCOperand &I : MCI) if (I.isImm()) { - int64_t Value (I.getImm()); + int64_t Value(I.getImm()); NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( MCConstantExpr::create(Value, getContext()), getContext()))); } else { if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() && WarnSignedMismatch) - Warning (MCI.getLoc(), "Signed/Unsigned mismatch"); + Warning(MCI.getLoc(), "Signed/Unsigned mismatch"); NewInst.addOperand(I); } MCI = NewInst; @@ -572,6 +590,15 @@ bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc, llvm_unreachable("Implement any new match types added!"); } +void HexagonAsmParser::eatToEndOfPacket() { + assert(InBrackets); + MCAsmLexer &Lexer = getLexer(); + while (!Lexer.is(AsmToken::RCurly)) + Lexer.Lex(); + Lexer.Lex(); + InBrackets = false; +} + bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, @@ -586,6 +613,7 @@ bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, assert(Operands.size() == 1 && "Brackets should be by themselves"); if (InBrackets) { getParser().Error(IDLoc, "Already in a packet"); + InBrackets = false; return true; } InBrackets = true; @@ -604,8 +632,11 @@ bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, } MCInst *SubInst = new (getParser().getContext()) MCInst; if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo, - MatchingInlineAsm)) + MatchingInlineAsm)) { + if (InBrackets) + eatToEndOfPacket(); return true; + } HexagonMCInstrInfo::extendIfNeeded( getParser().getContext(), MII, MCB, *SubInst); MCB.addOperand(MCOperand::createInst(SubInst)); @@ -853,10 +884,11 @@ bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) { do { std::pair<StringRef, StringRef> HeadTail = String.split('.'); if (!HeadTail.first.empty()) - Operands.push_back(HexagonOperand::CreateToken(HeadTail.first, Loc)); + Operands.push_back( + HexagonOperand::CreateToken(getContext(), HeadTail.first, Loc)); if (!HeadTail.second.empty()) Operands.push_back(HexagonOperand::CreateToken( - String.substr(HeadTail.first.size(), 1), Loc)); + getContext(), String.substr(HeadTail.first.size(), 1), Loc)); String = HeadTail.second; } while (!String.empty()); return false; @@ -878,38 +910,43 @@ bool HexagonAsmParser::parseOperand(OperandVector &Operands) { case Hexagon::P3: if (previousEqual(Operands, 0, "if")) { if (WarnMissingParenthesis) - Warning (Begin, "Missing parenthesis around predicate register"); + Warning(Begin, "Missing parenthesis around predicate register"); static char const *LParen = "("; static char const *RParen = ")"; - Operands.push_back(HexagonOperand::CreateToken(LParen, Begin)); - Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); + Operands.push_back( + HexagonOperand::CreateToken(getContext(), LParen, Begin)); + Operands.push_back( + HexagonOperand::CreateReg(getContext(), Register, Begin, End)); const AsmToken &MaybeDotNew = Lexer.getTok(); if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) && MaybeDotNew.getString().equals_lower(".new")) splitIdentifier(Operands); - Operands.push_back(HexagonOperand::CreateToken(RParen, Begin)); + Operands.push_back( + HexagonOperand::CreateToken(getContext(), RParen, Begin)); return false; } if (previousEqual(Operands, 0, "!") && previousEqual(Operands, 1, "if")) { if (WarnMissingParenthesis) - Warning (Begin, "Missing parenthesis around predicate register"); + Warning(Begin, "Missing parenthesis around predicate register"); static char const *LParen = "("; static char const *RParen = ")"; - Operands.insert(Operands.end () - 1, - HexagonOperand::CreateToken(LParen, Begin)); - Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); + Operands.insert(Operands.end() - 1, HexagonOperand::CreateToken( + getContext(), LParen, Begin)); + Operands.push_back( + HexagonOperand::CreateReg(getContext(), Register, Begin, End)); const AsmToken &MaybeDotNew = Lexer.getTok(); if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) && MaybeDotNew.getString().equals_lower(".new")) splitIdentifier(Operands); - Operands.push_back(HexagonOperand::CreateToken(RParen, Begin)); + Operands.push_back( + HexagonOperand::CreateToken(getContext(), RParen, Begin)); return false; } break; } - Operands.push_back(HexagonOperand::CreateReg( - Register, Begin, End)); + Operands.push_back( + HexagonOperand::CreateReg(getContext(), Register, Begin, End)); return false; } return splitIdentifier(Operands); @@ -931,10 +968,9 @@ bool HexagonAsmParser::isLabel(AsmToken &Token) { return true; if (!matchRegister(String.lower())) return true; - (void)Second; assert(Second.is(AsmToken::Colon)); - StringRef Raw (String.data(), Third.getString().data() - String.data() + - Third.getString().size()); + StringRef Raw(String.data(), Third.getString().data() - String.data() + + Third.getString().size()); std::string Collapsed = Raw; Collapsed.erase(llvm::remove_if(Collapsed, isspace), Collapsed.end()); StringRef Whole = Collapsed; @@ -944,7 +980,8 @@ bool HexagonAsmParser::isLabel(AsmToken &Token) { return false; } -bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) { +bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, + SMLoc &Loc) { if (!Contigious && ErrorNoncontigiousRegister) { Error(Loc, "Register name is not contigious"); return true; @@ -954,7 +991,8 @@ bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, SMLoc &Loc) return false; } -bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { +bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) { MCAsmLexer &Lexer = getLexer(); StartLoc = getLexer().getLoc(); SmallVector<AsmToken, 5> Lookahead; @@ -963,19 +1001,19 @@ bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &En bool NeededWorkaround = false; while (Again) { AsmToken const &Token = Lexer.getTok(); - RawString = StringRef(RawString.data(), - Token.getString().data() - RawString.data () + - Token.getString().size()); + RawString = StringRef(RawString.data(), Token.getString().data() - + RawString.data() + + Token.getString().size()); Lookahead.push_back(Token); Lexer.Lex(); bool Contigious = Lexer.getTok().getString().data() == Lookahead.back().getString().data() + - Lookahead.back().getString().size(); + Lookahead.back().getString().size(); bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) || Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) || Lexer.is(AsmToken::Colon); - bool Workaround = Lexer.is(AsmToken::Colon) || - Lookahead.back().is(AsmToken::Colon); + bool Workaround = + Lexer.is(AsmToken::Colon) || Lookahead.back().is(AsmToken::Colon); Again = (Contigious && Type) || (Workaround && Type); NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type)); } @@ -1005,10 +1043,10 @@ bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &En std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':'); unsigned ColonReg = matchRegister(ColonSplit.first.lower()); if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) { - Lexer.UnLex(Lookahead.back()); - Lookahead.pop_back(); - Lexer.UnLex(Lookahead.back()); - Lookahead.pop_back(); + do { + Lexer.UnLex(Lookahead.back()); + Lookahead.pop_back(); + } while (!Lookahead.empty () && !Lexer.is(AsmToken::Colon)); RegNo = ColonReg; EndLoc = Lexer.getLoc(); if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) @@ -1036,19 +1074,18 @@ bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) { return false; } -bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) { +bool HexagonAsmParser::parseExpression(MCExpr const *&Expr) { SmallVector<AsmToken, 4> Tokens; MCAsmLexer &Lexer = getLexer(); bool Done = false; - static char const * Comma = ","; + static char const *Comma = ","; do { - Tokens.emplace_back (Lexer.getTok()); + Tokens.emplace_back(Lexer.getTok()); Lex(); - switch (Tokens.back().getKind()) - { + switch (Tokens.back().getKind()) { case AsmToken::TokenKind::Hash: - if (Tokens.size () > 1) - if ((Tokens.end () - 2)->getKind() == AsmToken::TokenKind::Plus) { + if (Tokens.size() > 1) + if ((Tokens.end() - 2)->getKind() == AsmToken::TokenKind::Plus) { Tokens.insert(Tokens.end() - 2, AsmToken(AsmToken::TokenKind::Comma, Comma)); Done = true; @@ -1067,7 +1104,8 @@ bool HexagonAsmParser::parseExpression(MCExpr const *& Expr) { Lexer.UnLex(Tokens.back()); Tokens.pop_back(); } - return getParser().parseExpression(Expr); + SMLoc Loc = Lexer.getLoc(); + return getParser().parseExpression(Expr, Loc); } bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) { @@ -1078,7 +1116,8 @@ bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) { bool Error = parseExpression(Expr); Expr = HexagonMCExpr::create(Expr, getContext()); if (!Error) - Operands.push_back(HexagonOperand::CreateImm(Expr, Loc, Loc)); + Operands.push_back( + HexagonOperand::CreateImm(getContext(), Expr, Loc, Loc)); return Error; } return parseOperand(Operands); @@ -1091,6 +1130,7 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) { while (true) { AsmToken const &Token = Parser.getTok(); switch (Token.getKind()) { + case AsmToken::Eof: case AsmToken::EndOfStatement: { Lex(); return false; @@ -1098,15 +1138,15 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) { case AsmToken::LCurly: { if (!Operands.empty()) return true; - Operands.push_back( - HexagonOperand::CreateToken(Token.getString(), Token.getLoc())); + Operands.push_back(HexagonOperand::CreateToken( + getContext(), Token.getString(), Token.getLoc())); Lex(); return false; } case AsmToken::RCurly: { if (Operands.empty()) { - Operands.push_back( - HexagonOperand::CreateToken(Token.getString(), Token.getLoc())); + Operands.push_back(HexagonOperand::CreateToken( + getContext(), Token.getString(), Token.getLoc())); Lex(); } return false; @@ -1122,9 +1162,9 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) { case AsmToken::LessEqual: case AsmToken::LessLess: { Operands.push_back(HexagonOperand::CreateToken( - Token.getString().substr(0, 1), Token.getLoc())); + getContext(), Token.getString().substr(0, 1), Token.getLoc())); Operands.push_back(HexagonOperand::CreateToken( - Token.getString().substr(1, 1), Token.getLoc())); + getContext(), Token.getString().substr(1, 1), Token.getLoc())); Lex(); continue; } @@ -1133,8 +1173,8 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) { bool ImplicitExpression = implicitExpressionLocation(Operands); SMLoc ExprLoc = Lexer.getLoc(); if (!ImplicitExpression) - Operands.push_back( - HexagonOperand::CreateToken(Token.getString(), Token.getLoc())); + Operands.push_back(HexagonOperand::CreateToken( + getContext(), Token.getString(), Token.getLoc())); Lex(); bool MustExtend = false; bool HiOnly = false; @@ -1171,16 +1211,15 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) { if (Expr->evaluateAsAbsolute(Value)) { if (HiOnly) Expr = MCBinaryExpr::createLShr( - Expr, MCConstantExpr::create(16, Context), Context); + Expr, MCConstantExpr::create(16, Context), Context); if (HiOnly || LoOnly) - Expr = MCBinaryExpr::createAnd(Expr, - MCConstantExpr::create(0xffff, Context), - Context); + Expr = MCBinaryExpr::createAnd( + Expr, MCConstantExpr::create(0xffff, Context), Context); } else { MCValue Value; if (Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) { if (!Value.isAbsolute()) { - switch(Value.getAccessVariant()) { + switch (Value.getAccessVariant()) { case MCSymbolRefExpr::VariantKind::VK_TPREL: case MCSymbolRefExpr::VariantKind::VK_DTPREL: // Don't lazy extend these expression variants @@ -1196,7 +1235,7 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) { HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend); HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend); std::unique_ptr<HexagonOperand> Operand = - HexagonOperand::CreateImm(Expr, ExprLoc, ExprLoc); + HexagonOperand::CreateImm(getContext(), Expr, ExprLoc, ExprLoc); Operands.push_back(std::move(Operand)); continue; } @@ -1209,15 +1248,14 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) { } bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info, - StringRef Name, - AsmToken ID, + StringRef Name, AsmToken ID, OperandVector &Operands) { getLexer().UnLex(ID); return parseInstruction(Operands); } -static MCInst makeCombineInst(int opCode, MCOperand &Rdd, - MCOperand &MO1, MCOperand &MO2) { +static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, + MCOperand &MO2) { MCInst TmpInst; TmpInst.setOpcode(opCode); TmpInst.addOperand(Rdd); @@ -1286,6 +1324,13 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, bool is32bit = false; // used to distinguish between CONST32 and CONST64 switch (Inst.getOpcode()) { default: + if (HexagonMCInstrInfo::getDesc(MII, Inst).isPseudo()) { + SMDiagnostic Diag = getSourceManager().GetMessage( + IDLoc, SourceMgr::DK_Error, + "Found pseudo instruction with no expansion"); + Diag.print("", errs()); + report_fatal_error("Invalid pseudo instruction"); + } break; case Hexagon::A2_iconst: { @@ -1319,8 +1364,10 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, case Hexagon::C2_cmpgei: { MCOperand &MO = Inst.getOperand(2); - MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( - MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context)); + MO.setExpr(HexagonMCExpr::create( + MCBinaryExpr::createSub(MO.getExpr(), + MCConstantExpr::create(1, Context), Context), + Context)); Inst.setOpcode(Hexagon::C2_cmpgti); break; } @@ -1341,8 +1388,10 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, TmpInst.addOperand(Rt); Inst = TmpInst; } else { - MO.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( - MO.getExpr(), MCConstantExpr::create(1, Context), Context), Context)); + MO.setExpr(HexagonMCExpr::create( + MCBinaryExpr::createSub(MO.getExpr(), + MCConstantExpr::create(1, Context), Context), + Context)); Inst.setOpcode(Hexagon::C2_cmpgtui); } break; @@ -1509,7 +1558,7 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, TmpInst.addOperand(MO_0); TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( - MCSymbolRefExpr::create(Sym, getContext()), getContext()))); + MCSymbolRefExpr::create(Sym, getContext()), getContext()))); Inst = TmpInst; } } @@ -1540,7 +1589,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, MCConstantExpr::create(s8, Context), Context))); // upper 32 auto Expr = HexagonMCExpr::create( MCConstantExpr::create(Lo_32(Value), Context), Context); - HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr())); + HexagonMCInstrInfo::setMustExtend( + *Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr())); MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); } else { @@ -1588,15 +1638,16 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, case Hexagon::S2_tableidxh_goodsyntax: { MCInst TmpInst; MCOperand &Rx = Inst.getOperand(0); - MCOperand &_dst_ = Inst.getOperand(1); MCOperand &Rs = Inst.getOperand(2); MCOperand &Imm4 = Inst.getOperand(3); MCOperand &Imm6 = Inst.getOperand(4); - Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( - Imm6.getExpr(), MCConstantExpr::create(1, Context), Context), Context)); + Imm6.setExpr(HexagonMCExpr::create( + MCBinaryExpr::createSub(Imm6.getExpr(), + MCConstantExpr::create(1, Context), Context), + Context)); TmpInst.setOpcode(Hexagon::S2_tableidxh); TmpInst.addOperand(Rx); - TmpInst.addOperand(_dst_); + TmpInst.addOperand(Rx); TmpInst.addOperand(Rs); TmpInst.addOperand(Imm4); TmpInst.addOperand(Imm6); @@ -1607,15 +1658,16 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, case Hexagon::S2_tableidxw_goodsyntax: { MCInst TmpInst; MCOperand &Rx = Inst.getOperand(0); - MCOperand &_dst_ = Inst.getOperand(1); MCOperand &Rs = Inst.getOperand(2); MCOperand &Imm4 = Inst.getOperand(3); MCOperand &Imm6 = Inst.getOperand(4); - Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( - Imm6.getExpr(), MCConstantExpr::create(2, Context), Context), Context)); + Imm6.setExpr(HexagonMCExpr::create( + MCBinaryExpr::createSub(Imm6.getExpr(), + MCConstantExpr::create(2, Context), Context), + Context)); TmpInst.setOpcode(Hexagon::S2_tableidxw); TmpInst.addOperand(Rx); - TmpInst.addOperand(_dst_); + TmpInst.addOperand(Rx); TmpInst.addOperand(Rs); TmpInst.addOperand(Imm4); TmpInst.addOperand(Imm6); @@ -1626,15 +1678,16 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, case Hexagon::S2_tableidxd_goodsyntax: { MCInst TmpInst; MCOperand &Rx = Inst.getOperand(0); - MCOperand &_dst_ = Inst.getOperand(1); MCOperand &Rs = Inst.getOperand(2); MCOperand &Imm4 = Inst.getOperand(3); MCOperand &Imm6 = Inst.getOperand(4); - Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( - Imm6.getExpr(), MCConstantExpr::create(3, Context), Context), Context)); + Imm6.setExpr(HexagonMCExpr::create( + MCBinaryExpr::createSub(Imm6.getExpr(), + MCConstantExpr::create(3, Context), Context), + Context)); TmpInst.setOpcode(Hexagon::S2_tableidxd); TmpInst.addOperand(Rx); - TmpInst.addOperand(_dst_); + TmpInst.addOperand(Rx); TmpInst.addOperand(Rs); TmpInst.addOperand(Imm4); TmpInst.addOperand(Imm6); @@ -1655,21 +1708,15 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, bool Absolute = Expr.evaluateAsAbsolute(Value); assert(Absolute); (void)Absolute; - if (!HexagonMCInstrInfo::mustExtend(Expr)) { - if (Value < 0 && Value > -256) { - Imm.setExpr(HexagonMCExpr::create( - MCConstantExpr::create(Value * -1, Context), Context)); - TmpInst.setOpcode(Hexagon::M2_mpysin); - } else if (Value < 256 && Value >= 0) - TmpInst.setOpcode(Hexagon::M2_mpysip); - else - return Match_InvalidOperand; - } else { - if (Value >= 0) - TmpInst.setOpcode(Hexagon::M2_mpysip); - else - return Match_InvalidOperand; - } + if (!HexagonMCInstrInfo::mustExtend(Expr) && + ((Value <= -256) || Value >= 256)) + return Match_InvalidOperand; + if (Value < 0 && Value > -256) { + Imm.setExpr(HexagonMCExpr::create( + MCConstantExpr::create(Value * -1, Context), Context)); + TmpInst.setOpcode(Hexagon::M2_mpysin); + } else + TmpInst.setOpcode(Hexagon::M2_mpysip); TmpInst.addOperand(Rd); TmpInst.addOperand(Rs); TmpInst.addOperand(Imm); @@ -1952,7 +1999,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, break; case Hexagon::A2_zxtb: { Inst.setOpcode(Hexagon::A2_andir); - Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, Context))); + Inst.addOperand( + MCOperand::createExpr(MCConstantExpr::create(255, Context))); break; } } // switch diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt b/llvm/lib/Target/Hexagon/CMakeLists.txt index 9f30f2b7cc3..1c36093923a 100644 --- a/llvm/lib/Target/Hexagon/CMakeLists.txt +++ b/llvm/lib/Target/Hexagon/CMakeLists.txt @@ -27,6 +27,7 @@ add_llvm_target(HexagonCodeGen HexagonExpandCondsets.cpp HexagonFixupHwLoops.cpp HexagonFrameLowering.cpp + HexagonGatherPacketize.cpp HexagonGenExtract.cpp HexagonGenInsert.cpp HexagonGenMux.cpp diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index c26ba3db8ef..8a6bb475696 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -45,10 +45,12 @@ class HexagonDisassembler : public MCDisassembler { public: std::unique_ptr<MCInstrInfo const> const MCII; std::unique_ptr<MCInst *> CurrentBundle; + mutable MCInst const *CurrentExtender; HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII) - : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *) {} + : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), + CurrentExtender(nullptr) {} DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address, @@ -58,40 +60,38 @@ public: ArrayRef<uint8_t> Bytes, uint64_t Address, raw_ostream &VStream, raw_ostream &CStream) const override; - void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; + void remapInstruction(MCInst &Instr) const; }; -} // end anonymous namespace - -static uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, +static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI, int64_t Value) { - MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( - MCB, HexagonMCInstrInfo::bundleSize(MCB)); - if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) + MCInstrInfo MCII = *Disassembler.MCII; + if (!Disassembler.CurrentExtender || + MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) return Value; unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; int64_t Bits; - bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); - assert(Success); (void)Success; - uint32_t Upper26 = static_cast<uint32_t>(Bits); - uint32_t Operand = Upper26 | Lower6; + bool Success = + Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute( + Bits); + assert(Success); + (void)Success; + uint64_t Upper26 = static_cast<uint64_t>(Bits); + uint64_t Operand = Upper26 | Lower6; return Operand; } - static HexagonDisassembler const &disassembler(void const *Decoder) { return *static_cast<HexagonDisassembler const *>(Decoder); } - template <size_t T> static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); - int64_t FullValue = - fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, - SignExtend64<T>(tmp)); + int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp)); int64_t Extended = SignExtend64<32>(FullValue); HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); } +} // Forward declare these because the auto-generated code will reference them. // Definitions are further down. @@ -107,8 +107,8 @@ static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, + const void *Decoder); static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); @@ -116,14 +116,14 @@ static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, + const void *Decoder); static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, + const void *Decoder); static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); @@ -141,62 +141,7 @@ static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); -static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, - const void *Decoder) { - signedDecoder<4>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, - const void *Decoder) { - signedDecoder<14>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, - const void *Decoder) { - signedDecoder<8>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, - const void *Decoder) { - signedDecoder<7>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, - const void *Decoder) { - signedDecoder<12>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, - const void *Decoder) { - signedDecoder<3>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, - const void *Decoder) { - signedDecoder<13>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, - const void *Decoder) { - signedDecoder<6>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, - const void *Decoder) { - signedDecoder<9>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, - const void *Decoder) { - signedDecoder<5>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, - const void *Decoder) { - signedDecoder<6>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - +#include "HexagonDepDecoders.h" #include "HexagonGenDisassemblerTables.inc" static MCDisassembler *createHexagonDisassembler(const Target &T, @@ -215,12 +160,15 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &os, raw_ostream &cs) const { + (void)&s10_0ImmDecoder; + (void)&s10_6ImmDecoder; DecodeStatus Result = DecodeStatus::Success; bool Complete = false; Size = 0; *CurrentBundle = &MI; - MI = HexagonMCInstrInfo::createBundle(); + MI.setOpcode(Hexagon::BUNDLE); + MI.addOperand(MCOperand::createImm(0)); while (Result == Success && !Complete) { if (Bytes.size() < HEXAGON_INSTR_SIZE) return MCDisassembler::Fail; @@ -238,9 +186,89 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, *getContext().getRegisterInfo(), false); if (!Checker.check()) return MCDisassembler::Fail; + remapInstruction(MI); return MCDisassembler::Success; } +void HexagonDisassembler::remapInstruction(MCInst &Instr) const { + for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) { + auto &MI = const_cast<MCInst &>(*I.getInst()); + switch (MI.getOpcode()) { + case Hexagon::S2_allocframe: + if (MI.getOperand(0).getReg() == Hexagon::R29) { + MI.setOpcode(Hexagon::S6_allocframe_to_raw); + MI.erase(MI.begin () + 1); + MI.erase(MI.begin ()); + } + break; + case Hexagon::L2_deallocframe: + if (MI.getOperand(0).getReg() == Hexagon::D15 && + MI.getOperand(1).getReg() == Hexagon::R30) { + MI.setOpcode(L6_deallocframe_map_to_raw); + MI.erase(MI.begin () + 1); + MI.erase(MI.begin ()); + } + break; + case Hexagon::L4_return: + if (MI.getOperand(0).getReg() == Hexagon::D15 && + MI.getOperand(1).getReg() == Hexagon::R30) { + MI.setOpcode(L6_return_map_to_raw); + MI.erase(MI.begin () + 1); + MI.erase(MI.begin ()); + } + break; + case Hexagon::L4_return_t: + if (MI.getOperand(0).getReg() == Hexagon::D15 && + MI.getOperand(2).getReg() == Hexagon::R30) { + MI.setOpcode(L4_return_map_to_raw_t); + MI.erase(MI.begin () + 2); + MI.erase(MI.begin ()); + } + break; + case Hexagon::L4_return_f: + if (MI.getOperand(0).getReg() == Hexagon::D15 && + MI.getOperand(2).getReg() == Hexagon::R30) { + MI.setOpcode(L4_return_map_to_raw_f); + MI.erase(MI.begin () + 2); + MI.erase(MI.begin ()); + } + break; + case Hexagon::L4_return_tnew_pt: + if (MI.getOperand(0).getReg() == Hexagon::D15 && + MI.getOperand(2).getReg() == Hexagon::R30) { + MI.setOpcode(L4_return_map_to_raw_tnew_pt); + MI.erase(MI.begin () + 2); + MI.erase(MI.begin ()); + } + break; + case Hexagon::L4_return_fnew_pt: + if (MI.getOperand(0).getReg() == Hexagon::D15 && + MI.getOperand(2).getReg() == Hexagon::R30) { + MI.setOpcode(L4_return_map_to_raw_fnew_pt); + MI.erase(MI.begin () + 2); + MI.erase(MI.begin ()); + } + break; + case Hexagon::L4_return_tnew_pnt: + if (MI.getOperand(0).getReg() == Hexagon::D15 && + MI.getOperand(2).getReg() == Hexagon::R30) { + MI.setOpcode(L4_return_map_to_raw_tnew_pnt); + MI.erase(MI.begin () + 2); + MI.erase(MI.begin ()); + } + break; + case Hexagon::L4_return_fnew_pnt: + if (MI.getOperand(0).getReg() == Hexagon::D15 && + MI.getOperand(2).getReg() == Hexagon::R30) { + MI.setOpcode(L4_return_map_to_raw_fnew_pnt); + MI.erase(MI.begin () + 2); + MI.erase(MI.begin ()); + } + break; + } + } +} + static void adjustDuplex(MCInst &MI, MCContext &Context) { switch (MI.getOpcode()) { case Hexagon::SA1_setin1: @@ -274,7 +302,7 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( return DecodeStatus::Fail; } - MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( + CurrentExtender = HexagonMCInstrInfo::extenderForIndex( MCB, HexagonMCInstrInfo::bundleSize(MCB)); DecodeStatus Result = DecodeStatus::Fail; @@ -350,8 +378,12 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); MCInst *MILow = new (getContext()) MCInst; MCInst *MIHigh = new (getContext()) MCInst; + auto TmpExtender = CurrentExtender; + CurrentExtender = + nullptr; // constant extenders in duplex must always be in slot 1 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, this, STI); + CurrentExtender = TmpExtender; if (Result != DecodeStatus::Success) return DecodeStatus::Fail; adjustDuplex(*MILow, getContext()); @@ -370,7 +402,7 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( HexagonII::INST_PARSE_PACKET_END) Complete = true; - if (Extender != nullptr) + if (CurrentExtender != nullptr) Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, Address, this, STI); @@ -429,25 +461,29 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( unsigned Lookback = (Register & 0x6) >> 1; unsigned Offset = 1; bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); + bool PrevVector = false; auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); auto i = Instructions.end() - 1; for (auto n = Instructions.begin() - 1;; --i, ++Offset) { if (i == n) // Couldn't find producer return MCDisassembler::Fail; - if (Vector && !HexagonMCInstrInfo::isVector(*MCII, *i->getInst())) + bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst()); + if (Vector && !CurrentVector) // Skip scalars when calculating distances for vectors ++Lookback; - if (HexagonMCInstrInfo::isImmext(*i->getInst())) + if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector)) ++Lookback; + PrevVector = CurrentVector; if (Offset == Lookback) break; } auto const &Inst = *i->getInst(); bool SubregBit = (Register & 0x1) != 0; - if (SubregBit && HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { + if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) { // If subreg bit is set we're selecting the second produced newvalue - unsigned Producer = + unsigned Producer = SubregBit ? + HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() : HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg(); assert(Producer != Hexagon::NoRegister); MCO.setReg(Producer); @@ -466,7 +502,7 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( return MCDisassembler::Fail; } - if (Extender != nullptr) { + if (CurrentExtender != nullptr) { MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) ? *MI.getOperand(1).getInst() : MI; @@ -666,8 +702,7 @@ static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, const void *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); - int64_t FullValue = - fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, tmp); + int64_t FullValue = fullValue(Disassembler, MI, tmp); assert(FullValue >= 0 && "Negative in unsigned decoder"); HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); return MCDisassembler::Success; @@ -690,10 +725,8 @@ static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, // r13_2 is not extendable, so if there are no extent bits, it's r13_2 if (Bits == 0) Bits = 15; - uint32_t FullValue = - fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, - SignExtend64(tmp, Bits)); - int64_t Extended = SignExtend64<32>(FullValue) + Address; + uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits)); + uint32_t Extended = FullValue + Address; if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); return MCDisassembler::Success; diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index 3218f2510e5..6292e2a7a4e 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -25,33 +25,36 @@ include "llvm/Target/Target.td" include "HexagonDepArch.td" // Hexagon ISA Extensions -def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion", +def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion", "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">; +def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion", + "Hexagon::ArchEnum::V60", "Hexagon HVX instructions", + [ExtensionHVX]>; def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion", "Hexagon::ArchEnum::V62", "Hexagon HVX instructions", - [ExtensionHVXV60]>; -def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion", - "Hexagon::ArchEnum::V62", "Hexagon HVX instructions", - [ExtensionHVXV60, - ExtensionHVXV62]>; + [ExtensionHVX,ExtensionHVXV60]>; +def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion", + "Hexagon::ArchEnum::V65", "Hexagon HVX instructions", + [ExtensionHVX,ExtensionHVXV60, ExtensionHVXV62]>; def ExtensionHVX64B : SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true", - "Hexagon HVX 64B instructions", - [ExtensionHVXV60, ExtensionHVXV62]>; + "Hexagon HVX 64B instructions", [ExtensionHVX]>; def ExtensionHVX128B : SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true", - "Hexagon HVX 128B instructions", - [ExtensionHVXV60, ExtensionHVXV62]>; + "Hexagon HVX 128B instructions", [ExtensionHVX]>; // This is an alias to ExtensionHVX128B to accept the hvx-double as // an acceptable subtarget feature. def ExtensionHVXDbl : SubtargetFeature<"hvx-double", "UseHVX128BOps", "true", - "Hexagon HVX 128B instructions", - [ExtensionHVXV60, ExtensionHVXV62]>; + "Hexagon HVX 128B instructions", [ExtensionHVX128B]>; def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", "Use constant-extended calls">; +def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false", + "Supports mem_noshuf feature">; +def FeatureDuplex : SubtargetFeature<"duplex", "EnableDuplex", "true", + "Enable generation of duplex instruction">; //===----------------------------------------------------------------------===// // Hexagon Instruction Predicate Definitions. @@ -69,6 +72,8 @@ def UseHVXV60 : Predicate<"HST->useHVXOps()">, AssemblerPredicate<"ExtensionHVXV60">; def UseHVXV62 : Predicate<"HST->useHVXOps()">, AssemblerPredicate<"ExtensionHVXV62">; +def UseHVXV65 : Predicate<"HST->useHVXOps()">, + AssemblerPredicate<"ExtensionHVXV65">; def Hvx64 : HwMode<"+hvx-length64b">; def Hvx64old : HwMode<"-hvx-double">; @@ -80,21 +85,22 @@ def Hvx128old : HwMode<"+hvx-double">; //===----------------------------------------------------------------------===// class ImmRegShl; +// ImmRegRel - Filter class used to relate instructions having reg-reg form +// with their reg-imm counterparts. +class ImmRegRel; // PredRel - Filter class used to relate non-predicated instructions with their // predicated forms. class PredRel; // PredNewRel - Filter class used to relate predicated instructions with their // predicate-new forms. class PredNewRel: PredRel; -// ImmRegRel - Filter class used to relate instructions having reg-reg form -// with their reg-imm counterparts. -class ImmRegRel; // NewValueRel - Filter class used to relate regular store instructions with // their new-value store form. class NewValueRel: PredNewRel; // NewValueRel - Filter class used to relate load/store instructions having // different addressing modes with each other. class AddrModeRel: NewValueRel; +class PostInc_BaseImm; class IntrinsicsRel; //===----------------------------------------------------------------------===// @@ -220,6 +226,22 @@ def changeAddrMode_rr_io: InstrMapping { let ValueCols = [["BaseImmOffset"]]; } +def changeAddrMode_pi_io: InstrMapping { + let FilterClass = "PostInc_BaseImm"; + let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; + let ColFields = ["addrMode"]; + let KeyCol = ["PostInc"]; + let ValueCols = [["BaseImmOffset"]]; +} + +def changeAddrMode_io_pi: InstrMapping { + let FilterClass = "PostInc_BaseImm"; + let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; + let ColFields = ["addrMode"]; + let KeyCol = ["BaseImmOffset"]; + let ValueCols = [["PostInc"]]; +} + def changeAddrMode_rr_ur: InstrMapping { let FilterClass = "ImmRegShl"; let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"]; @@ -268,7 +290,7 @@ def getRealHWInstr : InstrMapping { let ValueCols = [["Pseudo"], ["Real"]]; } //===----------------------------------------------------------------------===// -// Register File, Calling Conv, Instruction Descriptions +// Register File, Instruction Descriptions //===----------------------------------------------------------------------===// include "HexagonSchedule.td" include "HexagonRegisterInfo.td" @@ -280,9 +302,11 @@ include "HexagonDepInstrFormats.td" include "HexagonDepInstrInfo.td" include "HexagonPseudo.td" include "HexagonPatterns.td" +include "HexagonPatternsV65.td" include "HexagonDepMappings.td" include "HexagonIntrinsics.td" include "HexagonMapAsm2IntrinV62.gen.td" +include "HexagonMapAsm2IntrinV65.gen.td" def HexagonInstrInfo : InstrInfo; @@ -295,15 +319,18 @@ class Proc<string Name, SchedMachineModel Model, : ProcessorModel<Name, Model, Features>; def : Proc<"hexagonv4", HexagonModelV4, - [ArchV4]>; + [ArchV4, FeatureDuplex]>; def : Proc<"hexagonv5", HexagonModelV4, - [ArchV4, ArchV5]>; + [ArchV4, ArchV5, FeatureDuplex]>; def : Proc<"hexagonv55", HexagonModelV55, - [ArchV4, ArchV5, ArchV55]>; + [ArchV4, ArchV5, ArchV55, FeatureDuplex]>; def : Proc<"hexagonv60", HexagonModelV60, - [ArchV4, ArchV5, ArchV55, ArchV60]>; + [ArchV4, ArchV5, ArchV55, ArchV60, FeatureDuplex]>; def : Proc<"hexagonv62", HexagonModelV62, - [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62]>; + [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, FeatureDuplex]>; +def : Proc<"hexagonv65", HexagonModelV65, + [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, + FeatureMemNoShuf, FeatureDuplex]>; //===----------------------------------------------------------------------===// // Declare the target which we are implementing @@ -317,11 +344,17 @@ def HexagonAsmParser : AsmParser { def HexagonAsmParserVariant : AsmParserVariant { int Variant = 0; string TokenizingCharacters = "#()=:.<>!+*-|^&"; + string BreakCharacters = ""; +} + +def HexagonAsmWriter : AsmWriter { + string AsmWriterClassName = "InstPrinter"; + bit isMCAsmWriter = 1; } def Hexagon : Target { - // Pull in Instruction Info: let InstructionSet = HexagonInstrInfo; let AssemblyParsers = [HexagonAsmParser]; let AssemblyParserVariants = [HexagonAsmParserVariant]; + let AssemblyWriters = [HexagonAsmWriter]; } diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp index b69299511bc..68b1fe6bf4b 100644 --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -615,7 +615,18 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, MappedInst = TmpInst; return; } + case Hexagon::V6_vdd0: { + MCInst TmpInst; + assert (Inst.getOperand(0).isReg() && + "Expected register and none was found"); + TmpInst.setOpcode(Hexagon::V6_vsubw_dv); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(0)); + TmpInst.addOperand(Inst.getOperand(0)); + MappedInst = TmpInst; + return; + } case Hexagon::V6_vL32Ub_pi: case Hexagon::V6_vL32b_cur_pi: case Hexagon::V6_vL32b_nt_cur_pi: @@ -715,13 +726,25 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, case Hexagon::V6_vS32b_qpred_ai: MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); return; + + // V65+ + case Hexagon::V6_vS32b_srls_ai: + MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext); + return; + + case Hexagon::V6_vS32b_srls_pi: + MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); + return; + } } /// printMachineInstruction -- Print out a single Hexagon MI in Darwin syntax to /// the current output stream. void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { - MCInst MCB = HexagonMCInstrInfo::createBundle(); + MCInst MCB; + MCB.setOpcode(Hexagon::BUNDLE); + MCB.addOperand(MCOperand::createImm(0)); const MCInstrInfo &MCII = *Subtarget->getInstrInfo(); if (MI->isBundle()) { diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.h b/llvm/lib/Target/Hexagon/HexagonDepArch.h index 92573d33132..dc75f8f6340 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepArch.h +++ b/llvm/lib/Target/Hexagon/HexagonDepArch.h @@ -1,4 +1,4 @@ -//===--- HexagonDepArch.h -------------------------------------------------===// +//===- HexagonDepArch.h ---------------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,12 +6,16 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + + #ifndef HEXAGON_DEP_ARCH_H #define HEXAGON_DEP_ARCH_H namespace llvm { namespace Hexagon { -enum class ArchEnum { V4, V5, V55, V60, V62 }; +enum class ArchEnum { V4,V5,V55,V60,V62,V65 }; } // namespace Hexagon -} // namespace llvm +} // namespace llvm; #endif // HEXAGON_DEP_ARCH_H diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.td b/llvm/lib/Target/Hexagon/HexagonDepArch.td index 98403956e6a..87dcd966f2e 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepArch.td +++ b/llvm/lib/Target/Hexagon/HexagonDepArch.td @@ -1,4 +1,4 @@ -//===--- HexagonDepArch.td ------------------------------------------------===// +//===- HexagonDepArch.td --------------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,7 +6,12 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + +def ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V65 architecture">; +def HasV65T : Predicate<"HST->hasV65TOps()">, AssemblerPredicate<"ArchV65">; def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architecture">; def HasV62T : Predicate<"HST->hasV62TOps()">, AssemblerPredicate<"ArchV62">; def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architecture">; diff --git a/llvm/lib/Target/Hexagon/HexagonDepDecoders.h b/llvm/lib/Target/Hexagon/HexagonDepDecoders.h new file mode 100644 index 00000000000..cc28c8fb0e6 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonDepDecoders.h @@ -0,0 +1,78 @@ +//===- HexagonDepDecoders.h -----------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + + + +static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<4>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<14>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s10_6ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<16>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<8>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<7>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<12>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<3>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<13>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<6>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<9>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<5>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<6>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<10>(MI, tmp, Decoder); + return MCDisassembler::Success; +} diff --git a/llvm/lib/Target/Hexagon/HexagonDepIICHVX.td b/llvm/lib/Target/Hexagon/HexagonDepIICHVX.td index 1c1788264c6..b27cdae81a2 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepIICHVX.td +++ b/llvm/lib/Target/Hexagon/HexagonDepIICHVX.td @@ -1,4 +1,4 @@ -//===--- HexagonDepIICHVX.td ----------------------------------------------===// +//===- HexagonDepIICHVX.td ------------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,11 +6,15 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + def tc_0317c6ca : InstrItinClass; def tc_1b93bdc6 : InstrItinClass; def tc_2171ebae : InstrItinClass; def tc_28978789 : InstrItinClass; +def tc_29841470 : InstrItinClass; def tc_316c637c : InstrItinClass; def tc_354299ad : InstrItinClass; def tc_35e92f8e : InstrItinClass; @@ -20,39 +24,49 @@ def tc_41f4b64e : InstrItinClass; def tc_41f99e1c : InstrItinClass; def tc_45453b98 : InstrItinClass; def tc_4e2a5159 : InstrItinClass; +def tc_4f190ba3 : InstrItinClass; def tc_4fd8566e : InstrItinClass; def tc_51cd3aab : InstrItinClass; def tc_5a9fc4ec : InstrItinClass; +def tc_5c03dc63 : InstrItinClass; def tc_5c120602 : InstrItinClass; def tc_5cbf490b : InstrItinClass; +def tc_63e3d94c : InstrItinClass; def tc_644584f8 : InstrItinClass; +def tc_66bb62ea : InstrItinClass; def tc_69b6dd20 : InstrItinClass; def tc_6b78cf13 : InstrItinClass; def tc_6fd9ad30 : InstrItinClass; def tc_71337255 : InstrItinClass; def tc_72ad7b54 : InstrItinClass; +def tc_7474003e : InstrItinClass; def tc_77a4c701 : InstrItinClass; def tc_7c3f55c4 : InstrItinClass; def tc_7e9f581b : InstrItinClass; def tc_7fa82b08 : InstrItinClass; def tc_7fa8b40f : InstrItinClass; def tc_85d237e3 : InstrItinClass; +def tc_8a6eb39a : InstrItinClass; def tc_8b6a873f : InstrItinClass; def tc_908a4c8c : InstrItinClass; def tc_9311da3f : InstrItinClass; +def tc_94f43c04 : InstrItinClass; def tc_9777e6bf : InstrItinClass; def tc_97c165b9 : InstrItinClass; +def tc_98733e9d : InstrItinClass; def tc_99093773 : InstrItinClass; def tc_9b9642a1 : InstrItinClass; def tc_9c267309 : InstrItinClass; def tc_a3127e12 : InstrItinClass; def tc_a4c9df3b : InstrItinClass; +def tc_a807365d : InstrItinClass; def tc_aedb9f9e : InstrItinClass; def tc_b06ab583 : InstrItinClass; def tc_b712833a : InstrItinClass; def tc_b77635b4 : InstrItinClass; def tc_bbaf280e : InstrItinClass; def tc_bf142ae2 : InstrItinClass; +def tc_bfe309d5 : InstrItinClass; def tc_c00bf9c9 : InstrItinClass; def tc_c4b515c5 : InstrItinClass; def tc_cbf6d1dc : InstrItinClass; @@ -65,14 +79,18 @@ def tc_d7bea0ec : InstrItinClass; def tc_d98f4d63 : InstrItinClass; def tc_da979fb3 : InstrItinClass; def tc_db5b9e2f : InstrItinClass; +def tc_df54ad52 : InstrItinClass; def tc_e172d86a : InstrItinClass; def tc_e231aa4f : InstrItinClass; def tc_e3748cdf : InstrItinClass; def tc_e5053c8f : InstrItinClass; def tc_e6299d16 : InstrItinClass; def tc_eb669007 : InstrItinClass; +def tc_ec58f88a : InstrItinClass; def tc_eda67dcd : InstrItinClass; +def tc_ee927c0e : InstrItinClass; def tc_f3fc3f83 : InstrItinClass; +def tc_fa99dc24 : InstrItinClass; class DepHVXItinV55 { list<InstrItinData> DepHVXItinV55_list = [ @@ -97,6 +115,11 @@ class DepHVXItinV55 { InstrStage<1, [CVI_ALL]>], [3, 2], [HVX_FWD, Hex_FWD]>, + InstrItinData <tc_29841470, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], @@ -146,6 +169,12 @@ class DepHVXItinV55 { InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2], [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [SLOT1], 0>, @@ -163,6 +192,11 @@ class DepHVXItinV55 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2], @@ -174,11 +208,23 @@ class DepHVXItinV55 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7], [HVX_FWD, HVX_FWD]>, + InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_69b6dd20, /*SLOT23,VX*/ [InstrStage<1, [SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2], @@ -206,6 +252,11 @@ class DepHVXItinV55 { InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], [HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/ [InstrStage<1, [SLOT0, SLOT1], 0>, InstrStage<1, [CVI_LD]>], [9, 1, 2], @@ -239,6 +290,11 @@ class DepHVXItinV55 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7], [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9], + [HVX_FWD]>, + InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], @@ -254,6 +310,12 @@ class DepHVXItinV55 { InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2], [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_9777e6bf, /*SLOT0,VA*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1], @@ -264,6 +326,12 @@ class DepHVXItinV55 { InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_ST], 0>, @@ -291,6 +359,12 @@ class DepHVXItinV55 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7], [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_ST], 0>, @@ -323,6 +397,12 @@ class DepHVXItinV55 { InstrStage<1, [CVI_XLANE]>], [9, 5, 2], [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2], @@ -386,6 +466,12 @@ class DepHVXItinV55 { InstrStage<1, [CVI_ST]>], [3, 1, 2, 5], [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/ [InstrStage<1, [SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5], @@ -418,15 +504,32 @@ class DepHVXItinV55 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/ [InstrStage<1, [SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01]>], [9, 5, 5], [HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_XLANE]>], [9, 5, 5], - [HVX_FWD, HVX_FWD, HVX_FWD]> + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]> ]; } @@ -453,6 +556,11 @@ class DepHVXItinV60 { InstrStage<1, [CVI_ALL]>], [3, 2], [HVX_FWD, Hex_FWD]>, + InstrItinData <tc_29841470, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], @@ -502,6 +610,12 @@ class DepHVXItinV60 { InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2], [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [SLOT1], 0>, @@ -519,6 +633,11 @@ class DepHVXItinV60 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2], @@ -530,11 +649,23 @@ class DepHVXItinV60 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7], [HVX_FWD, HVX_FWD]>, + InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_69b6dd20, /*SLOT23,VX*/ [InstrStage<1, [SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2], @@ -562,6 +693,11 @@ class DepHVXItinV60 { InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], [HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/ [InstrStage<1, [SLOT0, SLOT1], 0>, InstrStage<1, [CVI_LD]>], [9, 1, 2], @@ -595,6 +731,11 @@ class DepHVXItinV60 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7], [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9], + [HVX_FWD]>, + InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], @@ -610,6 +751,12 @@ class DepHVXItinV60 { InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2], [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_9777e6bf, /*SLOT0,VA*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1], @@ -620,6 +767,12 @@ class DepHVXItinV60 { InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_ST], 0>, @@ -647,6 +800,12 @@ class DepHVXItinV60 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7], [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_ST], 0>, @@ -679,6 +838,12 @@ class DepHVXItinV60 { InstrStage<1, [CVI_XLANE]>], [9, 5, 2], [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2], @@ -742,6 +907,12 @@ class DepHVXItinV60 { InstrStage<1, [CVI_ST]>], [3, 1, 2, 5], [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/ [InstrStage<1, [SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5], @@ -774,15 +945,32 @@ class DepHVXItinV60 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/ [InstrStage<1, [SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01]>], [9, 5, 5], [HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_XLANE]>], [9, 5, 5], - [HVX_FWD, HVX_FWD, HVX_FWD]> + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]> ]; } @@ -809,6 +997,11 @@ class DepHVXItinV62 { InstrStage<1, [CVI_ALL]>], [3, 2], [HVX_FWD, Hex_FWD]>, + InstrItinData <tc_29841470, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], @@ -858,6 +1051,12 @@ class DepHVXItinV62 { InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2], [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [SLOT1], 0>, @@ -875,6 +1074,11 @@ class DepHVXItinV62 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2], @@ -886,11 +1090,23 @@ class DepHVXItinV62 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7], [HVX_FWD, HVX_FWD]>, + InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_69b6dd20, /*SLOT23,VX*/ [InstrStage<1, [SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2], @@ -918,6 +1134,11 @@ class DepHVXItinV62 { InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], [HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/ [InstrStage<1, [SLOT0, SLOT1], 0>, InstrStage<1, [CVI_LD]>], [9, 1, 2], @@ -951,6 +1172,11 @@ class DepHVXItinV62 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7], [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9], + [HVX_FWD]>, + InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], @@ -966,6 +1192,12 @@ class DepHVXItinV62 { InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2], [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_9777e6bf, /*SLOT0,VA*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1], @@ -976,6 +1208,12 @@ class DepHVXItinV62 { InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_ST], 0>, @@ -1003,6 +1241,12 @@ class DepHVXItinV62 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7], [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/ [InstrStage<1, [SLOT0], 0>, InstrStage<1, [CVI_ST], 0>, @@ -1035,6 +1279,12 @@ class DepHVXItinV62 { InstrStage<1, [CVI_XLANE]>], [9, 5, 2], [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2], @@ -1098,6 +1348,12 @@ class DepHVXItinV62 { InstrStage<1, [CVI_ST]>], [3, 1, 2, 5], [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/ [InstrStage<1, [SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5], @@ -1130,14 +1386,472 @@ class DepHVXItinV62 { InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/ [InstrStage<1, [SLOT2, SLOT3], 0>, InstrStage<1, [CVI_MPY01]>], [9, 5, 5], [HVX_FWD, HVX_FWD, HVX_FWD]>, + InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, InstrStage<1, [CVI_XLANE]>], [9, 5, 5], - [HVX_FWD, HVX_FWD, HVX_FWD]> + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]> + ]; +} + +class DepHVXItinV65 { + list<InstrItinData> DepHVXItinV65_list = [ + InstrItinData <tc_0317c6ca, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 2, 1, 2, 7], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_1b93bdc6, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [1, 2, 5], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_2171ebae, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 2, 7, 7], + [HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_28978789, /*SLOT0123,4SLOT*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL]>], [3, 2], + [HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_29841470, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_316c637c, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_354299ad, /*SLOT0,NOSLOT1,STORE,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [1, 2, 5], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_35e92f8e, /*SLOT0,NOSLOT1,LOAD,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_38208312, /*SLOT01,LOAD*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4105d6b5, /*SLOT0123,VP*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 2], + [HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_41f4b64e, /*SLOT0123,VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_SHIFT]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_41f99e1c, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_45453b98, /*SLOT0123,VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_SHIFT]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_4e2a5159, /*SLOT0123,VP_VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_4f190ba3, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 3, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_51cd3aab, /*SLOT01,LOAD*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD]>], [9, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5a9fc4ec, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_5c03dc63, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5c120602, /*SLOT0123,VP_VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_5cbf490b, /*SLOT01,LOAD,VA*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_644584f8, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7], + [HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_69b6dd20, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_6b78cf13, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 2], + [HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_6fd9ad30, /*SLOT0,NOSLOT1,STORE,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [3, 2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_71337255, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7], + [HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_72ad7b54, /*SLOT0123,VP_VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_7474003e, /*SLOT2,VX_DV*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD]>], [9, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7c3f55c4, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_7e9f581b, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 2, 2], + [HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7fa82b08, /*SLOT0,NOSLOT1,STORE,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_7fa8b40f, /*SLOT0123,VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_SHIFT]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_85d237e3, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_8a6eb39a, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9], + [HVX_FWD]>, + + InstrItinData <tc_8b6a873f, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_908a4c8c, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_9311da3f, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_94f43c04, /*SLOT0,STORE,VA_DV*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_9777e6bf, /*SLOT0,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1], + [Hex_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_97c165b9, /*SLOT0123,VA_DV*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_99093773, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 7, 1, 2, 7], + [Hex_FWD, HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_9b9642a1, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_9c267309, /*SLOT01,LOAD*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD]>], [9, 3, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a3127e12, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_a4c9df3b, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_a807365d, /*SLOT23,VS_VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_aedb9f9e, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_b06ab583, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7], + [HVX_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_b712833a, /*SLOT01,LOAD,VA*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b77635b4, /*SLOT0123,4SLOT*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_bbaf280e, /*SLOT0123,VA*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_bf142ae2, /*SLOT0123,VP*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_bfe309d5, /*SLOT1,LOAD,VA_DV*/ + [InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_c00bf9c9, /*SLOT0123,VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_c4b515c5, /*SLOT0123,VP*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_cbf6d1dc, /*SLOT0123,VP_VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_cedf314b, /*SLOT0123,4SLOT*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL]>], [3], + [HVX_FWD]>, + + InstrItinData <tc_d2cb81ea, /*SLOT0123,VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_SHIFT]>], [9, 5], + [HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_d5090f3e, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_d642eff3, /*SLOT0,NOSLOT1,STORE,VP*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_d725e5b0, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_d7bea0ec, /*SLOT0123,VP_VS*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [9, 5], + [HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_d98f4d63, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_da979fb3, /*SLOT01,LOAD,VA*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_db5b9e2f, /*SLOT0,STORE*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_df54ad52, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_e172d86a, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_e231aa4f, /*SLOT23,VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_e3748cdf, /*SLOT0,STORE,VA*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData <tc_e5053c8f, /*SLOT0123,4SLOT*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ALL]>], [], + []>, + + InstrItinData <tc_e6299d16, /*SLOT0123,VP*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 5], + [HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_eb669007, /*SLOT01,LOAD,VA*/ + [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ec58f88a, /*SLOT0,STORE,VA_DV*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_eda67dcd, /*SLOT23,VX_DV*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_ee927c0e, /*SLOT23,VS_VX*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData <tc_f3fc3f83, /*SLOT0123,VP*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData <tc_fa99dc24, /*SLOT2,VX_DV*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]> ]; } diff --git a/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td b/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td index 261778bda72..083ec7753e0 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td +++ b/llvm/lib/Target/Hexagon/HexagonDepIICScalar.td @@ -1,4 +1,4 @@ -//===--- HexagonDepIICScalar.td -------------------------------------------===// +//===- HexagonDepIICScalar.td ---------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,2499 +6,4185 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + -def tc_049dfb74 : InstrItinClass; -def tc_0767081f : InstrItinClass; -def tc_07ac815d : InstrItinClass; -def tc_090485bb : InstrItinClass; -def tc_09c86199 : InstrItinClass; -def tc_09faec3b : InstrItinClass; -def tc_0cb867f2 : InstrItinClass; -def tc_1000eb10 : InstrItinClass; -def tc_128719e8 : InstrItinClass; -def tc_136c4786 : InstrItinClass; -def tc_14da557c : InstrItinClass; -def tc_1b6011fb : InstrItinClass; -def tc_1b834fe7 : InstrItinClass; -def tc_1e062b18 : InstrItinClass; -def tc_1e69aa99 : InstrItinClass; -def tc_1f9668cc : InstrItinClass; -def tc_1fe8323c : InstrItinClass; -def tc_20a8e109 : InstrItinClass; -def tc_210b2456 : InstrItinClass; -def tc_251c87b2 : InstrItinClass; -def tc_261d9b78 : InstrItinClass; -def tc_28d296df : InstrItinClass; -def tc_29c14515 : InstrItinClass; -def tc_2aaab1e0 : InstrItinClass; -def tc_2c8fe5ae : InstrItinClass; -def tc_2d1e6f5c : InstrItinClass; -def tc_2e55aa16 : InstrItinClass; -def tc_30665cb0 : InstrItinClass; -def tc_336e698c : InstrItinClass; -def tc_34e882a4 : InstrItinClass; -def tc_35fb9d13 : InstrItinClass; -def tc_37326008 : InstrItinClass; -def tc_3993c58b : InstrItinClass; -def tc_3b4892c6 : InstrItinClass; -def tc_3bea1824 : InstrItinClass; -def tc_3c10f809 : InstrItinClass; -def tc_3d905451 : InstrItinClass; -def tc_3e61d314 : InstrItinClass; -def tc_3eab77bd : InstrItinClass; -def tc_43068634 : InstrItinClass; -def tc_45631a8d : InstrItinClass; -def tc_47ab9233 : InstrItinClass; -def tc_47f0b7ad : InstrItinClass; -def tc_485bb57c : InstrItinClass; -def tc_4997da4a : InstrItinClass; -def tc_511f28f6 : InstrItinClass; -def tc_537e2013 : InstrItinClass; -def tc_53ee6546 : InstrItinClass; -def tc_548f402d : InstrItinClass; -def tc_5625c6c1 : InstrItinClass; -def tc_580a779c : InstrItinClass; -def tc_583510c7 : InstrItinClass; -def tc_5d806107 : InstrItinClass; -def tc_5fa2857c : InstrItinClass; -def tc_5fe9fcd0 : InstrItinClass; -def tc_6264c5e0 : InstrItinClass; -def tc_639d93ee : InstrItinClass; -def tc_63cd9d2d : InstrItinClass; -def tc_65dc7cc4 : InstrItinClass; -def tc_69bb508b : InstrItinClass; -def tc_6c52d277 : InstrItinClass; -def tc_6c576d46 : InstrItinClass; -def tc_70cabf66 : InstrItinClass; -def tc_7639d4b0 : InstrItinClass; -def tc_7675c0e9 : InstrItinClass; -def tc_76c4c5ef : InstrItinClass; -def tc_77781686 : InstrItinClass; -def tc_78b3c689 : InstrItinClass; -def tc_7986ba30 : InstrItinClass; -def tc_7bc567a7 : InstrItinClass; -def tc_7c2dcd4d : InstrItinClass; -def tc_7ca2ea10 : InstrItinClass; -def tc_7d01cbdc : InstrItinClass; -def tc_7d9a56cd : InstrItinClass; -def tc_81a23d44 : InstrItinClass; -def tc_821c4233 : InstrItinClass; -def tc_82f0f122 : InstrItinClass; -def tc_84630363 : InstrItinClass; -def tc_86442910 : InstrItinClass; -def tc_87601822 : InstrItinClass; -def tc_88fa2da6 : InstrItinClass; -def tc_8c8041e6 : InstrItinClass; -def tc_8cb685d9 : InstrItinClass; -def tc_8def9c57 : InstrItinClass; -def tc_8f0a6bad : InstrItinClass; -def tc_8fab9ac3 : InstrItinClass; -def tc_92d1833c : InstrItinClass; -def tc_94e6ffd9 : InstrItinClass; -def tc_95c54f8b : InstrItinClass; -def tc_9a13af9d : InstrItinClass; -def tc_9b73d261 : InstrItinClass; -def tc_9c18c9a5 : InstrItinClass; -def tc_9c68db63 : InstrItinClass; -def tc_9ce7a5ab : InstrItinClass; -def tc_9da3628f : InstrItinClass; -def tc_9dafb7d3 : InstrItinClass; -def tc_9df8b0dc : InstrItinClass; -def tc_9e86015f : InstrItinClass; -def tc_9f518242 : InstrItinClass; -def tc_a12a5971 : InstrItinClass; -def tc_a1fb80e1 : InstrItinClass; -def tc_a333d2a9 : InstrItinClass; -def tc_a4567c39 : InstrItinClass; -def tc_a87879e8 : InstrItinClass; -def tc_a9c993d9 : InstrItinClass; -def tc_aad55963 : InstrItinClass; -def tc_ab1b5e74 : InstrItinClass; -def tc_ae0722f7 : InstrItinClass; -def tc_ae2c2dc2 : InstrItinClass; -def tc_ae762521 : InstrItinClass; -def tc_b08b653e : InstrItinClass; -def tc_b08be45e : InstrItinClass; -def tc_b0f50e3c : InstrItinClass; -def tc_b189ad4c : InstrItinClass; -def tc_b324366f : InstrItinClass; -def tc_b5bfaa60 : InstrItinClass; -def tc_b5f5a094 : InstrItinClass; -def tc_b86c7e8b : InstrItinClass; -def tc_baccf077 : InstrItinClass; -def tc_bc5561d8 : InstrItinClass; -def tc_bcf0e36e : InstrItinClass; -def tc_bd16579e : InstrItinClass; -def tc_be995eaf : InstrItinClass; -def tc_bf6fa601 : InstrItinClass; -def tc_c0cd91a8 : InstrItinClass; -def tc_c14739d5 : InstrItinClass; -def tc_c1dbc916 : InstrItinClass; -def tc_c58f771a : InstrItinClass; -def tc_c85212ca : InstrItinClass; -def tc_c8f9a6f6 : InstrItinClass; -def tc_ca280e8b : InstrItinClass; -def tc_cbe45117 : InstrItinClass; -def tc_cd321066 : InstrItinClass; -def tc_d108a090 : InstrItinClass; -def tc_d1b5a4b6 : InstrItinClass; -def tc_d2609065 : InstrItinClass; -def tc_d267fa19 : InstrItinClass; -def tc_d2a33af5 : InstrItinClass; -def tc_d63b71d1 : InstrItinClass; -def tc_d6a805a8 : InstrItinClass; -def tc_d95f4e98 : InstrItinClass; -def tc_da79106e : InstrItinClass; -def tc_dbe218dd : InstrItinClass; -def tc_dcfee7ae : InstrItinClass; -def tc_e17ce9ad : InstrItinClass; -def tc_e2480a7f : InstrItinClass; -def tc_e2c08bb4 : InstrItinClass; -def tc_e2c31426 : InstrItinClass; -def tc_e578178f : InstrItinClass; -def tc_e836c161 : InstrItinClass; -def tc_e8c7a357 : InstrItinClass; -def tc_eb07ef6f : InstrItinClass; -def tc_ecfaae86 : InstrItinClass; -def tc_ef0ebaaa : InstrItinClass; -def tc_ef2676fd : InstrItinClass; -def tc_f027ebe9 : InstrItinClass; -def tc_f055fbb6 : InstrItinClass; -def tc_f1240c08 : InstrItinClass; -def tc_f16d5b17 : InstrItinClass; -def tc_f1aa2cdb : InstrItinClass; -def tc_f26aa619 : InstrItinClass; -def tc_f4608adc : InstrItinClass; -def tc_faab1248 : InstrItinClass; -def tc_fcee8723 : InstrItinClass; -def tc_feb4974b : InstrItinClass; +def tc_0077f68c : InstrItinClass; +def tc_00afc57e : InstrItinClass; +def tc_00e7c26e : InstrItinClass; +def tc_03220ffa : InstrItinClass; +def tc_038a1342 : InstrItinClass; +def tc_04c9decc : InstrItinClass; +def tc_05b6c987 : InstrItinClass; +def tc_0a2b8c7c : InstrItinClass; +def tc_0cd51c76 : InstrItinClass; +def tc_0dc560de : InstrItinClass; +def tc_0fc1ae07 : InstrItinClass; +def tc_10b97e27 : InstrItinClass; +def tc_128f96e3 : InstrItinClass; +def tc_1372bca1 : InstrItinClass; +def tc_1432937d : InstrItinClass; +def tc_14cd4cfa : InstrItinClass; +def tc_15411484 : InstrItinClass; +def tc_16d0d8d5 : InstrItinClass; +def tc_181af5d0 : InstrItinClass; +def tc_1853ea6d : InstrItinClass; +def tc_1b82a277 : InstrItinClass; +def tc_1b9c9ee5 : InstrItinClass; +def tc_1c0005f9 : InstrItinClass; +def tc_1d5a38a8 : InstrItinClass; +def tc_1e856f58 : InstrItinClass; +def tc_20280784 : InstrItinClass; +def tc_234a11a5 : InstrItinClass; +def tc_238d91d2 : InstrItinClass; +def tc_29175780 : InstrItinClass; +def tc_29641329 : InstrItinClass; +def tc_2a160009 : InstrItinClass; +def tc_2b2f4060 : InstrItinClass; +def tc_2b6f77c6 : InstrItinClass; +def tc_2e00db30 : InstrItinClass; +def tc_2f185f5c : InstrItinClass; +def tc_2fc0c436 : InstrItinClass; +def tc_351fed2d : InstrItinClass; +def tc_3669266a : InstrItinClass; +def tc_367f7f3d : InstrItinClass; +def tc_36c68ad1 : InstrItinClass; +def tc_395dc00f : InstrItinClass; +def tc_3bc2c5d3 : InstrItinClass; +def tc_3cb8ea06 : InstrItinClass; +def tc_3d04548d : InstrItinClass; +def tc_3da80ba5 : InstrItinClass; +def tc_3e07fb90 : InstrItinClass; +def tc_41d5298e : InstrItinClass; +def tc_4403ca65 : InstrItinClass; +def tc_44126683 : InstrItinClass; +def tc_452f85af : InstrItinClass; +def tc_481e5e5c : InstrItinClass; +def tc_49eb22c8 : InstrItinClass; +def tc_4ca572d4 : InstrItinClass; +def tc_4d9914c9 : InstrItinClass; +def tc_4d99bca9 : InstrItinClass; +def tc_4f7cd700 : InstrItinClass; +def tc_513bef45 : InstrItinClass; +def tc_51b866be : InstrItinClass; +def tc_523fcf30 : InstrItinClass; +def tc_5274e61a : InstrItinClass; +def tc_52d7bbea : InstrItinClass; +def tc_53173427 : InstrItinClass; +def tc_53bc8a6a : InstrItinClass; +def tc_53bdb2f6 : InstrItinClass; +def tc_540fdfbc : InstrItinClass; +def tc_55050d58 : InstrItinClass; +def tc_56d25411 : InstrItinClass; +def tc_57288781 : InstrItinClass; +def tc_594ab548 : InstrItinClass; +def tc_5acef64a : InstrItinClass; +def tc_5ba5997d : InstrItinClass; +def tc_5eb851fc : InstrItinClass; +def tc_5f6847a1 : InstrItinClass; +def tc_60571023 : InstrItinClass; +def tc_609d2efe : InstrItinClass; +def tc_60d76817 : InstrItinClass; +def tc_60f5738d : InstrItinClass; +def tc_63fe3df7 : InstrItinClass; +def tc_66888ded : InstrItinClass; +def tc_6792d5ff : InstrItinClass; +def tc_681a2300 : InstrItinClass; +def tc_68cb12ce : InstrItinClass; +def tc_6aa5711a : InstrItinClass; +def tc_6ac37025 : InstrItinClass; +def tc_6ebb4a12 : InstrItinClass; +def tc_6efc556e : InstrItinClass; +def tc_73043bf4 : InstrItinClass; +def tc_746baa8e : InstrItinClass; +def tc_74e47fd9 : InstrItinClass; +def tc_7934b9df : InstrItinClass; +def tc_7a830544 : InstrItinClass; +def tc_7f881c76 : InstrItinClass; +def tc_84df2cd3 : InstrItinClass; +def tc_85523bcb : InstrItinClass; +def tc_855b0b61 : InstrItinClass; +def tc_87735c3b : InstrItinClass; +def tc_88fa1a78 : InstrItinClass; +def tc_897d1a9d : InstrItinClass; +def tc_8b15472a : InstrItinClass; +def tc_8bb285ec : InstrItinClass; +def tc_8fd5f294 : InstrItinClass; +def tc_8fe6b782 : InstrItinClass; +def tc_90f3e30c : InstrItinClass; +def tc_976ddc4f : InstrItinClass; +def tc_97743097 : InstrItinClass; +def tc_999d32db : InstrItinClass; +def tc_99be14ca : InstrItinClass; +def tc_9c00ce8d : InstrItinClass; +def tc_9c98e8af : InstrItinClass; +def tc_9d5941c7 : InstrItinClass; +def tc_9ef61e5c : InstrItinClass; +def tc_9faf76ae : InstrItinClass; +def tc_9fdb5406 : InstrItinClass; +def tc_a21dc435 : InstrItinClass; +def tc_a27582fa : InstrItinClass; +def tc_a46f0df5 : InstrItinClass; +def tc_a788683e : InstrItinClass; +def tc_a8acdac0 : InstrItinClass; +def tc_a904d137 : InstrItinClass; +def tc_adb14c66 : InstrItinClass; +def tc_b13761ae : InstrItinClass; +def tc_b166348b : InstrItinClass; +def tc_b44c6e2a : InstrItinClass; +def tc_b5a33b22 : InstrItinClass; +def tc_b77c481f : InstrItinClass; +def tc_b7dd427e : InstrItinClass; +def tc_b9488031 : InstrItinClass; +def tc_b9c0b731 : InstrItinClass; +def tc_b9c4623f : InstrItinClass; +def tc_bad2bcaf : InstrItinClass; +def tc_bcc96cee : InstrItinClass; +def tc_bd90564c : InstrItinClass; +def tc_bde7aaf4 : InstrItinClass; +def tc_be706f30 : InstrItinClass; +def tc_c2f7d806 : InstrItinClass; +def tc_c5e2426d : InstrItinClass; +def tc_c6aa82f7 : InstrItinClass; +def tc_c6ce9b3f : InstrItinClass; +def tc_c6ebf8dd : InstrItinClass; +def tc_c74f796f : InstrItinClass; +def tc_c82dc1ff : InstrItinClass; +def tc_caaebcba : InstrItinClass; +def tc_cd7374a0 : InstrItinClass; +def tc_cde8b071 : InstrItinClass; +def tc_cf47a43f : InstrItinClass; +def tc_cf59f215 : InstrItinClass; +def tc_d088982c : InstrItinClass; +def tc_d1090e34 : InstrItinClass; +def tc_d24b2d85 : InstrItinClass; +def tc_d580173f : InstrItinClass; +def tc_d6bf0472 : InstrItinClass; +def tc_d9709180 : InstrItinClass; +def tc_d9f95eef : InstrItinClass; +def tc_daa058fa : InstrItinClass; +def tc_dbdffe3d : InstrItinClass; +def tc_e0739b8c : InstrItinClass; +def tc_e1e0a2dc : InstrItinClass; +def tc_e1e99bfa : InstrItinClass; +def tc_e216a5db : InstrItinClass; +def tc_e421e012 : InstrItinClass; +def tc_e6b38e01 : InstrItinClass; +def tc_e7624c08 : InstrItinClass; +def tc_e7d02c66 : InstrItinClass; +def tc_e913dc32 : InstrItinClass; +def tc_e9c822f7 : InstrItinClass; +def tc_e9fae2d6 : InstrItinClass; +def tc_ef20db1c : InstrItinClass; +def tc_ef52ed71 : InstrItinClass; +def tc_ef84f62f : InstrItinClass; +def tc_f2704b9a : InstrItinClass; +def tc_f3eaa14b : InstrItinClass; +def tc_f47d212f : InstrItinClass; +def tc_f49e76f4 : InstrItinClass; +def tc_f4f43fb5 : InstrItinClass; +def tc_f7dd9c9f : InstrItinClass; +def tc_f86c328a : InstrItinClass; +def tc_f8eeed7a : InstrItinClass; +def tc_fcab4871 : InstrItinClass; +def tc_ff9ee76e : InstrItinClass; class DepScalarItinV4 { list<InstrItinData> DepScalarItinV4_list = [ - InstrItinData <tc_049dfb74, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_0767081f, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_07ac815d, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_090485bb, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_09c86199, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_09faec3b, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_0cb867f2, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_1000eb10, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_128719e8, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_136c4786, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_14da557c, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_1b6011fb, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_1b834fe7, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_1e062b18, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_1e69aa99, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_1f9668cc, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_1fe8323c, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_20a8e109, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_210b2456, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_251c87b2, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_261d9b78, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_28d296df, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_29c14515, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_2aaab1e0, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_2c8fe5ae, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_2d1e6f5c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_2e55aa16, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_30665cb0, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_336e698c, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_34e882a4, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_35fb9d13, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_37326008, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_3993c58b, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_3b4892c6, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_3bea1824, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_3c10f809, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_3d905451, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_3e61d314, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_3eab77bd, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_43068634, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_45631a8d, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_47ab9233, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_47f0b7ad, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_485bb57c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_4997da4a, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_511f28f6, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_537e2013, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_53ee6546, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_548f402d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_5625c6c1, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_580a779c, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_583510c7, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_5d806107, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_5fa2857c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_5fe9fcd0, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_6264c5e0, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_639d93ee, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_63cd9d2d, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_65dc7cc4, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_69bb508b, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_6c52d277, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_6c576d46, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_70cabf66, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_7639d4b0, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_7675c0e9, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_76c4c5ef, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_77781686, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_78b3c689, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_7986ba30, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_7bc567a7, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_7c2dcd4d, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_7ca2ea10, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_7d01cbdc, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_7d9a56cd, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_81a23d44, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_821c4233, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_82f0f122, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_84630363, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_86442910, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_87601822, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_88fa2da6, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_8c8041e6, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_8cb685d9, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_8def9c57, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_8f0a6bad, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_8fab9ac3, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_92d1833c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_94e6ffd9, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_95c54f8b, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9a13af9d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_9b73d261, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_9c18c9a5, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_9c68db63, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9ce7a5ab, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9da3628f, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9dafb7d3, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_9df8b0dc, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_9e86015f, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9f518242, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_a12a5971, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_a1fb80e1, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_a333d2a9, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_a4567c39, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_a87879e8, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_a9c993d9, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_aad55963, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_ab1b5e74, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_ae0722f7, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_ae2c2dc2, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_ae762521, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_b08b653e, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_b08be45e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_b0f50e3c, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_b189ad4c, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_b324366f, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_b5bfaa60, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_b5f5a094, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_b86c7e8b, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_baccf077, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_bc5561d8, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_bcf0e36e, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_bd16579e, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_be995eaf, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_bf6fa601, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_c0cd91a8, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_c14739d5, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_c1dbc916, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_c58f771a, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_c85212ca, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_c8f9a6f6, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_ca280e8b, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_cbe45117, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_cd321066, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_d108a090, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_d1b5a4b6, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_d2609065, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_d267fa19, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_d2a33af5, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_d63b71d1, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_d6a805a8, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_d95f4e98, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_da79106e, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_dbe218dd, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_dcfee7ae, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_e17ce9ad, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_e2480a7f, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_e2c08bb4, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_e2c31426, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_e578178f, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_e836c161, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_e8c7a357, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_eb07ef6f, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_ecfaae86, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_ef0ebaaa, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_ef2676fd, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_f027ebe9, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_f055fbb6, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_f1240c08, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_f16d5b17, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_f1aa2cdb, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_f26aa619, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_f4608adc, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_faab1248, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_fcee8723, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_feb4974b, [InstrStage<1, [SLOT3]>]> ]; + InstrItinData <tc_0077f68c, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_00afc57e, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_00e7c26e, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_03220ffa, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_038a1342, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_04c9decc, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_05b6c987, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_0a2b8c7c, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_0cd51c76, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_0dc560de, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_0fc1ae07, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_10b97e27, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_128f96e3, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_1372bca1, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_1432937d, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_14cd4cfa, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_15411484, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_16d0d8d5, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_181af5d0, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_1853ea6d, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_1b82a277, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_1b9c9ee5, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_1c0005f9, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_1d5a38a8, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_1e856f58, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_20280784, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_234a11a5, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_238d91d2, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_29175780, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_29641329, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_2a160009, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_2b2f4060, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_2b6f77c6, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_2e00db30, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_2f185f5c, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_2fc0c436, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_351fed2d, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_3669266a, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_367f7f3d, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_36c68ad1, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_395dc00f, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_3bc2c5d3, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_3cb8ea06, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_3d04548d, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_3da80ba5, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_3e07fb90, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_41d5298e, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_4403ca65, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_44126683, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_452f85af, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_481e5e5c, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_49eb22c8, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_4ca572d4, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_4d9914c9, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_4d99bca9, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_4f7cd700, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_513bef45, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_51b866be, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_523fcf30, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_5274e61a, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_52d7bbea, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_53173427, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_53bc8a6a, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_53bdb2f6, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_540fdfbc, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_55050d58, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_56d25411, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_57288781, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_594ab548, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_5acef64a, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_5ba5997d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_5eb851fc, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_5f6847a1, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_60571023, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_609d2efe, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_60d76817, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_60f5738d, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_63fe3df7, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_66888ded, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_6792d5ff, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_681a2300, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_68cb12ce, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_6aa5711a, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_6ac37025, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_6ebb4a12, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_6efc556e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_73043bf4, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_746baa8e, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_74e47fd9, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_7934b9df, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_7a830544, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_7f881c76, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_84df2cd3, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_85523bcb, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_855b0b61, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_87735c3b, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_88fa1a78, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_897d1a9d, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_8b15472a, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_8bb285ec, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_8fd5f294, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_8fe6b782, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_90f3e30c, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_976ddc4f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_97743097, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_999d32db, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_99be14ca, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_9c00ce8d, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_9c98e8af, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_9d5941c7, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_9ef61e5c, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_9faf76ae, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_9fdb5406, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_a21dc435, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_a27582fa, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a46f0df5, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a788683e, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_a8acdac0, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_a904d137, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_adb14c66, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_b13761ae, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_b166348b, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_b44c6e2a, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_b5a33b22, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_b77c481f, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_b7dd427e, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_b9488031, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_b9c0b731, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_b9c4623f, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_bad2bcaf, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_bcc96cee, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_bd90564c, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_bde7aaf4, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_be706f30, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c2f7d806, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c5e2426d, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_c6aa82f7, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_c6ce9b3f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c6ebf8dd, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c74f796f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c82dc1ff, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_caaebcba, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_cd7374a0, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_cde8b071, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_cf47a43f, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_cf59f215, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_d088982c, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_d1090e34, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_d24b2d85, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_d580173f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_d6bf0472, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_d9709180, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_d9f95eef, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_daa058fa, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_dbdffe3d, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_e0739b8c, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_e1e0a2dc, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_e1e99bfa, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_e216a5db, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_e421e012, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_e6b38e01, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_e7624c08, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_e7d02c66, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_e913dc32, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_e9c822f7, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_e9fae2d6, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_ef20db1c, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_ef52ed71, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_ef84f62f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f2704b9a, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f3eaa14b, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f47d212f, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_f49e76f4, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f4f43fb5, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_f7dd9c9f, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_f86c328a, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_f8eeed7a, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_fcab4871, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_ff9ee76e, [InstrStage<1, [SLOT0]>]> ]; } class DepScalarItinV5 { list<InstrItinData> DepScalarItinV5_list = [ - InstrItinData <tc_049dfb74, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_0767081f, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_07ac815d, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_090485bb, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_09c86199, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_09faec3b, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_0cb867f2, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_1000eb10, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_128719e8, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_136c4786, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_14da557c, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_1b6011fb, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_1b834fe7, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_1e062b18, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_1e69aa99, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_1f9668cc, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_1fe8323c, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_20a8e109, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_210b2456, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_251c87b2, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_261d9b78, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_28d296df, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_29c14515, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_2aaab1e0, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_2c8fe5ae, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_2d1e6f5c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_2e55aa16, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_30665cb0, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_336e698c, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_34e882a4, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_35fb9d13, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_37326008, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_3993c58b, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_3b4892c6, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_3bea1824, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_3c10f809, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_3d905451, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_3e61d314, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_3eab77bd, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_43068634, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_45631a8d, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_47ab9233, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_47f0b7ad, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_485bb57c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_4997da4a, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_511f28f6, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_537e2013, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_53ee6546, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_548f402d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_5625c6c1, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_580a779c, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_583510c7, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_5d806107, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_5fa2857c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_5fe9fcd0, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_6264c5e0, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_639d93ee, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_63cd9d2d, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_65dc7cc4, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_69bb508b, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_6c52d277, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_6c576d46, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_70cabf66, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_7639d4b0, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_7675c0e9, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_76c4c5ef, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_77781686, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_78b3c689, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_7986ba30, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_7bc567a7, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_7c2dcd4d, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_7ca2ea10, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_7d01cbdc, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_7d9a56cd, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_81a23d44, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_821c4233, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_82f0f122, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_84630363, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_86442910, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_87601822, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_88fa2da6, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_8c8041e6, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_8cb685d9, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_8def9c57, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_8f0a6bad, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_8fab9ac3, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_92d1833c, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_94e6ffd9, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_95c54f8b, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9a13af9d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_9b73d261, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_9c18c9a5, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_9c68db63, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9ce7a5ab, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9da3628f, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9dafb7d3, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_9df8b0dc, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_9e86015f, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_9f518242, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_a12a5971, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_a1fb80e1, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_a333d2a9, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_a4567c39, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_a87879e8, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_a9c993d9, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_aad55963, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_ab1b5e74, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_ae0722f7, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_ae2c2dc2, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_ae762521, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_b08b653e, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_b08be45e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_b0f50e3c, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_b189ad4c, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_b324366f, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_b5bfaa60, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_b5f5a094, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_b86c7e8b, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_baccf077, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_bc5561d8, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_bcf0e36e, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_bd16579e, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_be995eaf, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_bf6fa601, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_c0cd91a8, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_c14739d5, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_c1dbc916, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_c58f771a, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_c85212ca, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_c8f9a6f6, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_ca280e8b, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_cbe45117, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_cd321066, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_d108a090, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_d1b5a4b6, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_d2609065, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_d267fa19, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_d2a33af5, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_d63b71d1, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_d6a805a8, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_d95f4e98, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_da79106e, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_dbe218dd, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_dcfee7ae, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_e17ce9ad, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_e2480a7f, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_e2c08bb4, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_e2c31426, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_e578178f, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_e836c161, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_e8c7a357, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_eb07ef6f, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_ecfaae86, [InstrStage<1, [SLOT2]>]>, - InstrItinData <tc_ef0ebaaa, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_ef2676fd, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_f027ebe9, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_f055fbb6, [InstrStage<1, [SLOT3]>]>, - InstrItinData <tc_f1240c08, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_f16d5b17, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData <tc_f1aa2cdb, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_f26aa619, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_f4608adc, [InstrStage<1, [SLOT0]>]>, - InstrItinData <tc_faab1248, [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData <tc_fcee8723, [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData <tc_feb4974b, [InstrStage<1, [SLOT3]>]> ]; + InstrItinData <tc_0077f68c, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_00afc57e, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_00e7c26e, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_03220ffa, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_038a1342, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_04c9decc, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_05b6c987, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_0a2b8c7c, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_0cd51c76, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_0dc560de, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_0fc1ae07, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_10b97e27, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_128f96e3, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_1372bca1, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_1432937d, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_14cd4cfa, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_15411484, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_16d0d8d5, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_181af5d0, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_1853ea6d, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_1b82a277, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_1b9c9ee5, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_1c0005f9, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_1d5a38a8, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_1e856f58, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_20280784, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_234a11a5, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_238d91d2, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_29175780, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_29641329, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_2a160009, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_2b2f4060, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_2b6f77c6, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_2e00db30, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_2f185f5c, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_2fc0c436, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_351fed2d, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_3669266a, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_367f7f3d, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_36c68ad1, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_395dc00f, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_3bc2c5d3, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_3cb8ea06, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_3d04548d, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_3da80ba5, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_3e07fb90, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_41d5298e, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_4403ca65, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_44126683, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_452f85af, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_481e5e5c, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_49eb22c8, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_4ca572d4, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_4d9914c9, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_4d99bca9, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_4f7cd700, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_513bef45, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_51b866be, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_523fcf30, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_5274e61a, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_52d7bbea, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_53173427, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_53bc8a6a, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_53bdb2f6, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_540fdfbc, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_55050d58, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_56d25411, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_57288781, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_594ab548, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_5acef64a, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_5ba5997d, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_5eb851fc, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_5f6847a1, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_60571023, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_609d2efe, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_60d76817, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_60f5738d, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_63fe3df7, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_66888ded, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_6792d5ff, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_681a2300, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_68cb12ce, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_6aa5711a, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_6ac37025, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_6ebb4a12, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_6efc556e, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_73043bf4, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_746baa8e, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_74e47fd9, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_7934b9df, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_7a830544, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_7f881c76, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_84df2cd3, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_85523bcb, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_855b0b61, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_87735c3b, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_88fa1a78, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_897d1a9d, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_8b15472a, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_8bb285ec, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_8fd5f294, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_8fe6b782, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_90f3e30c, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_976ddc4f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_97743097, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_999d32db, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_99be14ca, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_9c00ce8d, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_9c98e8af, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_9d5941c7, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_9ef61e5c, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_9faf76ae, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_9fdb5406, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_a21dc435, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_a27582fa, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a46f0df5, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_a788683e, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_a8acdac0, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_a904d137, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_adb14c66, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_b13761ae, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_b166348b, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_b44c6e2a, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_b5a33b22, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_b77c481f, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_b7dd427e, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_b9488031, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_b9c0b731, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_b9c4623f, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_bad2bcaf, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_bcc96cee, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_bd90564c, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_bde7aaf4, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_be706f30, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c2f7d806, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c5e2426d, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_c6aa82f7, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_c6ce9b3f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c6ebf8dd, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c74f796f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_c82dc1ff, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_caaebcba, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_cd7374a0, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_cde8b071, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_cf47a43f, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_cf59f215, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_d088982c, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_d1090e34, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_d24b2d85, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_d580173f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_d6bf0472, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData <tc_d9709180, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_d9f95eef, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_daa058fa, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_dbdffe3d, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_e0739b8c, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_e1e0a2dc, [InstrStage<1, [SLOT2]>]>, + InstrItinData <tc_e1e99bfa, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_e216a5db, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_e421e012, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_e6b38e01, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_e7624c08, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_e7d02c66, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_e913dc32, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_e9c822f7, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_e9fae2d6, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_ef20db1c, [InstrStage<1, [SLOT3]>]>, + InstrItinData <tc_ef52ed71, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_ef84f62f, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f2704b9a, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f3eaa14b, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f47d212f, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_f49e76f4, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_f4f43fb5, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_f7dd9c9f, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_f86c328a, [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData <tc_f8eeed7a, [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData <tc_fcab4871, [InstrStage<1, [SLOT0]>]>, + InstrItinData <tc_ff9ee76e, [InstrStage<1, [SLOT0]>]> ]; } class DepScalarItinV55 { list<InstrItinData> DepScalarItinV55_list = [ - InstrItinData <tc_049dfb74, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], + InstrItinData <tc_0077f68c, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2], [Hex_FWD]>, - InstrItinData <tc_0767081f, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_00afc57e, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_07ac815d, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_00e7c26e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, - InstrItinData <tc_090485bb, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_03220ffa, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_09c86199, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_038a1342, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_09faec3b, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], + InstrItinData <tc_04c9decc, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0cb867f2, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 2, 2], + InstrItinData <tc_05b6c987, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1000eb10, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_0a2b8c7c, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_128719e8, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + InstrItinData <tc_0cd51c76, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_136c4786, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + InstrItinData <tc_0dc560de, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0fc1ae07, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_10b97e27, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_128f96e3, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1372bca1, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14da557c, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1432937d, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1b6011fb, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_14cd4cfa, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_15411484, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_16d0d8d5, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1b834fe7, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_181af5d0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1e062b18, /*tc_1*/ + InstrItinData <tc_1853ea6d, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1b82a277, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_1b9c9ee5, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1e69aa99, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1c0005f9, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1f9668cc, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [3, 1], + InstrItinData <tc_1d5a38a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1e856f58, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_20280784, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1fe8323c, /*tc_2*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_234a11a5, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_20a8e109, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_238d91d2, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_210b2456, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_29175780, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_251c87b2, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_29641329, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_261d9b78, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_2a160009, /*tc_2early*/ + [InstrStage<1, [SLOT0]>], [], + []>, - InstrItinData <tc_28d296df, /*tc_1*/ + InstrItinData <tc_2b2f4060, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_29c14515, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 1], + InstrItinData <tc_2b6f77c6, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2e00db30, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_2f185f5c, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2aaab1e0, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1], + InstrItinData <tc_2fc0c436, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2c8fe5ae, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 2, 3], + InstrItinData <tc_351fed2d, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3669266a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_367f7f3d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_36c68ad1, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [], + []>, + + InstrItinData <tc_395dc00f, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 3, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2d1e6f5c, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_3bc2c5d3, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, - InstrItinData <tc_2e55aa16, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_3cb8ea06, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3d04548d, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_30665cb0, /*tc_st*/ + InstrItinData <tc_3da80ba5, /*tc_ld*/ [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_336e698c, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + InstrItinData <tc_3e07fb90, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_41d5298e, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4403ca65, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44126683, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_34e882a4, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1], + InstrItinData <tc_452f85af, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData <tc_35fb9d13, /*tc_2early*/ - [InstrStage<1, [SLOT0]>], [], + InstrItinData <tc_481e5e5c, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_49eb22c8, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4ca572d4, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [], []>, - InstrItinData <tc_37326008, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_4d9914c9, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4d99bca9, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3993c58b, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 3, 1], + InstrItinData <tc_4f7cd700, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_513bef45, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3b4892c6, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_51b866be, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_523fcf30, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5274e61a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_52d7bbea, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_53173427, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3bea1824, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_53bc8a6a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3c10f809, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_53bdb2f6, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3d905451, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_540fdfbc, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3e61d314, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [1, 3, 2], + InstrItinData <tc_55050d58, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3eab77bd, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_56d25411, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_43068634, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_57288781, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_594ab548, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_45631a8d, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], + InstrItinData <tc_5acef64a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_47ab9233, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_5ba5997d, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_47f0b7ad, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5eb851fc, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_485bb57c, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5f6847a1, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4997da4a, /*tc_3x*/ + InstrItinData <tc_60571023, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_609d2efe, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_60d76817, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [], + []>, + + InstrItinData <tc_60f5738d, /*tc_3x*/ [InstrStage<1, [SLOT3]>], [1], [Hex_FWD]>, - InstrItinData <tc_511f28f6, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_63fe3df7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_66888ded, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_537e2013, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_6792d5ff, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_681a2300, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_68cb12ce, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_53ee6546, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_6aa5711a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6ac37025, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_548f402d, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_6ebb4a12, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5625c6c1, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_6efc556e, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, - InstrItinData <tc_580a779c, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2], + InstrItinData <tc_73043bf4, /*tc_2early*/ + [InstrStage<1, [SLOT3]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_746baa8e, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_74e47fd9, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7934b9df, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7a830544, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_583510c7, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + InstrItinData <tc_7f881c76, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_84df2cd3, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5d806107, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_85523bcb, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5fa2857c, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], + InstrItinData <tc_855b0b61, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5fe9fcd0, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], + InstrItinData <tc_87735c3b, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_88fa1a78, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_897d1a9d, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6264c5e0, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + InstrItinData <tc_8b15472a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_639d93ee, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2], + InstrItinData <tc_8bb285ec, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_63cd9d2d, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_8fd5f294, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_65dc7cc4, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_69bb508b, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_8fe6b782, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6c52d277, /*tc_st*/ + InstrItinData <tc_90f3e30c, /*tc_2early*/ [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6c576d46, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 3], + InstrItinData <tc_976ddc4f, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_97743097, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_999d32db, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_99be14ca, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_70cabf66, /*tc_ld*/ + InstrItinData <tc_9c00ce8d, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9c98e8af, /*tc_ld*/ [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7639d4b0, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], + InstrItinData <tc_9d5941c7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7675c0e9, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], + InstrItinData <tc_9ef61e5c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_76c4c5ef, /*tc_2*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_9faf76ae, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, - InstrItinData <tc_77781686, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + InstrItinData <tc_9fdb5406, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_78b3c689, /*tc_1*/ + InstrItinData <tc_a21dc435, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a27582fa, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_a46f0df5, /*tc_2early*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7986ba30, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_a788683e, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7bc567a7, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + InstrItinData <tc_a8acdac0, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a904d137, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_adb14c66, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7c2dcd4d, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], - [Hex_FWD]>, + InstrItinData <tc_b13761ae, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [], + []>, - InstrItinData <tc_7ca2ea10, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_b166348b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b44c6e2a, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7d01cbdc, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 1, 1], + InstrItinData <tc_b5a33b22, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7d9a56cd, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + InstrItinData <tc_b77c481f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b7dd427e, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b9488031, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b9c0b731, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_81a23d44, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_b9c4623f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_821c4233, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + InstrItinData <tc_bad2bcaf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bcc96cee, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bd90564c, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bde7aaf4, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_82f0f122, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 1], + InstrItinData <tc_be706f30, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_84630363, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_c2f7d806, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_86442910, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [], - []>, + InstrItinData <tc_c5e2426d, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_87601822, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_c6aa82f7, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_88fa2da6, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_c6ce9b3f, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8c8041e6, /*tc_3x*/ + InstrItinData <tc_c6ebf8dd, /*tc_3stall*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8cb685d9, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + InstrItinData <tc_c74f796f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8def9c57, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + InstrItinData <tc_c82dc1ff, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_caaebcba, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8f0a6bad, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_cd7374a0, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cde8b071, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cf47a43f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8fab9ac3, /*tc_st*/ + InstrItinData <tc_cf59f215, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d088982c, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d1090e34, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d24b2d85, /*tc_st*/ [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_92d1833c, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2], + InstrItinData <tc_d580173f, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d6bf0472, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d9709180, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d9f95eef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_daa058fa, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_dbdffe3d, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_94e6ffd9, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_e0739b8c, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_95c54f8b, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [], + InstrItinData <tc_e1e0a2dc, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [], []>, - InstrItinData <tc_9a13af9d, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], - [Hex_FWD]>, - - InstrItinData <tc_9b73d261, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e1e99bfa, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9c18c9a5, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_e216a5db, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9c68db63, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + InstrItinData <tc_e421e012, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ce7a5ab, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 2, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e6b38e01, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9da3628f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + InstrItinData <tc_e7624c08, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_e7d02c66, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9dafb7d3, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e913dc32, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9df8b0dc, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e9c822f7, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, - InstrItinData <tc_9e86015f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 3], + InstrItinData <tc_e9fae2d6, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9f518242, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_ef20db1c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a12a5971, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + InstrItinData <tc_ef52ed71, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a1fb80e1, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_ef84f62f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f2704b9a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a333d2a9, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2], - [Hex_FWD]>, + InstrItinData <tc_f3eaa14b, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a4567c39, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], + InstrItinData <tc_f47d212f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a87879e8, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_f49e76f4, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a9c993d9, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_f4f43fb5, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_aad55963, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + InstrItinData <tc_f7dd9c9f, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f86c328a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f8eeed7a, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fcab4871, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [], []>, - InstrItinData <tc_ab1b5e74, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_ff9ee76e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], + [Hex_FWD, Hex_FWD]> + ]; +} + +class DepScalarItinV60 { + list<InstrItinData> DepScalarItinV60_list = [ + InstrItinData <tc_0077f68c, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_00afc57e, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae0722f7, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1], + InstrItinData <tc_00e7c26e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_03220ffa, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_038a1342, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae2c2dc2, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], + InstrItinData <tc_04c9decc, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae762521, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], + InstrItinData <tc_05b6c987, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0a2b8c7c, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0cd51c76, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b08b653e, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], + InstrItinData <tc_0dc560de, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0fc1ae07, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], [Hex_FWD]>, - InstrItinData <tc_b08be45e, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_10b97e27, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b0f50e3c, /*tc_2*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_128f96e3, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1372bca1, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b189ad4c, /*tc_2early*/ + InstrItinData <tc_1432937d, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_14cd4cfa, /*tc_2early*/ [InstrStage<1, [SLOT2]>], [2], [Hex_FWD]>, - InstrItinData <tc_b324366f, /*tc_2early*/ - [InstrStage<1, [SLOT3]>], [1, 2], + InstrItinData <tc_15411484, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_16d0d8d5, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_181af5d0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b5bfaa60, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_1853ea6d, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1b82a277, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_1b9c9ee5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c0005f9, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b5f5a094, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + InstrItinData <tc_1d5a38a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b86c7e8b, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_1e856f58, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_20280784, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_baccf077, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_234a11a5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bc5561d8, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_238d91d2, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bcf0e36e, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [], - []>, + InstrItinData <tc_29175780, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bd16579e, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_29641329, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_be995eaf, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + InstrItinData <tc_2a160009, /*tc_2early*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_2b2f4060, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bf6fa601, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + InstrItinData <tc_2b6f77c6, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c0cd91a8, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_2e00db30, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [], + []>, - InstrItinData <tc_c14739d5, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + InstrItinData <tc_2f185f5c, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c1dbc916, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + InstrItinData <tc_2fc0c436, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_351fed2d, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c58f771a, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_3669266a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], + [Hex_FWD]>, - InstrItinData <tc_c85212ca, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], + InstrItinData <tc_367f7f3d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_36c68ad1, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [], + []>, + + InstrItinData <tc_395dc00f, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c8f9a6f6, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, - InstrItinData <tc_ca280e8b, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_3cb8ea06, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cbe45117, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2], + InstrItinData <tc_3d04548d, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3da80ba5, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_cd321066, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_3e07fb90, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d108a090, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2], + InstrItinData <tc_41d5298e, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4403ca65, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44126683, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d1b5a4b6, /*tc_1*/ + InstrItinData <tc_452f85af, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_481e5e5c, /*tc_2early*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d2609065, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_49eb22c8, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d267fa19, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [], + InstrItinData <tc_4ca572d4, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], []>, - InstrItinData <tc_d2a33af5, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_4d9914c9, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d63b71d1, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_4d99bca9, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d6a805a8, /*tc_3x*/ + InstrItinData <tc_4f7cd700, /*tc_3stall*/ [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d95f4e98, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2, 2], + InstrItinData <tc_513bef45, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_51b866be, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_523fcf30, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da79106e, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_5274e61a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_52d7bbea, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_53173427, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_53bc8a6a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_dbe218dd, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [3, 2], + InstrItinData <tc_53bdb2f6, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_540fdfbc, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_55050d58, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_56d25411, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_dcfee7ae, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 2], + InstrItinData <tc_57288781, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e17ce9ad, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + InstrItinData <tc_594ab548, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e2480a7f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + InstrItinData <tc_5acef64a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5ba5997d, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5eb851fc, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5f6847a1, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_60571023, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e2c08bb4, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_609d2efe, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e2c31426, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + InstrItinData <tc_60d76817, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], []>, - InstrItinData <tc_e578178f, /*tc_ld*/ + InstrItinData <tc_60f5738d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_63fe3df7, /*tc_ld*/ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e836c161, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_66888ded, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e8c7a357, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_6792d5ff, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_681a2300, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_68cb12ce, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_eb07ef6f, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 2], + InstrItinData <tc_6aa5711a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ecfaae86, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], - [Hex_FWD]>, + InstrItinData <tc_6ac37025, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ef0ebaaa, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_6ebb4a12, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ef2676fd, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [], + InstrItinData <tc_6efc556e, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], []>, - InstrItinData <tc_f027ebe9, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [2], - [Hex_FWD]>, + InstrItinData <tc_73043bf4, /*tc_2early*/ + [InstrStage<1, [SLOT3]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_746baa8e, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_74e47fd9, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f055fbb6, /*tc_3x*/ + InstrItinData <tc_7934b9df, /*tc_3x*/ [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f1240c08, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_7a830544, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f16d5b17, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_7f881c76, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_84df2cd3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_85523bcb, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_855b0b61, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_87735c3b, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_88fa1a78, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f1aa2cdb, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1], + InstrItinData <tc_897d1a9d, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f26aa619, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], + InstrItinData <tc_8b15472a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8bb285ec, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_f4608adc, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [1, 1], + InstrItinData <tc_8fd5f294, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8fe6b782, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_90f3e30c, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_faab1248, /*tc_2*/ + InstrItinData <tc_976ddc4f, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fcee8723, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_97743097, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_999d32db, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_99be14ca, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_feb4974b, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 2], - [Hex_FWD, Hex_FWD]> - ]; -} + InstrItinData <tc_9c00ce8d, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, -class DepScalarItinV60 { - list<InstrItinData> DepScalarItinV60_list = [ - InstrItinData <tc_049dfb74, /*tc_2early*/ + InstrItinData <tc_9c98e8af, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9d5941c7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9ef61e5c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9faf76ae, /*tc_2early*/ [InstrStage<1, [SLOT2]>], [1], [Hex_FWD]>, - InstrItinData <tc_0767081f, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_9fdb5406, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a21dc435, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_07ac815d, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_a27582fa, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_a46f0df5, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_090485bb, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + InstrItinData <tc_a788683e, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a8acdac0, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_09c86199, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], + InstrItinData <tc_a904d137, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_adb14c66, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b13761ae, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_b166348b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_09faec3b, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], + InstrItinData <tc_b44c6e2a, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0cb867f2, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 2, 2], + InstrItinData <tc_b5a33b22, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1000eb10, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_b77c481f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_128719e8, /*tc_ld*/ + InstrItinData <tc_b7dd427e, /*tc_ld*/ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_136c4786, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + InstrItinData <tc_b9488031, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14da557c, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + InstrItinData <tc_b9c0b731, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b9c4623f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bad2bcaf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bcc96cee, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bd90564c, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bde7aaf4, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_be706f30, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c2f7d806, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c5e2426d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c6aa82f7, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c6ce9b3f, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c6ebf8dd, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c74f796f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c82dc1ff, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_caaebcba, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cd7374a0, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cde8b071, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cf47a43f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1b6011fb, /*tc_1*/ + InstrItinData <tc_cf59f215, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d088982c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d1090e34, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d24b2d85, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d580173f, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d6bf0472, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1b834fe7, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_d9709180, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d9f95eef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_daa058fa, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1e062b18, /*tc_1*/ + InstrItinData <tc_dbdffe3d, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1e69aa99, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e0739b8c, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1f9668cc, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [3, 1], + InstrItinData <tc_e1e0a2dc, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_e1e99bfa, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1fe8323c, /*tc_2*/ + InstrItinData <tc_e216a5db, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e421e012, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e6b38e01, /*tc_3x*/ [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_20a8e109, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_e7624c08, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_e7d02c66, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_210b2456, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + InstrItinData <tc_e913dc32, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_251c87b2, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e9c822f7, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, - InstrItinData <tc_261d9b78, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + InstrItinData <tc_e9fae2d6, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef20db1c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef52ed71, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_28d296df, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], + InstrItinData <tc_ef84f62f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_29c14515, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 1], + InstrItinData <tc_f2704b9a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2aaab1e0, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + InstrItinData <tc_f3eaa14b, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f47d212f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2c8fe5ae, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 2, 3], + InstrItinData <tc_f49e76f4, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2d1e6f5c, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + InstrItinData <tc_f4f43fb5, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f7dd9c9f, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f86c328a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2e55aa16, /*tc_4x*/ + InstrItinData <tc_f8eeed7a, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fcab4871, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_ff9ee76e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], + [Hex_FWD, Hex_FWD]> + ]; +} + +class DepScalarItinV60se { + list<InstrItinData> DepScalarItinV60se_list = [ + InstrItinData <tc_0077f68c, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_00afc57e, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_00e7c26e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_03220ffa, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_038a1342, /*tc_4x*/ [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_30665cb0, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1], + InstrItinData <tc_04c9decc, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_05b6c987, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0a2b8c7c, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0cd51c76, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0dc560de, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0fc1ae07, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], [Hex_FWD]>, - InstrItinData <tc_336e698c, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + InstrItinData <tc_10b97e27, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_128f96e3, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1372bca1, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_34e882a4, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1], + InstrItinData <tc_1432937d, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_14cd4cfa, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [2], [Hex_FWD]>, - InstrItinData <tc_35fb9d13, /*tc_2early*/ - [InstrStage<1, [SLOT0]>], [], - []>, + InstrItinData <tc_15411484, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [1], + [Hex_FWD]>, - InstrItinData <tc_37326008, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_16d0d8d5, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_181af5d0, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [3, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1853ea6d, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3993c58b, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 3, 2], + InstrItinData <tc_1b82a277, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_1b9c9ee5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c0005f9, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1d5a38a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1e856f58, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_20280784, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_234a11a5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_238d91d2, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3b4892c6, /*tc_3x*/ + InstrItinData <tc_29175780, /*tc_3x*/ [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3bea1824, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + InstrItinData <tc_29641329, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3c10f809, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + InstrItinData <tc_2a160009, /*tc_2early*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [], + []>, + + InstrItinData <tc_2b2f4060, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3d905451, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + InstrItinData <tc_2b6f77c6, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2e00db30, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_2f185f5c, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2fc0c436, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3e61d314, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [2, 3, 2], + InstrItinData <tc_351fed2d, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3669266a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_367f7f3d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_36c68ad1, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [], + []>, + + InstrItinData <tc_395dc00f, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3eab77bd, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], + InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_3cb8ea06, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3d04548d, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3da80ba5, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_3e07fb90, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_43068634, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_41d5298e, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_45631a8d, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], + InstrItinData <tc_4403ca65, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44126683, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_452f85af, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_481e5e5c, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_47ab9233, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_49eb22c8, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_47f0b7ad, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], + InstrItinData <tc_4ca572d4, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], + []>, + + InstrItinData <tc_4d9914c9, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_485bb57c, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_4d99bca9, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4f7cd700, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4997da4a, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [1], - [Hex_FWD]>, + InstrItinData <tc_513bef45, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_511f28f6, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_51b866be, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_537e2013, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_523fcf30, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5274e61a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_52d7bbea, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [], + []>, + + InstrItinData <tc_53173427, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_53ee6546, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_53bc8a6a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_548f402d, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_53bdb2f6, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5625c6c1, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_540fdfbc, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_580a779c, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], + InstrItinData <tc_55050d58, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_583510c7, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + InstrItinData <tc_56d25411, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_57288781, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_594ab548, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5d806107, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_5acef64a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5ba5997d, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5fa2857c, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], + InstrItinData <tc_5eb851fc, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [2, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5fe9fcd0, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], + InstrItinData <tc_5f6847a1, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6264c5e0, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_60571023, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_639d93ee, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2], + InstrItinData <tc_609d2efe, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_60d76817, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], + []>, + + InstrItinData <tc_60f5738d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1], [Hex_FWD]>, - InstrItinData <tc_63cd9d2d, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_63fe3df7, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_66888ded, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_65dc7cc4, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_6792d5ff, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_69bb508b, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_681a2300, /*tc_3stall*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [2], + [Hex_FWD]>, - InstrItinData <tc_6c52d277, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_68cb12ce, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6c576d46, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 3], + InstrItinData <tc_6aa5711a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6ac37025, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_70cabf66, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + InstrItinData <tc_6ebb4a12, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6efc556e, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_73043bf4, /*tc_2early*/ + [InstrStage<1, [SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7639d4b0, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_746baa8e, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7675c0e9, /*tc_st*/ + InstrItinData <tc_74e47fd9, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_76c4c5ef, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_7934b9df, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7a830544, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_77781686, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + InstrItinData <tc_7f881c76, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_84df2cd3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_85523bcb, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_855b0b61, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_87735c3b, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_78b3c689, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_88fa1a78, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7986ba30, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 3], + InstrItinData <tc_897d1a9d, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7bc567a7, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_8b15472a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7c2dcd4d, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], + InstrItinData <tc_8bb285ec, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_7ca2ea10, /*tc_2*/ + InstrItinData <tc_8fd5f294, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8fe6b782, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_90f3e30c, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_976ddc4f, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7d01cbdc, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 1, 1], + InstrItinData <tc_97743097, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_999d32db, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_99be14ca, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7d9a56cd, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + InstrItinData <tc_9c00ce8d, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_81a23d44, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_9c98e8af, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_821c4233, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_9d5941c7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9ef61e5c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_82f0f122, /*tc_3x*/ + InstrItinData <tc_9faf76ae, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_9fdb5406, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a21dc435, /*tc_3x*/ [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_84630363, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_a27582fa, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_a46f0df5, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_86442910, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [], + InstrItinData <tc_a788683e, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a8acdac0, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a904d137, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_adb14c66, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b13761ae, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [], []>, - InstrItinData <tc_87601822, /*tc_2*/ + InstrItinData <tc_b166348b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b44c6e2a, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_88fa2da6, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_b5a33b22, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8c8041e6, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_b77c481f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8cb685d9, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + InstrItinData <tc_b7dd427e, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b9488031, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b9c0b731, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8def9c57, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + InstrItinData <tc_b9c4623f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bad2bcaf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8f0a6bad, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_bcc96cee, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8fab9ac3, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_bd90564c, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_92d1833c, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 2], + InstrItinData <tc_bde7aaf4, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_94e6ffd9, /*tc_2*/ + InstrItinData <tc_be706f30, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c2f7d806, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_95c54f8b, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [], - []>, + InstrItinData <tc_c5e2426d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9a13af9d, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + InstrItinData <tc_c6aa82f7, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c6ce9b3f, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c6ebf8dd, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c74f796f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c82dc1ff, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], [Hex_FWD]>, - InstrItinData <tc_9b73d261, /*tc_st*/ + InstrItinData <tc_caaebcba, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cd7374a0, /*tc_st*/ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9c18c9a5, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_cde8b071, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9c68db63, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + InstrItinData <tc_cf47a43f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cf59f215, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d088982c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d1090e34, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d24b2d85, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ce7a5ab, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d580173f, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9da3628f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], + InstrItinData <tc_d6bf0472, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9dafb7d3, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], + InstrItinData <tc_d9709180, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d9f95eef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9df8b0dc, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], + InstrItinData <tc_daa058fa, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_dbdffe3d, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9e86015f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 3], + InstrItinData <tc_e0739b8c, /*tc_2early*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9f518242, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_e1e0a2dc, /*tc_3stall*/ + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_ST]>], [], + []>, + + InstrItinData <tc_e1e99bfa, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e216a5db, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a12a5971, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e421e012, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a1fb80e1, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_e6b38e01, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a333d2a9, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2], + InstrItinData <tc_e7624c08, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [3], [Hex_FWD]>, - InstrItinData <tc_a4567c39, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], + InstrItinData <tc_e7d02c66, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a87879e8, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e913dc32, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a9c993d9, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_e9c822f7, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_e9fae2d6, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_ST]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef20db1c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef52ed71, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef84f62f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f2704b9a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f3eaa14b, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f47d212f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f49e76f4, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_aad55963, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + InstrItinData <tc_f4f43fb5, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f7dd9c9f, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f86c328a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f8eeed7a, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fcab4871, /*tc_newvjump*/ + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [], []>, - InstrItinData <tc_ab1b5e74, /*tc_2*/ + InstrItinData <tc_ff9ee76e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], + [Hex_FWD, Hex_FWD]> + ]; +} + +class DepScalarItinV62 { + list<InstrItinData> DepScalarItinV62_list = [ + InstrItinData <tc_0077f68c, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_00afc57e, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae0722f7, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 1], + InstrItinData <tc_00e7c26e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_03220ffa, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_038a1342, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae2c2dc2, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], + InstrItinData <tc_04c9decc, /*tc_3stall*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae762521, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], + InstrItinData <tc_05b6c987, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0a2b8c7c, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0cd51c76, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b08b653e, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], + InstrItinData <tc_0dc560de, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0fc1ae07, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], [Hex_FWD]>, - InstrItinData <tc_b08be45e, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_10b97e27, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b0f50e3c, /*tc_2*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_128f96e3, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1372bca1, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b189ad4c, /*tc_3stall*/ + InstrItinData <tc_1432937d, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_14cd4cfa, /*tc_2early*/ [InstrStage<1, [SLOT2]>], [2], [Hex_FWD]>, - InstrItinData <tc_b324366f, /*tc_2early*/ - [InstrStage<1, [SLOT3]>], [1, 2], + InstrItinData <tc_15411484, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_16d0d8d5, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_181af5d0, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b5bfaa60, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_1853ea6d, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1b82a277, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, + + InstrItinData <tc_1b9c9ee5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1c0005f9, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b5f5a094, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + InstrItinData <tc_1d5a38a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b86c7e8b, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_1e856f58, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_20280784, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_baccf077, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_234a11a5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bc5561d8, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_238d91d2, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bcf0e36e, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [], - []>, + InstrItinData <tc_29175780, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bd16579e, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_29641329, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_be995eaf, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + InstrItinData <tc_2a160009, /*tc_2early*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_2b2f4060, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bf6fa601, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + InstrItinData <tc_2b6f77c6, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c0cd91a8, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_2e00db30, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [], + []>, - InstrItinData <tc_c14739d5, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + InstrItinData <tc_2f185f5c, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c1dbc916, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + InstrItinData <tc_2fc0c436, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_351fed2d, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c58f771a, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_3669266a, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, - InstrItinData <tc_c85212ca, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], + InstrItinData <tc_367f7f3d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_36c68ad1, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [], + []>, + + InstrItinData <tc_395dc00f, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c8f9a6f6, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, - InstrItinData <tc_ca280e8b, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_3cb8ea06, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cbe45117, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2], + InstrItinData <tc_3d04548d, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_3da80ba5, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_cd321066, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_3e07fb90, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d108a090, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2], + InstrItinData <tc_41d5298e, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4403ca65, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_44126683, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d1b5a4b6, /*tc_1*/ + InstrItinData <tc_452f85af, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_481e5e5c, /*tc_2early*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d2609065, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_49eb22c8, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d267fa19, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [], + InstrItinData <tc_4ca572d4, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], []>, - InstrItinData <tc_d2a33af5, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_4d9914c9, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d63b71d1, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_4d99bca9, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d6a805a8, /*tc_3stall*/ + InstrItinData <tc_4f7cd700, /*tc_3stall*/ [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d95f4e98, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], + InstrItinData <tc_513bef45, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_51b866be, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_523fcf30, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da79106e, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_5274e61a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_52d7bbea, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_53173427, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_53bc8a6a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_dbe218dd, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2], + InstrItinData <tc_53bdb2f6, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_540fdfbc, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_55050d58, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_56d25411, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_dcfee7ae, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2], + InstrItinData <tc_57288781, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e17ce9ad, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + InstrItinData <tc_594ab548, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e2480a7f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + InstrItinData <tc_5acef64a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5ba5997d, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5eb851fc, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_5f6847a1, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_60571023, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e2c08bb4, /*tc_3stall*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + InstrItinData <tc_609d2efe, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e2c31426, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + InstrItinData <tc_60d76817, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], []>, - InstrItinData <tc_e578178f, /*tc_ld*/ + InstrItinData <tc_60f5738d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_63fe3df7, /*tc_ld*/ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e836c161, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_66888ded, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e8c7a357, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_6792d5ff, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_681a2300, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_68cb12ce, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_eb07ef6f, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [1, 2], + InstrItinData <tc_6aa5711a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ecfaae86, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], - [Hex_FWD]>, + InstrItinData <tc_6ac37025, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ef0ebaaa, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_6ebb4a12, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ef2676fd, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [], + InstrItinData <tc_6efc556e, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], []>, - InstrItinData <tc_f027ebe9, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [2], - [Hex_FWD]>, + InstrItinData <tc_73043bf4, /*tc_2early*/ + [InstrStage<1, [SLOT3]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_746baa8e, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_74e47fd9, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f055fbb6, /*tc_3x*/ + InstrItinData <tc_7934b9df, /*tc_3x*/ [InstrStage<1, [SLOT3]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f1240c08, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_7a830544, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f16d5b17, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_7f881c76, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_84df2cd3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_85523bcb, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_855b0b61, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_87735c3b, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_88fa1a78, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f1aa2cdb, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + InstrItinData <tc_897d1a9d, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f26aa619, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], + InstrItinData <tc_8b15472a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8bb285ec, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData <tc_f4608adc, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [1, 1], + InstrItinData <tc_8fd5f294, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_8fe6b782, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_90f3e30c, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_faab1248, /*tc_2*/ + InstrItinData <tc_976ddc4f, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fcee8723, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_97743097, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_999d32db, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_99be14ca, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_feb4974b, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [2, 2], - [Hex_FWD, Hex_FWD]> - ]; -} + InstrItinData <tc_9c00ce8d, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, -class DepScalarItinV62 { - list<InstrItinData> DepScalarItinV62_list = [ - InstrItinData <tc_049dfb74, /*tc_2early*/ + InstrItinData <tc_9c98e8af, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9d5941c7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9ef61e5c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9faf76ae, /*tc_2early*/ [InstrStage<1, [SLOT2]>], [1], [Hex_FWD]>, - InstrItinData <tc_0767081f, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_9fdb5406, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a21dc435, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_07ac815d, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_a27582fa, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_a46f0df5, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_090485bb, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + InstrItinData <tc_a788683e, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a8acdac0, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_09c86199, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], + InstrItinData <tc_a904d137, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_adb14c66, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b13761ae, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_b166348b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_09faec3b, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], + InstrItinData <tc_b44c6e2a, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_0cb867f2, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 2, 2], + InstrItinData <tc_b5a33b22, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1000eb10, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_b77c481f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_128719e8, /*tc_ld*/ + InstrItinData <tc_b7dd427e, /*tc_ld*/ [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_136c4786, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], + InstrItinData <tc_b9488031, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_14da557c, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + InstrItinData <tc_b9c0b731, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1b6011fb, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_b9c4623f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bad2bcaf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bcc96cee, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1b834fe7, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_bd90564c, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1e062b18, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_bde7aaf4, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1e69aa99, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_be706f30, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1f9668cc, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [3, 1], + InstrItinData <tc_c2f7d806, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_1fe8323c, /*tc_2*/ - [InstrStage<1, [SLOT3]>], [4, 2], + InstrItinData <tc_c5e2426d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_20a8e109, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_c6aa82f7, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c6ce9b3f, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_210b2456, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], + InstrItinData <tc_c6ebf8dd, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c74f796f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_251c87b2, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], + InstrItinData <tc_c82dc1ff, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_caaebcba, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_261d9b78, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_cd7374a0, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_28d296df, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2, 2], + InstrItinData <tc_cde8b071, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cf47a43f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_29c14515, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [4, 1], + InstrItinData <tc_cf59f215, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2aaab1e0, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d088982c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2c8fe5ae, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_d1090e34, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d24b2d85, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2d1e6f5c, /*tc_4x*/ + InstrItinData <tc_d580173f, /*tc_4x*/ [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_2e55aa16, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], + InstrItinData <tc_d6bf0472, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d9709180, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d9f95eef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_30665cb0, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1], - [Hex_FWD]>, + InstrItinData <tc_daa058fa, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_336e698c, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], + InstrItinData <tc_dbdffe3d, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_34e882a4, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1], - [Hex_FWD]>, + InstrItinData <tc_e0739b8c, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_35fb9d13, /*tc_2early*/ - [InstrStage<1, [SLOT0]>], [], + InstrItinData <tc_e1e0a2dc, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], []>, - InstrItinData <tc_37326008, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e1e99bfa, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3993c58b, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 3, 2], + InstrItinData <tc_e216a5db, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3b4892c6, /*tc_3x*/ + InstrItinData <tc_e421e012, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e6b38e01, /*tc_3x*/ [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3bea1824, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e7624c08, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3], + [Hex_FWD]>, - InstrItinData <tc_3c10f809, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + InstrItinData <tc_e7d02c66, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3d905451, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], + InstrItinData <tc_e913dc32, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_3e61d314, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [2, 3, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e9c822f7, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, - InstrItinData <tc_3eab77bd, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_e9fae2d6, /*tc_2early*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_43068634, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_ef20db1c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_45631a8d, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], + InstrItinData <tc_ef52ed71, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_47ab9233, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_ef84f62f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_47f0b7ad, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1], + InstrItinData <tc_f2704b9a, /*tc_2early*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_485bb57c, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_f3eaa14b, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_4997da4a, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [1], - [Hex_FWD]>, + InstrItinData <tc_f47d212f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_511f28f6, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_f49e76f4, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_537e2013, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], - [Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_53ee6546, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_f4f43fb5, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_548f402d, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_f7dd9c9f, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5625c6c1, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + InstrItinData <tc_f86c328a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_580a779c, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_583510c7, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + InstrItinData <tc_f8eeed7a, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5d806107, /*tc_3x*/ + InstrItinData <tc_fcab4871, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_ff9ee76e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], + [Hex_FWD, Hex_FWD]> + ]; +} + +class DepScalarItinV65 { + list<InstrItinData> DepScalarItinV65_list = [ + InstrItinData <tc_0077f68c, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_00afc57e, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_00e7c26e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_03220ffa, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_038a1342, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_04c9decc, /*tc_3stall*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5fa2857c, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 2], + InstrItinData <tc_05b6c987, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_5fe9fcd0, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_0a2b8c7c, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6264c5e0, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + InstrItinData <tc_0cd51c76, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_0dc560de, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_639d93ee, /*tc_3*/ - [InstrStage<1, [SLOT2, SLOT3]>], [2], + InstrItinData <tc_0fc1ae07, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [2], [Hex_FWD]>, - InstrItinData <tc_63cd9d2d, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_10b97e27, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_128f96e3, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_1372bca1, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_65dc7cc4, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1432937d, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [1, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_69bb508b, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], + InstrItinData <tc_14cd4cfa, /*tc_2early*/ + [InstrStage<1, [SLOT2]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_15411484, /*tc_3*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_16d0d8d5, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6c52d277, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_181af5d0, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_6c576d46, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 3], + InstrItinData <tc_1853ea6d, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_70cabf66, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1b82a277, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3], + [Hex_FWD]>, - InstrItinData <tc_7639d4b0, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1b9c9ee5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7675c0e9, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 3, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1c0005f9, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_76c4c5ef, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_1d5a38a8, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_77781686, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_1e856f58, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_78b3c689, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_20280784, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7986ba30, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 3], + InstrItinData <tc_234a11a5, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_238d91d2, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7bc567a7, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_29175780, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7c2dcd4d, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], - [Hex_FWD]>, + InstrItinData <tc_29641329, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2a160009, /*tc_2early*/ + [InstrStage<1, [SLOT0]>], [], + []>, - InstrItinData <tc_7ca2ea10, /*tc_2*/ + InstrItinData <tc_2b2f4060, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2b6f77c6, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_7d01cbdc, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_2e00db30, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [], + []>, - InstrItinData <tc_7d9a56cd, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + InstrItinData <tc_2f185f5c, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_2fc0c436, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_81a23d44, /*tc_2early*/ + InstrItinData <tc_351fed2d, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_821c4233, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_82f0f122, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [4, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_3669266a, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], + [Hex_FWD]>, - InstrItinData <tc_84630363, /*tc_3*/ - [InstrStage<1, [SLOT2]>], [2, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_367f7f3d, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [], + []>, - InstrItinData <tc_86442910, /*tc_ld*/ + InstrItinData <tc_36c68ad1, /*tc_ld*/ [InstrStage<1, [SLOT0, SLOT1]>], [], []>, - InstrItinData <tc_87601822, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_395dc00f, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 3, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_88fa2da6, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_3bc2c5d3, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_3cb8ea06, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8c8041e6, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_3d04548d, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8cb685d9, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_3da80ba5, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, - InstrItinData <tc_8def9c57, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + InstrItinData <tc_3e07fb90, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8f0a6bad, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + InstrItinData <tc_41d5298e, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_8fab9ac3, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 3, 1, 2, 3], + InstrItinData <tc_4403ca65, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_92d1833c, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 2], + InstrItinData <tc_44126683, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_94e6ffd9, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], - [Hex_FWD, Hex_FWD]>, - - InstrItinData <tc_95c54f8b, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [], - []>, - - InstrItinData <tc_9a13af9d, /*tc_1*/ + InstrItinData <tc_452f85af, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData <tc_9b73d261, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_481e5e5c, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9c18c9a5, /*tc_1*/ + InstrItinData <tc_49eb22c8, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9c68db63, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_4ca572d4, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], + []>, + + InstrItinData <tc_4d9914c9, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_4d99bca9, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9ce7a5ab, /*tc_newvjump*/ + InstrItinData <tc_4f7cd700, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_513bef45, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_51b866be, /*tc_newvjump*/ [InstrStage<1, [SLOT0]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9da3628f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_523fcf30, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9dafb7d3, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], + InstrItinData <tc_5274e61a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9df8b0dc, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_52d7bbea, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, - InstrItinData <tc_9e86015f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [2, 3], + InstrItinData <tc_53173427, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_9f518242, /*tc_1*/ + InstrItinData <tc_53bc8a6a, /*tc_1*/ [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a12a5971, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_53bdb2f6, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a1fb80e1, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [2, 1], + InstrItinData <tc_540fdfbc, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_55050d58, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_56d25411, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a333d2a9, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], - [Hex_FWD]>, + InstrItinData <tc_57288781, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a4567c39, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2, 2], + InstrItinData <tc_594ab548, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a87879e8, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5acef64a, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_a9c993d9, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_5ba5997d, /*tc_2*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_aad55963, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], - []>, + InstrItinData <tc_5eb851fc, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [2, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ab1b5e74, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_5f6847a1, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae0722f7, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1], + InstrItinData <tc_60571023, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae2c2dc2, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 2], + InstrItinData <tc_609d2efe, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ae762521, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_60d76817, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [], + []>, - InstrItinData <tc_b08b653e, /*tc_2early*/ - [InstrStage<1, [SLOT2]>], [1], + InstrItinData <tc_60f5738d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [1], [Hex_FWD]>, - InstrItinData <tc_b08be45e, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 3, 2], + InstrItinData <tc_63fe3df7, /*tc_latepredldaia*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_66888ded, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b0f50e3c, /*tc_2*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_6792d5ff, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b189ad4c, /*tc_3stall*/ + InstrItinData <tc_681a2300, /*tc_3stall*/ [InstrStage<1, [SLOT2]>], [2], [Hex_FWD]>, - InstrItinData <tc_b324366f, /*tc_2early*/ - [InstrStage<1, [SLOT3]>], [1, 2], + InstrItinData <tc_68cb12ce, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b5bfaa60, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + InstrItinData <tc_6aa5711a, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b5f5a094, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + InstrItinData <tc_6ac37025, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_b86c7e8b, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_6ebb4a12, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_6efc556e, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], + []>, + + InstrItinData <tc_73043bf4, /*tc_1*/ + [InstrStage<1, [SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_baccf077, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2, 2], + InstrItinData <tc_746baa8e, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_74e47fd9, /*tc_latepredstaia*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bc5561d8, /*tc_3x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1, 2], + InstrItinData <tc_7934b9df, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7a830544, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_7f881c76, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_84df2cd3, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_85523bcb, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_855b0b61, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_87735c3b, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bcf0e36e, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [], - []>, + InstrItinData <tc_88fa1a78, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bd16579e, /*tc_2*/ + InstrItinData <tc_897d1a9d, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_be995eaf, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + InstrItinData <tc_8b15472a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_bf6fa601, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2], + InstrItinData <tc_8bb285ec, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_8fd5f294, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c0cd91a8, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_8fe6b782, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c14739d5, /*tc_st*/ + InstrItinData <tc_90f3e30c, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c1dbc916, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], + InstrItinData <tc_976ddc4f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_97743097, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c58f771a, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_999d32db, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [1], + [Hex_FWD]>, - InstrItinData <tc_c85212ca, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [2, 2, 2], + InstrItinData <tc_99be14ca, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_c8f9a6f6, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], + InstrItinData <tc_9c00ce8d, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ca280e8b, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + InstrItinData <tc_9c98e8af, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_cbe45117, /*tc_2early*/ + InstrItinData <tc_9d5941c7, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9ef61e5c, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_9faf76ae, /*tc_1*/ [InstrStage<1, [SLOT2]>], [2], [Hex_FWD]>, - InstrItinData <tc_cd321066, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_9fdb5406, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d108a090, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_a21dc435, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d1b5a4b6, /*tc_1*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + InstrItinData <tc_a27582fa, /*tc_3*/ + [InstrStage<1, [SLOT2, SLOT3]>], [2], + [Hex_FWD]>, + + InstrItinData <tc_a46f0df5, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a788683e, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_a8acdac0, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d2609065, /*tc_1*/ + InstrItinData <tc_a904d137, /*tc_1*/ [InstrStage<1, [SLOT0, SLOT1]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d267fa19, /*tc_2early*/ + InstrItinData <tc_adb14c66, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b13761ae, /*tc_3stall*/ [InstrStage<1, [SLOT2]>], [], []>, - InstrItinData <tc_d2a33af5, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_b166348b, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d63b71d1, /*tc_2early*/ - [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], + InstrItinData <tc_b44c6e2a, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d6a805a8, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [2, 1], + InstrItinData <tc_b5a33b22, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b77c481f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b7dd427e, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b9488031, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b9c0b731, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_b9c4623f, /*tc_2*/ + [InstrStage<1, [SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_d95f4e98, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2, 2], + InstrItinData <tc_bad2bcaf, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 2, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_da79106e, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [1, 2, 2], + InstrItinData <tc_bcc96cee, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bd90564c, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_bde7aaf4, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_dbe218dd, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2], + InstrItinData <tc_be706f30, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_dcfee7ae, /*tc_newvjump*/ - [InstrStage<1, [SLOT0]>], [3, 2], + InstrItinData <tc_c2f7d806, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e17ce9ad, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_c5e2426d, /*tc_3stall*/ + [InstrStage<1, [SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e2480a7f, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], - [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData <tc_c6aa82f7, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e2c08bb4, /*tc_3stall*/ + InstrItinData <tc_c6ce9b3f, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_c6ebf8dd, /*tc_3x*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e2c31426, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [], - []>, + InstrItinData <tc_c74f796f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e578178f, /*tc_ld*/ - [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 3, 1, 2], + InstrItinData <tc_c82dc1ff, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [1], + [Hex_FWD]>, + + InstrItinData <tc_caaebcba, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e836c161, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData <tc_cd7374a0, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_e8c7a357, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2], + InstrItinData <tc_cde8b071, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_eb07ef6f, /*tc_2early*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2], + InstrItinData <tc_cf47a43f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_cf59f215, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ecfaae86, /*tc_3*/ - [InstrStage<1, [SLOT2]>], [1], - [Hex_FWD]>, + InstrItinData <tc_d088982c, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ef0ebaaa, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [1, 2], + InstrItinData <tc_d1090e34, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_ef2676fd, /*tc_st*/ - [InstrStage<1, [SLOT0]>], [], - []>, + InstrItinData <tc_d24b2d85, /*tc_latepredstaia*/ + [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f027ebe9, /*tc_ld*/ - [InstrStage<1, [SLOT0]>], [2], - [Hex_FWD]>, + InstrItinData <tc_d580173f, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f055fbb6, /*tc_3x*/ - [InstrStage<1, [SLOT3]>], [2, 1], + InstrItinData <tc_d6bf0472, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d9709180, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_d9f95eef, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_daa058fa, /*tc_3stall*/ + [InstrStage<1, [SLOT0]>], [1, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f1240c08, /*tc_2*/ - [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], + InstrItinData <tc_dbdffe3d, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f16d5b17, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], + InstrItinData <tc_e0739b8c, /*tc_1*/ + [InstrStage<1, [SLOT2]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f1aa2cdb, /*tc_4x*/ - [InstrStage<1, [SLOT2, SLOT3]>], [5, 5, 1], + InstrItinData <tc_e1e0a2dc, /*tc_3stall*/ + [InstrStage<1, [SLOT2]>], [], + []>, + + InstrItinData <tc_e1e99bfa, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e216a5db, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_f26aa619, /*tc_1*/ - [InstrStage<1, [SLOT0, SLOT1]>], [3], + InstrItinData <tc_e421e012, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e6b38e01, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e7624c08, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData <tc_f4608adc, /*tc_3stall*/ - [InstrStage<1, [SLOT0]>], [1, 1], + InstrItinData <tc_e7d02c66, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e913dc32, /*tc_3x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_e9c822f7, /*tc_2latepred*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4], + [Hex_FWD]>, + + InstrItinData <tc_e9fae2d6, /*tc_1*/ + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef20db1c, /*tc_3x*/ + [InstrStage<1, [SLOT3]>], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef52ed71, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_ef84f62f, /*tc_2*/ + [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f2704b9a, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData <tc_faab1248, /*tc_2*/ + InstrItinData <tc_f3eaa14b, /*tc_4x*/ + [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f47d212f, /*tc_ld*/ + [InstrStage<1, [SLOT0, SLOT1]>], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f49e76f4, /*tc_2*/ [InstrStage<1, [SLOT2, SLOT3]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_fcee8723, /*tc_st*/ - [InstrStage<1, [SLOT0, SLOT1]>], [1, 2, 2], + InstrItinData <tc_f4f43fb5, /*tc_ld*/ + [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData <tc_feb4974b, /*tc_3stall*/ - [InstrStage<1, [SLOT3]>], [2, 2], + InstrItinData <tc_f7dd9c9f, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f86c328a, /*tc_st*/ + [InstrStage<1, [SLOT0, SLOT1]>], [3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_f8eeed7a, /*tc_1*/ + [InstrStage<1, [SLOT2, SLOT3]>], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData <tc_fcab4871, /*tc_newvjump*/ + [InstrStage<1, [SLOT0]>], [], + []>, + + InstrItinData <tc_ff9ee76e, /*tc_st*/ + [InstrStage<1, [SLOT0]>], [2, 3], [Hex_FWD, Hex_FWD]> ]; } diff --git a/llvm/lib/Target/Hexagon/HexagonDepITypes.h b/llvm/lib/Target/Hexagon/HexagonDepITypes.h index be831b9501e..7e06ccede6e 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepITypes.h +++ b/llvm/lib/Target/Hexagon/HexagonDepITypes.h @@ -1,4 +1,4 @@ -//===--- HexagonDepITypes.h -----------------------------------------------===// +//===- HexagonDepITypes.h -------------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,6 +6,9 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + namespace llvm { namespace HexagonII { @@ -15,8 +18,17 @@ enum Type { TypeALU32_ADDI = 2, TypeALU64 = 3, TypeCJ = 4, + TypeCOPROC_VX = 5, TypeCR = 6, + TypeCVI_4SLOT_MPY = 7, + TypeCVI_GATHER = 8, + TypeCVI_GATHER_RST = 9, TypeCVI_HIST = 10, + TypeCVI_SCATTER = 11, + TypeCVI_SCATTER_DV = 12, + TypeCVI_SCATTER_NEW_RST = 13, + TypeCVI_SCATTER_NEW_ST = 14, + TypeCVI_SCATTER_RST = 15, TypeCVI_VA = 16, TypeCVI_VA_DV = 17, TypeCVI_VINLANESAT = 18, @@ -29,6 +41,7 @@ enum Type { TypeCVI_VP = 25, TypeCVI_VP_VS = 26, TypeCVI_VS = 27, + TypeCVI_VS_VX = 28, TypeCVI_VX = 29, TypeCVI_VX_DV = 30, TypeCVI_VX_LATE = 31, diff --git a/llvm/lib/Target/Hexagon/HexagonDepITypes.td b/llvm/lib/Target/Hexagon/HexagonDepITypes.td index ac1989e4dd8..0a385bf938f 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepITypes.td +++ b/llvm/lib/Target/Hexagon/HexagonDepITypes.td @@ -1,4 +1,4 @@ -//===--- HexagonDepITypes.td ----------------------------------------------===// +//===- HexagonDepITypes.td ------------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,6 +6,9 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + class IType<bits<6> t> { bits<6> Value = t; } def TypeALU32_2op : IType<0>; @@ -13,8 +16,17 @@ def TypeALU32_3op : IType<1>; def TypeALU32_ADDI : IType<2>; def TypeALU64 : IType<3>; def TypeCJ : IType<4>; +def TypeCOPROC_VX : IType<5>; def TypeCR : IType<6>; +def TypeCVI_4SLOT_MPY : IType<7>; +def TypeCVI_GATHER : IType<8>; +def TypeCVI_GATHER_RST : IType<9>; def TypeCVI_HIST : IType<10>; +def TypeCVI_SCATTER : IType<11>; +def TypeCVI_SCATTER_DV : IType<12>; +def TypeCVI_SCATTER_NEW_RST : IType<13>; +def TypeCVI_SCATTER_NEW_ST : IType<14>; +def TypeCVI_SCATTER_RST : IType<15>; def TypeCVI_VA : IType<16>; def TypeCVI_VA_DV : IType<17>; def TypeCVI_VINLANESAT : IType<18>; @@ -27,6 +39,7 @@ def TypeCVI_VM_VP_LDU : IType<24>; def TypeCVI_VP : IType<25>; def TypeCVI_VP_VS : IType<26>; def TypeCVI_VS : IType<27>; +def TypeCVI_VS_VX : IType<28>; def TypeCVI_VX : IType<29>; def TypeCVI_VX_DV : IType<30>; def TypeCVI_VX_LATE : IType<31>; diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td index 1b24be47715..9f98da3a1de 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td +++ b/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td @@ -1,4 +1,4 @@ -//===--- HexagonDepInstrFormats.td ----------------------------------------===// +//===- HexagonDepInstrFormats.td ------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,6 +6,9 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + class Enc_890909 : OpcodeHexagon { bits <5> Rs32; @@ -15,6 +18,18 @@ class Enc_890909 : OpcodeHexagon { bits <2> Pe4; let Inst{6-5} = Pe4{1-0}; } +class Enc_9be1de : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} class Enc_527412 : OpcodeHexagon { bits <2> Ps4; let Inst{17-16} = Ps4{1-0}; @@ -46,14 +61,23 @@ class Enc_27b757 : OpcodeHexagon { bits <5> Vs32; let Inst{4-0} = Vs32{4-0}; } -class Enc_5de85f : OpcodeHexagon { +class Enc_8d04c3 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_1de724 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; let Inst{7-1} = Ii{8-2}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-22} = n1{2-0}; } class Enc_0e41fa : OpcodeHexagon { bits <5> Vuu32; @@ -63,12 +87,48 @@ class Enc_0e41fa : OpcodeHexagon { bits <5> Vd32; let Inst{4-0} = Vd32{4-0}; } +class Enc_2a736a : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_3d6d37 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_a641d0 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} class Enc_802dc0 : OpcodeHexagon { bits <1> Ii; let Inst{8-8} = Ii{0-0}; bits <2> Qv4; let Inst{23-22} = Qv4{1-0}; } +class Enc_6a4549 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_6b197f : OpcodeHexagon { bits <4> Ii; let Inst{8-5} = Ii{3-0}; @@ -77,6 +137,14 @@ class Enc_6b197f : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_1f3376 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} class Enc_1f5d8f : OpcodeHexagon { bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; @@ -165,6 +233,14 @@ class Enc_7eee72 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_310ba1 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} class Enc_d7dc10 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; @@ -191,6 +267,14 @@ class Enc_8dec2e : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_28dcbb : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} class Enc_eaa9f8 : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; @@ -207,6 +291,14 @@ class Enc_509701 : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } +class Enc_c84567 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_830e5d : OpcodeHexagon { bits <8> Ii; let Inst{12-5} = Ii{7-0}; @@ -218,6 +310,12 @@ class Enc_830e5d : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_ae0040 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <6> Sd64; + let Inst{5-0} = Sd64{5-0}; +} class Enc_79b8c8 : OpcodeHexagon { bits <6> Ii; let Inst{6-3} = Ii{5-2}; @@ -238,6 +336,16 @@ class Enc_58a8bf : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_e8ddd5 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_041d7b : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -261,6 +369,14 @@ class Enc_f44229 : OpcodeHexagon { bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } +class Enc_fc563d : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_aad80c : OpcodeHexagon { bits <5> Vuu32; let Inst{12-8} = Vuu32{4-0}; @@ -432,6 +548,13 @@ class Enc_6a5972 : OpcodeHexagon { bits <4> Rt16; let Inst{11-8} = Rt16{3-0}; } +class Enc_ff3442 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; +} class Enc_53dca9 : OpcodeHexagon { bits <6> Ii; let Inst{11-8} = Ii{5-2}; @@ -456,6 +579,12 @@ class Enc_93af4c : OpcodeHexagon { bits <4> Rx16; let Inst{3-0} = Rx16{3-0}; } +class Enc_621fba : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Gd32; + let Inst{4-0} = Gd32{4-0}; +} class Enc_5bdd42 : OpcodeHexagon { bits <7> Ii; let Inst{8-5} = Ii{6-3}; @@ -464,6 +593,14 @@ class Enc_5bdd42 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_ad9bef : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} class Enc_71f1b4 : OpcodeHexagon { bits <6> Ii; let Inst{8-5} = Ii{5-2}; @@ -483,6 +620,12 @@ class Enc_14640c : OpcodeHexagon { let Inst{24-22} = n1{3-1}; let Inst{13-13} = n1{0-0}; } +class Enc_2516bf : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_31db33 : OpcodeHexagon { bits <2> Qt4; let Inst{6-5} = Qt4{1-0}; @@ -513,6 +656,24 @@ class Enc_784502 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_9a9d62 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_3a81ac : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_6413b6 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -592,6 +753,16 @@ class Enc_e39bb2 : OpcodeHexagon { bits <4> Rd16; let Inst{3-0} = Rd16{3-0}; } +class Enc_7db2f8 : OpcodeHexagon { + bits <5> Vu32; + let Inst{13-9} = Vu32{4-0}; + bits <5> Vv32; + let Inst{8-4} = Vv32{4-0}; + bits <4> Vdd16; + let Inst{3-0} = Vdd16{3-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_1b64fb : OpcodeHexagon { bits <16> Ii; let Inst{26-25} = Ii{15-14}; @@ -670,6 +841,10 @@ class Enc_fcf7a7 : OpcodeHexagon { bits <2> Pd4; let Inst{1-0} = Pd4{1-0}; } +class Enc_2c3281 : OpcodeHexagon { + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_55355c : OpcodeHexagon { bits <2> Ii; let Inst{13-13} = Ii{1-1}; @@ -745,6 +920,10 @@ class Enc_fef969 : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_b2ffce : OpcodeHexagon { + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_63eaeb : OpcodeHexagon { bits <2> Ii; let Inst{1-0} = Ii{1-0}; @@ -769,6 +948,12 @@ class Enc_372c9d : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_9e9047 : OpcodeHexagon { + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} class Enc_4dff07 : OpcodeHexagon { bits <2> Qv4; let Inst{12-11} = Qv4{1-0}; @@ -815,6 +1000,16 @@ class Enc_b388cf : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_880793 : OpcodeHexagon { + bits <3> Qt8; + let Inst{2-0} = Qt8{2-0}; + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_ad1c74 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -854,6 +1049,16 @@ class Enc_5e87ce : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_158beb : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; +} class Enc_f7ea77 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -897,6 +1102,14 @@ class Enc_226535 : OpcodeHexagon { bits <5> Rt32; let Inst{4-0} = Rt32{4-0}; } +class Enc_96f0fd : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <3> Qdd8; + let Inst{2-0} = Qdd8{2-0}; +} class Enc_31aa6a : OpcodeHexagon { bits <5> Ii; let Inst{6-3} = Ii{4-1}; @@ -907,6 +1120,12 @@ class Enc_31aa6a : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_932b58 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; +} class Enc_397f23 : OpcodeHexagon { bits <8> Ii; let Inst{13-13} = Ii{7-7}; @@ -973,6 +1192,14 @@ class Enc_01d3d0 : OpcodeHexagon { bits <5> Vdd32; let Inst{4-0} = Vdd32{4-0}; } +class Enc_3126d7 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_b0e9d8 : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; @@ -1049,6 +1276,12 @@ class Enc_88c16c : OpcodeHexagon { bits <5> Rxx32; let Inst{4-0} = Rxx32{4-0}; } +class Enc_e7408c : OpcodeHexagon { + bits <6> Sss64; + let Inst{21-16} = Sss64{5-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} class Enc_770858 : OpcodeHexagon { bits <2> Ps4; let Inst{6-5} = Ps4{1-0}; @@ -1090,6 +1323,16 @@ class Enc_412ff0 : OpcodeHexagon { bits <5> Rxx32; let Inst{12-8} = Rxx32{4-0}; } +class Enc_8e9fbd : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} class Enc_c9a18e : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -1134,6 +1377,16 @@ class Enc_d6990d : OpcodeHexagon { bits <5> Vxx32; let Inst{4-0} = Vxx32{4-0}; } +class Enc_6c4697 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_6c9440 : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; @@ -1278,6 +1531,12 @@ class Enc_a803e0 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; } +class Enc_fde0e3 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_45364e : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; @@ -1298,6 +1557,12 @@ class Enc_b909d2 : OpcodeHexagon { let Inst{13-13} = n1{1-1}; let Inst{8-8} = n1{0-0}; } +class Enc_790d6e : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_e6c957 : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; @@ -1358,6 +1623,14 @@ class Enc_0ed752 : OpcodeHexagon { bits <5> Cdd32; let Inst{4-0} = Cdd32{4-0}; } +class Enc_908985 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_143445 : OpcodeHexagon { bits <13> Ii; let Inst{26-25} = Ii{12-11}; @@ -1385,6 +1658,16 @@ class Enc_3e3989 : OpcodeHexagon { let Inst{25-22} = n1{4-1}; let Inst{8-8} = n1{0-0}; } +class Enc_12dd8f : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} class Enc_152467 : OpcodeHexagon { bits <5> Ii; let Inst{8-5} = Ii{4-1}; @@ -1393,6 +1676,14 @@ class Enc_152467 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_6b1bc4 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <3> Qt8; + let Inst{10-8} = Qt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_daea09 : OpcodeHexagon { bits <17> Ii; let Inst{23-22} = Ii{16-15}; @@ -1421,6 +1712,32 @@ class Enc_a198f6 : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_a265b7 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_4e4a80 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} +class Enc_8d5d98 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} class Enc_3dac0b : OpcodeHexagon { bits <2> Qt4; let Inst{6-5} = Qt4{1-0}; @@ -1463,6 +1780,16 @@ class Enc_2df31d : OpcodeHexagon { bits <4> Rd16; let Inst{3-0} = Rd16{3-0}; } +class Enc_b0e553 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_25bef0 : OpcodeHexagon { bits <16> Ii; let Inst{26-25} = Ii{15-14}; @@ -1482,6 +1809,12 @@ class Enc_f82302 : OpcodeHexagon { let Inst{26-25} = n1{2-1}; let Inst{23-23} = n1{0-0}; } +class Enc_44271f : OpcodeHexagon { + bits <5> Gs32; + let Inst{20-16} = Gs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} class Enc_83ee64 : OpcodeHexagon { bits <5> Ii; let Inst{12-8} = Ii{4-0}; @@ -1524,6 +1857,14 @@ class Enc_4df4e9 : OpcodeHexagon { bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } +class Enc_263841 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} class Enc_91b9fe : OpcodeHexagon { bits <5> Ii; let Inst{6-3} = Ii{4-1}; @@ -1564,6 +1905,11 @@ class Enc_bd1cbc : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_d0fe02 : OpcodeHexagon { + bits <5> Rxx32; + let Inst{20-16} = Rxx32{4-0}; + bits <0> sgp10; +} class Enc_a30110 : OpcodeHexagon { bits <5> Vu32; let Inst{12-8} = Vu32{4-0}; @@ -1583,6 +1929,16 @@ class Enc_f3f408 : OpcodeHexagon { bits <5> Vd32; let Inst{4-0} = Vd32{4-0}; } +class Enc_ce4c54 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_690862 : OpcodeHexagon { bits <13> Ii; let Inst{26-25} = Ii{12-11}; @@ -1593,6 +1949,20 @@ class Enc_690862 : OpcodeHexagon { bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } +class Enc_e570b0 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_3c46e8 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_2a3787 : OpcodeHexagon { bits <13> Ii; let Inst{26-25} = Ii{12-11}; @@ -1640,6 +2010,22 @@ class Enc_729ff7 : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } +class Enc_5883d0 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_ff0e49 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <6> Sdd64; + let Inst{5-0} = Sdd64{5-0}; +} class Enc_217147 : OpcodeHexagon { bits <2> Qv4; let Inst{23-22} = Qv4{1-0}; @@ -1674,6 +2060,14 @@ class Enc_541f26 : OpcodeHexagon { bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; } +class Enc_9aae4a : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <3> Qd8; + let Inst{2-0} = Qd8{2-0}; +} class Enc_724154 : OpcodeHexagon { bits <6> II; let Inst{5-0} = II{5-0}; @@ -1781,6 +2175,12 @@ class Enc_22c845 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_ed5027 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Gdd32; + let Inst{4-0} = Gdd32{4-0}; +} class Enc_9b0bc1 : OpcodeHexagon { bits <2> Pu4; let Inst{6-5} = Pu4{1-0}; @@ -1828,6 +2228,12 @@ class Enc_96ce4f : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_2bbae6 : OpcodeHexagon { + bits <6> Ss64; + let Inst{21-16} = Ss64{5-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} class Enc_143a3c : OpcodeHexagon { bits <6> Ii; let Inst{13-8} = Ii{5-0}; @@ -1959,6 +2365,26 @@ class Enc_b43b67 : OpcodeHexagon { bits <2> Qx4; let Inst{6-5} = Qx4{1-0}; } +class Enc_1cd70f : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_3a527f : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_4aca3a : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -1977,6 +2403,12 @@ class Enc_b38ffc : OpcodeHexagon { bits <4> Rt16; let Inst{3-0} = Rt16{3-0}; } +class Enc_5c3a80 : OpcodeHexagon { + bits <3> Qt8; + let Inst{10-8} = Qt8{2-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} class Enc_cda00a : OpcodeHexagon { bits <12> Ii; let Inst{19-16} = Ii{11-8}; @@ -1994,6 +2426,24 @@ class Enc_2fbf3c : OpcodeHexagon { bits <4> Rd16; let Inst{3-0} = Rd16{3-0}; } +class Enc_a4ae28 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_dd5f9f : OpcodeHexagon { + bits <3> Qtt8; + let Inst{2-0} = Qtt8{2-0}; + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_70b24b : OpcodeHexagon { bits <6> Ii; let Inst{8-5} = Ii{5-2}; @@ -2040,6 +2490,16 @@ class Enc_08d755 : OpcodeHexagon { bits <2> Pd4; let Inst{1-0} = Pd4{1-0}; } +class Enc_a7ca29 : OpcodeHexagon { + bits <3> Qt8; + let Inst{2-0} = Qt8{2-0}; + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_1178da : OpcodeHexagon { bits <3> Ii; let Inst{7-5} = Ii{2-0}; @@ -2058,6 +2518,14 @@ class Enc_8dbe85 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_17a474 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_5a18b3 : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -2118,6 +2586,14 @@ class Enc_12b6e9 : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } +class Enc_9a895f : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_6f70ca : OpcodeHexagon { bits <8> Ii; let Inst{8-4} = Ii{7-3}; @@ -2130,6 +2606,12 @@ class Enc_7222b7 : OpcodeHexagon { } class Enc_e3b0c4 : OpcodeHexagon { } +class Enc_d7e8ba : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_a255dc : OpcodeHexagon { bits <3> Ii; let Inst{10-8} = Ii{2-0}; @@ -2138,6 +2620,24 @@ class Enc_a255dc : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_cb785b : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_5b76ab : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-8} = Ii{8-3}; + let Inst{2-0} = Ii{2-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_cb4b4e : OpcodeHexagon { bits <2> Pu4; let Inst{6-5} = Pu4{1-0}; @@ -2148,6 +2648,24 @@ class Enc_cb4b4e : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } +class Enc_fbacc2 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_2ad23d : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} class Enc_9cdba7 : OpcodeHexagon { bits <8> Ii; let Inst{12-5} = Ii{7-0}; @@ -2165,6 +2683,10 @@ class Enc_5cd7e9 : OpcodeHexagon { bits <5> Ryy32; let Inst{4-0} = Ryy32{4-0}; } +class Enc_e7c9de : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; +} class Enc_454a26 : OpcodeHexagon { bits <2> Pt4; let Inst{9-8} = Pt4{1-0}; @@ -2193,6 +2715,16 @@ class Enc_c175d0 : OpcodeHexagon { bits <4> Rd16; let Inst{3-0} = Rd16{3-0}; } +class Enc_16c48b : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} class Enc_895bd9 : OpcodeHexagon { bits <2> Qu4; let Inst{9-8} = Qu4{1-0}; @@ -2254,6 +2786,14 @@ class Enc_d2c7f1 : OpcodeHexagon { bits <2> Pe4; let Inst{6-5} = Pe4{1-0}; } +class Enc_dcfcbb : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_3680c2 : OpcodeHexagon { bits <7> Ii; let Inst{11-5} = Ii{6-0}; @@ -2282,6 +2822,32 @@ class Enc_e957fb : OpcodeHexagon { bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; } +class Enc_2146c1 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <3> Qss8; + let Inst{2-0} = Qss8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_a662ae : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_8f7cc3 : OpcodeHexagon { + bits <3> Qtt8; + let Inst{10-8} = Qtt8{2-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; +} class Enc_c9e3bc : OpcodeHexagon { bits <4> Ii; let Inst{13-13} = Ii{3-3}; @@ -2314,6 +2880,40 @@ class Enc_0b2e5b : OpcodeHexagon { bits <5> Vd32; let Inst{4-0} = Vd32{4-0}; } +class Enc_6f83e7 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_46f33d : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_c1652e : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_b5b643 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_85daf5 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} class Enc_d483b9 : OpcodeHexagon { bits <1> Ii; let Inst{5-5} = Ii{0-0}; @@ -2346,6 +2946,26 @@ class Enc_70fb07 : OpcodeHexagon { bits <5> Rxx32; let Inst{4-0} = Rxx32{4-0}; } +class Enc_6c9ee0 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_72a92d : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} +class Enc_44661f : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_277737 : OpcodeHexagon { bits <8> Ii; let Inst{22-21} = Ii{7-6}; @@ -2496,6 +3116,14 @@ class Enc_8e583a : OpcodeHexagon { let Inst{25-23} = n1{3-1}; let Inst{13-13} = n1{0-0}; } +class Enc_334c2b : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_b886fd : OpcodeHexagon { bits <5> Ii; let Inst{6-3} = Ii{4-1}; @@ -2549,12 +3177,36 @@ class Enc_8dbdfe : OpcodeHexagon { bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } +class Enc_7dc746 : OpcodeHexagon { + bits <3> Quu8; + let Inst{10-8} = Quu8{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; +} class Enc_90cd8b : OpcodeHexagon { bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_b8513b : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_b3bac4 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} class Enc_bd0b33 : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; @@ -2564,6 +3216,24 @@ class Enc_bd0b33 : OpcodeHexagon { bits <2> Pd4; let Inst{1-0} = Pd4{1-0}; } +class Enc_843e80 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <3> Qxx8; + let Inst{2-0} = Qxx8{2-0}; +} +class Enc_8b8927 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; +} class Enc_c7cd90 : OpcodeHexagon { bits <4> Ii; let Inst{6-3} = Ii{3-0}; @@ -2711,15 +3381,24 @@ class Enc_1a9974 : OpcodeHexagon { bits <5> Rtt32; let Inst{4-0} = Rtt32{4-0}; } -class Enc_1de724 : OpcodeHexagon { +class Enc_9ce456 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-8} = Ii{8-3}; + let Inst{2-0} = Ii{2-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_5de85f : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> n1; - let Inst{28-28} = n1{3-3}; - let Inst{24-22} = n1{2-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; } class Enc_dd766a : OpcodeHexagon { bits <5> Vu32; @@ -2737,6 +3416,14 @@ class Enc_0b51ce : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_b5e54d : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} class Enc_b4e6cf : OpcodeHexagon { bits <10> Ii; let Inst{21-21} = Ii{9-9}; @@ -2755,6 +3442,12 @@ class Enc_44215c : OpcodeHexagon { bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; } +class Enc_0aa344 : OpcodeHexagon { + bits <5> Gss32; + let Inst{20-16} = Gss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} class Enc_a21d47 : OpcodeHexagon { bits <6> Ii; let Inst{10-5} = Ii{5-0}; @@ -2786,6 +3479,16 @@ class Enc_645d54 : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } +class Enc_b5d5a7 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; +} class Enc_667b39 : OpcodeHexagon { bits <5> Css32; let Inst{20-16} = Css32{4-0}; @@ -2843,6 +3546,16 @@ class Enc_b8c967 : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_f106e0 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{8-4} = Vv32{4-0}; + bits <5> Vt32; + let Inst{13-9} = Vt32{4-0}; + bits <4> Vdd16; + let Inst{3-0} = Vdd16{3-0}; +} class Enc_fb6577 : OpcodeHexagon { bits <2> Pu4; let Inst{9-8} = Pu4{1-0}; @@ -2851,6 +3564,20 @@ class Enc_fb6577 : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_37c406 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <4> Vdd16; + let Inst{7-4} = Vdd16{3-0}; +} +class Enc_403871 : OpcodeHexagon { + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_2bae10 : OpcodeHexagon { bits <4> Ii; let Inst{10-8} = Ii{3-1}; @@ -2859,6 +3586,22 @@ class Enc_2bae10 : OpcodeHexagon { bits <4> Rd16; let Inst{3-0} = Rd16{3-0}; } +class Enc_f3adb6 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_aac08c : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} class Enc_c4dc92 : OpcodeHexagon { bits <2> Qv4; let Inst{23-22} = Qv4{1-0}; @@ -3000,6 +3743,13 @@ class Enc_134437 : OpcodeHexagon { bits <2> Qd4; let Inst{1-0} = Qd4{1-0}; } +class Enc_33f8ba : OpcodeHexagon { + bits <8> Ii; + let Inst{12-8} = Ii{7-3}; + let Inst{4-2} = Ii{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_97d666 : OpcodeHexagon { bits <4> Rs16; let Inst{7-4} = Rs16{3-0}; @@ -3016,6 +3766,16 @@ class Enc_f82eaf : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_57e245 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} class Enc_69d63b : OpcodeHexagon { bits <11> Ii; let Inst{21-20} = Ii{10-9}; @@ -3082,6 +3842,24 @@ class Enc_7eaeb6 : OpcodeHexagon { bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } +class Enc_274a4c : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_aceeef : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_f55a0c : OpcodeHexagon { bits <6> Ii; let Inst{11-8} = Ii{5-2}; @@ -3120,6 +3898,16 @@ class Enc_7b523d : OpcodeHexagon { bits <5> Vxx32; let Inst{4-0} = Vxx32{4-0}; } +class Enc_c39a8b : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; +} class Enc_47ef61 : OpcodeHexagon { bits <3> Ii; let Inst{7-5} = Ii{2-0}; @@ -3229,6 +4017,16 @@ class Enc_eca7c8 : OpcodeHexagon { bits <5> Rt32; let Inst{4-0} = Rt32{4-0}; } +class Enc_598f6c : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_41dcc3 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} class Enc_4b39e4 : OpcodeHexagon { bits <3> Ii; let Inst{7-5} = Ii{2-0}; diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td index e42229fd57a..6e16762ac0e 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -1,4 +1,4 @@ -//===--- HexagonDepInstrInfo.td -------------------------------------------===// +//===- HexagonDepInstrInfo.td ---------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,12 +6,15 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + def A2_abs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = abs($Rs32)", -tc_94e6ffd9, TypeS_2op>, Enc_5e2823 { +tc_c2f7d806, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -22,7 +25,7 @@ def A2_absp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = abs($Rss32)", -tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb { +tc_c2f7d806, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000100; let prefersSlot3 = 1; @@ -31,7 +34,7 @@ def A2_abssat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = abs($Rs32):sat", -tc_94e6ffd9, TypeS_2op>, Enc_5e2823 { +tc_c2f7d806, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -43,7 +46,7 @@ def A2_add : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add($Rs32,$Rt32)", -tc_548f402d, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { +tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011000; @@ -59,7 +62,7 @@ def A2_addh_h16_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.h):<<16", -tc_bd16579e, TypeALU64>, Enc_bd6011 { +tc_897d1a9d, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -71,7 +74,7 @@ def A2_addh_h16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.l):<<16", -tc_bd16579e, TypeALU64>, Enc_bd6011 { +tc_897d1a9d, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -83,7 +86,7 @@ def A2_addh_h16_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h):<<16", -tc_bd16579e, TypeALU64>, Enc_bd6011 { +tc_897d1a9d, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -95,7 +98,7 @@ def A2_addh_h16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l):<<16", -tc_bd16579e, TypeALU64>, Enc_bd6011 { +tc_897d1a9d, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -107,7 +110,7 @@ def A2_addh_h16_sat_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -120,7 +123,7 @@ def A2_addh_h16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -133,7 +136,7 @@ def A2_addh_h16_sat_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -146,7 +149,7 @@ def A2_addh_h16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -159,7 +162,7 @@ def A2_addh_l16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h)", -tc_7ca2ea10, TypeALU64>, Enc_bd6011 { +tc_1b9c9ee5, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -171,7 +174,7 @@ def A2_addh_l16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l)", -tc_7ca2ea10, TypeALU64>, Enc_bd6011 { +tc_1b9c9ee5, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -183,7 +186,7 @@ def A2_addh_l16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h):sat", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -196,7 +199,7 @@ def A2_addh_l16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l):sat", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -209,7 +212,7 @@ def A2_addi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = add($Rs32,#$Ii)", -tc_548f402d, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel { +tc_b9488031, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel { let Inst{31-28} = 0b1011; let hasNewValue = 1; let opNewValue = 0; @@ -228,7 +231,7 @@ def A2_addp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32)", -tc_9c18c9a5, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -239,7 +242,7 @@ def A2_addpsat : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32):sat", -tc_47ab9233, TypeALU64>, Enc_a56825 { +tc_b44c6e2a, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -251,7 +254,7 @@ def A2_addsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add($Rs32,$Rt32):sat", -tc_b0f50e3c, TypeALU32_3op>, Enc_5ab2be { +tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110010; @@ -266,14 +269,14 @@ def A2_addsp : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rs32,$Rtt32)", -tc_bd16579e, TypeALU64> { +tc_897d1a9d, TypeALU64> { let isPseudo = 1; } def A2_addsph : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32):raw:hi", -tc_bd16579e, TypeALU64>, Enc_a56825 { +tc_897d1a9d, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -283,7 +286,7 @@ def A2_addspl : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32):raw:lo", -tc_bd16579e, TypeALU64>, Enc_a56825 { +tc_897d1a9d, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -293,7 +296,7 @@ def A2_and : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = and($Rs32,$Rt32)", -tc_548f402d, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { +tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001000; @@ -309,7 +312,7 @@ def A2_andir : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = and($Rs32,#$Ii)", -tc_548f402d, TypeALU32_2op>, Enc_140c83, ImmRegRel { +tc_b9488031, TypeALU32_2op>, Enc_140c83, ImmRegRel { let Inst{31-22} = 0b0111011000; let hasNewValue = 1; let opNewValue = 0; @@ -325,7 +328,7 @@ def A2_andp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = and($Rss32,$Rtt32)", -tc_9c18c9a5, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -335,7 +338,7 @@ def A2_aslh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = aslh($Rs32)", -tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000000; let hasNewValue = 1; @@ -347,7 +350,7 @@ def A2_asrh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = asrh($Rs32)", -tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000001; let hasNewValue = 1; @@ -359,7 +362,7 @@ def A2_combine_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.h,$Rs32.h)", -tc_548f402d, TypeALU32_3op>, Enc_bd6011 { +tc_b9488031, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011100; @@ -371,7 +374,7 @@ def A2_combine_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.h,$Rs32.l)", -tc_548f402d, TypeALU32_3op>, Enc_bd6011 { +tc_b9488031, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011101; @@ -383,7 +386,7 @@ def A2_combine_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.l,$Rs32.h)", -tc_548f402d, TypeALU32_3op>, Enc_bd6011 { +tc_b9488031, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011110; @@ -395,7 +398,7 @@ def A2_combine_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.l,$Rs32.l)", -tc_548f402d, TypeALU32_3op>, Enc_bd6011 { +tc_b9488031, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011111; @@ -407,7 +410,7 @@ def A2_combineii : HInst< (outs DoubleRegs:$Rdd32), (ins s32_0Imm:$Ii, s8_0Imm:$II), "$Rdd32 = combine(#$Ii,#$II)", -tc_548f402d, TypeALU32_2op>, Enc_18c338 { +tc_b9488031, TypeALU32_2op>, Enc_18c338 { let Inst{31-23} = 0b011111000; let isReMaterializable = 1; let isAsCheapAsAMove = 1; @@ -422,7 +425,7 @@ def A2_combinew : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = combine($Rs32,$Rt32)", -tc_548f402d, TypeALU32_3op>, Enc_be32a5, PredNewRel { +tc_b9488031, TypeALU32_3op>, Enc_be32a5, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110101000; @@ -434,7 +437,7 @@ def A2_max : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = max($Rs32,$Rt32)", -tc_47ab9233, TypeALU64>, Enc_5ab2be { +tc_b44c6e2a, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101110; @@ -446,7 +449,7 @@ def A2_maxp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = max($Rss32,$Rtt32)", -tc_47ab9233, TypeALU64>, Enc_a56825 { +tc_b44c6e2a, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -456,7 +459,7 @@ def A2_maxu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = maxu($Rs32,$Rt32)", -tc_47ab9233, TypeALU64>, Enc_5ab2be { +tc_b44c6e2a, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101110; @@ -468,7 +471,7 @@ def A2_maxup : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = maxu($Rss32,$Rtt32)", -tc_47ab9233, TypeALU64>, Enc_a56825 { +tc_b44c6e2a, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -478,7 +481,7 @@ def A2_min : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = min($Rt32,$Rs32)", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101101; @@ -490,7 +493,7 @@ def A2_minp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = min($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -500,7 +503,7 @@ def A2_minu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = minu($Rt32,$Rs32)", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101101; @@ -512,7 +515,7 @@ def A2_minup : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = minu($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -522,7 +525,7 @@ def A2_neg : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = neg($Rs32)", -tc_f16d5b17, TypeALU32_2op> { +tc_68cb12ce, TypeALU32_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -532,7 +535,7 @@ def A2_negp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = neg($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb { +tc_cde8b071, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000100; } @@ -540,7 +543,7 @@ def A2_negsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = neg($Rs32):sat", -tc_94e6ffd9, TypeS_2op>, Enc_5e2823 { +tc_c2f7d806, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -552,7 +555,7 @@ def A2_nop : HInst< (outs), (ins), "nop", -tc_e2c31426, TypeALU32_2op>, Enc_e3b0c4 { +tc_6efc556e, TypeALU32_2op>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b0111111100000000; } @@ -560,7 +563,7 @@ def A2_not : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = not($Rs32)", -tc_f16d5b17, TypeALU32_2op> { +tc_68cb12ce, TypeALU32_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -570,7 +573,7 @@ def A2_notp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = not($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb { +tc_cde8b071, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000100; } @@ -578,7 +581,7 @@ def A2_or : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = or($Rs32,$Rt32)", -tc_548f402d, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { +tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001001; @@ -594,7 +597,7 @@ def A2_orir : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = or($Rs32,#$Ii)", -tc_548f402d, TypeALU32_2op>, Enc_140c83, ImmRegRel { +tc_b9488031, TypeALU32_2op>, Enc_140c83, ImmRegRel { let Inst{31-22} = 0b0111011010; let hasNewValue = 1; let opNewValue = 0; @@ -610,7 +613,7 @@ def A2_orp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = or($Rss32,$Rtt32)", -tc_9c18c9a5, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -620,7 +623,7 @@ def A2_paddf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = add($Rs32,$Rt32)", -tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011000; @@ -636,7 +639,7 @@ def A2_paddfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)", -tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011000; @@ -653,7 +656,7 @@ def A2_paddif : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if (!$Pu4) $Rd32 = add($Rs32,#$Ii)", -tc_1b6011fb, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011101001; let isPredicated = 1; @@ -673,7 +676,7 @@ def A2_paddifnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)", -tc_28d296df, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_2b2f4060, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-23} = 0b011101001; let isPredicated = 1; @@ -694,7 +697,7 @@ def A2_paddit : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if ($Pu4) $Rd32 = add($Rs32,#$Ii)", -tc_1b6011fb, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011101000; let isPredicated = 1; @@ -713,7 +716,7 @@ def A2_padditnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)", -tc_28d296df, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_2b2f4060, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-23} = 0b011101000; let isPredicated = 1; @@ -733,7 +736,7 @@ def A2_paddt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = add($Rs32,$Rt32)", -tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011000; @@ -748,7 +751,7 @@ def A2_paddtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)", -tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011000; @@ -764,7 +767,7 @@ def A2_pandf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = and($Rs32,$Rt32)", -tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001000; @@ -778,7 +781,7 @@ def A2_pandfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)", -tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001000; @@ -793,7 +796,7 @@ def A2_pandt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = and($Rs32,$Rt32)", -tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001000; @@ -806,7 +809,7 @@ def A2_pandtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)", -tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001000; @@ -820,7 +823,7 @@ def A2_porf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = or($Rs32,$Rt32)", -tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001001; @@ -834,7 +837,7 @@ def A2_porfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)", -tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001001; @@ -849,7 +852,7 @@ def A2_port : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = or($Rs32,$Rt32)", -tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001001; @@ -862,7 +865,7 @@ def A2_portnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)", -tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001001; @@ -876,7 +879,7 @@ def A2_psubf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)", -tc_1b6011fb, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_d6bf0472, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011001; @@ -890,7 +893,7 @@ def A2_psubfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)", -tc_28d296df, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_2b2f4060, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011001; @@ -905,7 +908,7 @@ def A2_psubt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if ($Pu4) $Rd32 = sub($Rt32,$Rs32)", -tc_1b6011fb, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_d6bf0472, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011001; @@ -918,7 +921,7 @@ def A2_psubtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)", -tc_28d296df, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_2b2f4060, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011001; @@ -932,7 +935,7 @@ def A2_pxorf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)", -tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001011; @@ -946,7 +949,7 @@ def A2_pxorfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)", -tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001011; @@ -961,7 +964,7 @@ def A2_pxort : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = xor($Rs32,$Rt32)", -tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001011; @@ -974,7 +977,7 @@ def A2_pxortnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)", -tc_28d296df, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_2b2f4060, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001011; @@ -988,7 +991,7 @@ def A2_roundsat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = round($Rss32):sat", -tc_94e6ffd9, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_c2f7d806, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000110; let hasNewValue = 1; @@ -1000,7 +1003,7 @@ def A2_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = sat($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_90cd8b { +tc_cde8b071, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000110; let hasNewValue = 1; @@ -1011,7 +1014,7 @@ def A2_satb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = satb($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_5e2823 { +tc_cde8b071, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1022,7 +1025,7 @@ def A2_sath : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sath($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_5e2823 { +tc_cde8b071, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1033,7 +1036,7 @@ def A2_satub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = satub($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_5e2823 { +tc_cde8b071, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1044,7 +1047,7 @@ def A2_satuh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = satuh($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_5e2823 { +tc_cde8b071, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1055,7 +1058,7 @@ def A2_sub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32,$Rs32)", -tc_548f402d, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel { +tc_b9488031, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011001; @@ -1070,7 +1073,7 @@ def A2_subh_h16_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.h):<<16", -tc_bd16579e, TypeALU64>, Enc_bd6011 { +tc_897d1a9d, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1082,7 +1085,7 @@ def A2_subh_h16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.l):<<16", -tc_bd16579e, TypeALU64>, Enc_bd6011 { +tc_897d1a9d, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1094,7 +1097,7 @@ def A2_subh_h16_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h):<<16", -tc_bd16579e, TypeALU64>, Enc_bd6011 { +tc_897d1a9d, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1106,7 +1109,7 @@ def A2_subh_h16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l):<<16", -tc_bd16579e, TypeALU64>, Enc_bd6011 { +tc_897d1a9d, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1118,7 +1121,7 @@ def A2_subh_h16_sat_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1131,7 +1134,7 @@ def A2_subh_h16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1144,7 +1147,7 @@ def A2_subh_h16_sat_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1157,7 +1160,7 @@ def A2_subh_h16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1170,7 +1173,7 @@ def A2_subh_l16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h)", -tc_7ca2ea10, TypeALU64>, Enc_bd6011 { +tc_1b9c9ee5, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1182,7 +1185,7 @@ def A2_subh_l16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l)", -tc_7ca2ea10, TypeALU64>, Enc_bd6011 { +tc_1b9c9ee5, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1194,7 +1197,7 @@ def A2_subh_l16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h):sat", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1207,7 +1210,7 @@ def A2_subh_l16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l):sat", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1220,7 +1223,7 @@ def A2_subp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = sub($Rtt32,$Rss32)", -tc_9c18c9a5, TypeALU64>, Enc_ea23e4 { +tc_540fdfbc, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -1229,7 +1232,7 @@ def A2_subri : HInst< (outs IntRegs:$Rd32), (ins s32_0Imm:$Ii, IntRegs:$Rs32), "$Rd32 = sub(#$Ii,$Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel { +tc_b9488031, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel { let Inst{31-22} = 0b0111011001; let hasNewValue = 1; let opNewValue = 0; @@ -1245,7 +1248,7 @@ def A2_subsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32,$Rs32):sat", -tc_b0f50e3c, TypeALU32_3op>, Enc_bd6011 { +tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110110; @@ -1259,7 +1262,7 @@ def A2_svaddh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vaddh($Rs32,$Rt32)", -tc_548f402d, TypeALU32_3op>, Enc_5ab2be { +tc_b9488031, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110000; @@ -1272,7 +1275,7 @@ def A2_svaddhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vaddh($Rs32,$Rt32):sat", -tc_b0f50e3c, TypeALU32_3op>, Enc_5ab2be { +tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110001; @@ -1287,7 +1290,7 @@ def A2_svadduhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vadduh($Rs32,$Rt32):sat", -tc_b0f50e3c, TypeALU32_3op>, Enc_5ab2be { +tc_5ba5997d, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110011; @@ -1302,13 +1305,12 @@ def A2_svavgh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vavgh($Rs32,$Rt32)", -tc_511f28f6, TypeALU32_3op>, Enc_5ab2be { +tc_b9488031, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110111000; let hasNewValue = 1; let opNewValue = 0; -let prefersSlot3 = 1; let InputType = "reg"; let isCommutable = 1; } @@ -1316,13 +1318,12 @@ def A2_svavghs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vavgh($Rs32,$Rt32):rnd", -tc_76c4c5ef, TypeALU32_3op>, Enc_5ab2be { +tc_8fe6b782, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110111001; let hasNewValue = 1; let opNewValue = 0; -let prefersSlot3 = 1; let InputType = "reg"; let isCommutable = 1; } @@ -1330,20 +1331,19 @@ def A2_svnavgh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vnavgh($Rt32,$Rs32)", -tc_511f28f6, TypeALU32_3op>, Enc_bd6011 { +tc_b9488031, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110111011; let hasNewValue = 1; let opNewValue = 0; -let prefersSlot3 = 1; let InputType = "reg"; } def A2_svsubh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vsubh($Rt32,$Rs32)", -tc_548f402d, TypeALU32_3op>, Enc_bd6011 { +tc_b9488031, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110100; @@ -1355,7 +1355,7 @@ def A2_svsubhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vsubh($Rt32,$Rs32):sat", -tc_b0f50e3c, TypeALU32_3op>, Enc_bd6011 { +tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110101; @@ -1369,7 +1369,7 @@ def A2_svsubuhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vsubuh($Rt32,$Rs32):sat", -tc_b0f50e3c, TypeALU32_3op>, Enc_bd6011 { +tc_5ba5997d, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110111; @@ -1383,7 +1383,7 @@ def A2_swiz : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = swiz($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_5e2823 { +tc_cde8b071, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -1393,7 +1393,7 @@ def A2_sxtb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sxtb($Rs32)", -tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000101; let hasNewValue = 1; @@ -1405,7 +1405,7 @@ def A2_sxth : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sxth($Rs32)", -tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000111; let hasNewValue = 1; @@ -1417,7 +1417,7 @@ def A2_sxtw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = sxtw($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 { +tc_cde8b071, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100010; } @@ -1425,7 +1425,7 @@ def A2_tfr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = $Rs32", -tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000011; let hasNewValue = 1; @@ -1438,7 +1438,7 @@ def A2_tfrcrr : HInst< (outs IntRegs:$Rd32), (ins CtrRegs:$Cs32), "$Rd32 = $Cs32", -tc_3b4892c6, TypeCR>, Enc_0cb018 { +tc_29175780, TypeCR>, Enc_0cb018 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01101010000; let hasNewValue = 1; @@ -1448,7 +1448,7 @@ def A2_tfrf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = $Rs32", -tc_1b6011fb, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_d6bf0472, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; @@ -1463,7 +1463,7 @@ def A2_tfrfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = $Rs32", -tc_28d296df, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_2b2f4060, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; @@ -1479,7 +1479,7 @@ def A2_tfrih : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, u16_0Imm:$Ii), "$Rx32.h = #$Ii", -tc_548f402d, TypeALU32_2op>, Enc_51436c { +tc_b9488031, TypeALU32_2op>, Enc_51436c { let Inst{21-21} = 0b1; let Inst{31-24} = 0b01110010; let hasNewValue = 1; @@ -1490,7 +1490,7 @@ def A2_tfril : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, u16_0Imm:$Ii), "$Rx32.l = #$Ii", -tc_548f402d, TypeALU32_2op>, Enc_51436c { +tc_b9488031, TypeALU32_2op>, Enc_51436c { let Inst{21-21} = 0b1; let Inst{31-24} = 0b01110001; let hasNewValue = 1; @@ -1501,7 +1501,7 @@ def A2_tfrp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = $Rss32", -tc_548f402d, TypeALU32_2op>, PredNewRel { +tc_b9488031, TypeALU32_2op>, PredNewRel { let BaseOpcode = "A2_tfrp"; let isPredicable = 1; let isPseudo = 1; @@ -1510,7 +1510,7 @@ def A2_tfrpf : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if (!$Pu4) $Rdd32 = $Rss32", -tc_548f402d, TypeALU32_2op>, PredNewRel { +tc_b9488031, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let isPredicatedFalse = 1; let BaseOpcode = "A2_tfrp"; @@ -1520,7 +1520,7 @@ def A2_tfrpfnew : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if (!$Pu4.new) $Rdd32 = $Rss32", -tc_b08be45e, TypeALU32_2op>, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let isPredicatedFalse = 1; let isPredicatedNew = 1; @@ -1531,7 +1531,7 @@ def A2_tfrpi : HInst< (outs DoubleRegs:$Rdd32), (ins s8_0Imm:$Ii), "$Rdd32 = #$Ii", -tc_548f402d, TypeALU64> { +tc_b9488031, TypeALU64> { let isReMaterializable = 1; let isAsCheapAsAMove = 1; let isMoveImm = 1; @@ -1541,7 +1541,7 @@ def A2_tfrpt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if ($Pu4) $Rdd32 = $Rss32", -tc_548f402d, TypeALU32_2op>, PredNewRel { +tc_b9488031, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let BaseOpcode = "A2_tfrp"; let isPseudo = 1; @@ -1550,7 +1550,7 @@ def A2_tfrptnew : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if ($Pu4.new) $Rdd32 = $Rss32", -tc_b08be45e, TypeALU32_2op>, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let isPredicatedNew = 1; let BaseOpcode = "A2_tfrp"; @@ -1560,7 +1560,7 @@ def A2_tfrrcr : HInst< (outs CtrRegs:$Cd32), (ins IntRegs:$Rs32), "$Cd32 = $Rs32", -tc_82f0f122, TypeCR>, Enc_bd811a { +tc_a21dc435, TypeCR>, Enc_bd811a { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01100010001; let hasNewValue = 1; @@ -1570,7 +1570,7 @@ def A2_tfrsi : HInst< (outs IntRegs:$Rd32), (ins s32_0Imm:$Ii), "$Rd32 = #$Ii", -tc_f16d5b17, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel { +tc_68cb12ce, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel { let Inst{21-21} = 0b0; let Inst{31-24} = 0b01111000; let hasNewValue = 1; @@ -1592,7 +1592,7 @@ def A2_tfrt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = $Rs32", -tc_1b6011fb, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_d6bf0472, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; @@ -1606,7 +1606,7 @@ def A2_tfrtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = $Rs32", -tc_28d296df, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_2b2f4060, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; @@ -1621,7 +1621,7 @@ def A2_vabsh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsh($Rss32)", -tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb { +tc_c2f7d806, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1630,7 +1630,7 @@ def A2_vabshsat : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsh($Rss32):sat", -tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb { +tc_c2f7d806, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1640,7 +1640,7 @@ def A2_vabsw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsw($Rss32)", -tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb { +tc_c2f7d806, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1649,7 +1649,7 @@ def A2_vabswsat : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsw($Rss32):sat", -tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb { +tc_c2f7d806, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1659,7 +1659,7 @@ def A2_vaddb_map : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddb($Rss32,$Rtt32)", -tc_9c18c9a5, TypeMAPPING> { +tc_540fdfbc, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1667,7 +1667,7 @@ def A2_vaddh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddh($Rss32,$Rtt32)", -tc_9c18c9a5, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1676,7 +1676,7 @@ def A2_vaddhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddh($Rss32,$Rtt32):sat", -tc_47ab9233, TypeALU64>, Enc_a56825 { +tc_b44c6e2a, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1687,7 +1687,7 @@ def A2_vaddub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddub($Rss32,$Rtt32)", -tc_9c18c9a5, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1696,7 +1696,7 @@ def A2_vaddubs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddub($Rss32,$Rtt32):sat", -tc_47ab9233, TypeALU64>, Enc_a56825 { +tc_b44c6e2a, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1707,7 +1707,7 @@ def A2_vadduhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vadduh($Rss32,$Rtt32):sat", -tc_47ab9233, TypeALU64>, Enc_a56825 { +tc_b44c6e2a, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1718,7 +1718,7 @@ def A2_vaddw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddw($Rss32,$Rtt32)", -tc_9c18c9a5, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1727,7 +1727,7 @@ def A2_vaddws : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddw($Rss32,$Rtt32):sat", -tc_47ab9233, TypeALU64>, Enc_a56825 { +tc_b44c6e2a, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1738,17 +1738,16 @@ def A2_vavgh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgh($Rss32,$Rtt32)", -tc_cd321066, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; -let prefersSlot3 = 1; } def A2_vavghcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgh($Rss32,$Rtt32):crnd", -tc_63cd9d2d, TypeALU64>, Enc_a56825 { +tc_2b6f77c6, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1758,87 +1757,79 @@ def A2_vavghr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgh($Rss32,$Rtt32):rnd", -tc_37326008, TypeALU64>, Enc_a56825 { +tc_dbdffe3d, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; -let prefersSlot3 = 1; } def A2_vavgub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgub($Rss32,$Rtt32)", -tc_cd321066, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; -let prefersSlot3 = 1; } def A2_vavgubr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgub($Rss32,$Rtt32):rnd", -tc_37326008, TypeALU64>, Enc_a56825 { +tc_dbdffe3d, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; -let prefersSlot3 = 1; } def A2_vavguh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguh($Rss32,$Rtt32)", -tc_cd321066, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; -let prefersSlot3 = 1; } def A2_vavguhr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguh($Rss32,$Rtt32):rnd", -tc_37326008, TypeALU64>, Enc_a56825 { +tc_dbdffe3d, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; -let prefersSlot3 = 1; } def A2_vavguw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguw($Rss32,$Rtt32)", -tc_cd321066, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; -let prefersSlot3 = 1; } def A2_vavguwr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguw($Rss32,$Rtt32):rnd", -tc_37326008, TypeALU64>, Enc_a56825 { +tc_dbdffe3d, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; -let prefersSlot3 = 1; } def A2_vavgw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgw($Rss32,$Rtt32)", -tc_cd321066, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; -let prefersSlot3 = 1; } def A2_vavgwcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgw($Rss32,$Rtt32):crnd", -tc_63cd9d2d, TypeALU64>, Enc_a56825 { +tc_2b6f77c6, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -1848,17 +1839,16 @@ def A2_vavgwr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgw($Rss32,$Rtt32):rnd", -tc_37326008, TypeALU64>, Enc_a56825 { +tc_dbdffe3d, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; -let prefersSlot3 = 1; } def A2_vcmpbeq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpb.eq($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b110000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1867,7 +1857,7 @@ def A2_vcmpbgtu : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpb.gtu($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b111000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1876,7 +1866,7 @@ def A2_vcmpheq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmph.eq($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1885,7 +1875,7 @@ def A2_vcmphgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmph.gt($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1894,7 +1884,7 @@ def A2_vcmphgtu : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmph.gtu($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1903,7 +1893,7 @@ def A2_vcmpweq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpw.eq($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1912,7 +1902,7 @@ def A2_vcmpwgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpw.gt($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1921,7 +1911,7 @@ def A2_vcmpwgtu : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpw.gtu($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1930,7 +1920,7 @@ def A2_vconj : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vconj($Rss32):sat", -tc_94e6ffd9, TypeS_2op>, Enc_b9c5fb { +tc_c2f7d806, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000100; let prefersSlot3 = 1; @@ -1940,7 +1930,7 @@ def A2_vmaxb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxb($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1950,7 +1940,7 @@ def A2_vmaxh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxh($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1960,7 +1950,7 @@ def A2_vmaxub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxub($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1970,7 +1960,7 @@ def A2_vmaxuh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxuh($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1980,7 +1970,7 @@ def A2_vmaxuw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxuw($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -1990,7 +1980,7 @@ def A2_vmaxw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxw($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -2000,7 +1990,7 @@ def A2_vminb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminb($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -2010,7 +2000,7 @@ def A2_vminh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminh($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2020,7 +2010,7 @@ def A2_vminub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminub($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2030,7 +2020,7 @@ def A2_vminuh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminuh($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2040,7 +2030,7 @@ def A2_vminuw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminuw($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2050,7 +2040,7 @@ def A2_vminw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminw($Rtt32,$Rss32)", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2060,17 +2050,16 @@ def A2_vnavgh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgh($Rtt32,$Rss32)", -tc_cd321066, TypeALU64>, Enc_ea23e4 { +tc_540fdfbc, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; -let prefersSlot3 = 1; } def A2_vnavghcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat", -tc_63cd9d2d, TypeALU64>, Enc_ea23e4 { +tc_2b6f77c6, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2081,7 +2070,7 @@ def A2_vnavghr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat", -tc_63cd9d2d, TypeALU64>, Enc_ea23e4 { +tc_2b6f77c6, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2092,17 +2081,16 @@ def A2_vnavgw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgw($Rtt32,$Rss32)", -tc_cd321066, TypeALU64>, Enc_ea23e4 { +tc_540fdfbc, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; -let prefersSlot3 = 1; } def A2_vnavgwcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat", -tc_63cd9d2d, TypeALU64>, Enc_ea23e4 { +tc_2b6f77c6, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2113,7 +2101,7 @@ def A2_vnavgwr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat", -tc_63cd9d2d, TypeALU64>, Enc_ea23e4 { +tc_2b6f77c6, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2124,7 +2112,7 @@ def A2_vraddub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vraddub($Rss32,$Rtt32)", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -2134,7 +2122,7 @@ def A2_vraddub_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vraddub($Rss32,$Rtt32)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -2145,7 +2133,7 @@ def A2_vrsadub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrsadub($Rss32,$Rtt32)", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -2155,7 +2143,7 @@ def A2_vrsadub_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrsadub($Rss32,$Rtt32)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -2166,7 +2154,7 @@ def A2_vsubb_map : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vsubb($Rss32,$Rtt32)", -tc_9c18c9a5, TypeMAPPING> { +tc_540fdfbc, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -2174,7 +2162,7 @@ def A2_vsubh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubh($Rtt32,$Rss32)", -tc_9c18c9a5, TypeALU64>, Enc_ea23e4 { +tc_540fdfbc, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2183,7 +2171,7 @@ def A2_vsubhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubh($Rtt32,$Rss32):sat", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2194,7 +2182,7 @@ def A2_vsubub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubub($Rtt32,$Rss32)", -tc_9c18c9a5, TypeALU64>, Enc_ea23e4 { +tc_540fdfbc, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2203,7 +2191,7 @@ def A2_vsububs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubub($Rtt32,$Rss32):sat", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2214,7 +2202,7 @@ def A2_vsubuhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubuh($Rtt32,$Rss32):sat", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2225,7 +2213,7 @@ def A2_vsubw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubw($Rtt32,$Rss32)", -tc_9c18c9a5, TypeALU64>, Enc_ea23e4 { +tc_540fdfbc, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2234,7 +2222,7 @@ def A2_vsubws : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubw($Rtt32,$Rss32):sat", -tc_47ab9233, TypeALU64>, Enc_ea23e4 { +tc_b44c6e2a, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2245,7 +2233,7 @@ def A2_xor : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = xor($Rs32,$Rt32)", -tc_548f402d, TypeALU32_3op>, Enc_5ab2be, PredNewRel { +tc_b9488031, TypeALU32_3op>, Enc_5ab2be, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001011; @@ -2260,7 +2248,7 @@ def A2_xorp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = xor($Rss32,$Rtt32)", -tc_9c18c9a5, TypeALU64>, Enc_a56825 { +tc_540fdfbc, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2270,7 +2258,7 @@ def A2_zxtb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = zxtb($Rs32)", -tc_548f402d, TypeALU32_2op>, PredNewRel { +tc_b9488031, TypeALU32_2op>, PredNewRel { let hasNewValue = 1; let opNewValue = 0; let BaseOpcode = "A2_zxtb"; @@ -2282,7 +2270,7 @@ def A2_zxth : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = zxth($Rs32)", -tc_f16d5b17, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_68cb12ce, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000110; let hasNewValue = 1; @@ -2294,7 +2282,7 @@ def A4_addp_c : HInst< (outs DoubleRegs:$Rdd32, PredRegs:$Px4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), "$Rdd32 = add($Rss32,$Rtt32,$Px4):carry", -tc_a87879e8, TypeS_3op>, Enc_2b3f60 { +tc_523fcf30, TypeS_3op>, Enc_2b3f60 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010110; @@ -2305,7 +2293,7 @@ def A4_andn : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = and($Rt32,~$Rs32)", -tc_548f402d, TypeALU32_3op>, Enc_bd6011 { +tc_b9488031, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001100; @@ -2317,7 +2305,7 @@ def A4_andnp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = and($Rtt32,~$Rss32)", -tc_9c18c9a5, TypeALU64>, Enc_ea23e4 { +tc_540fdfbc, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2326,7 +2314,7 @@ def A4_bitsplit : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = bitsplit($Rs32,$Rt32)", -tc_7ca2ea10, TypeALU64>, Enc_be32a5 { +tc_1b9c9ee5, TypeALU64>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010100001; @@ -2336,7 +2324,7 @@ def A4_bitspliti : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rdd32 = bitsplit($Rs32,#$Ii)", -tc_7ca2ea10, TypeS_2op>, Enc_311abd { +tc_1b9c9ee5, TypeS_2op>, Enc_311abd { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001000110; @@ -2346,14 +2334,14 @@ def A4_boundscheck : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Pd4 = boundscheck($Rs32,$Rtt32)", -tc_c58f771a, TypeALU64> { +tc_1e856f58, TypeALU64> { let isPseudo = 1; } def A4_boundscheck_hi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -2362,7 +2350,7 @@ def A4_boundscheck_lo : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -2371,7 +2359,7 @@ def A4_cmpbeq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmpb.eq($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b110000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2384,7 +2372,7 @@ def A4_cmpbeqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u8_0Imm:$Ii), "$Pd4 = cmpb.eq($Rs32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_08d755, ImmRegRel { +tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101000; @@ -2397,7 +2385,7 @@ def A4_cmpbgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmpb.gt($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2409,7 +2397,7 @@ def A4_cmpbgti : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s8_0Imm:$Ii), "$Pd4 = cmpb.gt($Rs32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_08d755, ImmRegRel { +tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101001; @@ -2421,7 +2409,7 @@ def A4_cmpbgtu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmpb.gtu($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b111000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2433,7 +2421,7 @@ def A4_cmpbgtui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = cmpb.gtu($Rs32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_02553a, ImmRegRel { +tc_7a830544, TypeALU64>, Enc_02553a, ImmRegRel { let Inst{4-2} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011101010; @@ -2450,7 +2438,7 @@ def A4_cmpheq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmph.eq($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2463,7 +2451,7 @@ def A4_cmpheqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmph.eq($Rs32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_08d755, ImmRegRel { +tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101000; @@ -2481,7 +2469,7 @@ def A4_cmphgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmph.gt($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2493,7 +2481,7 @@ def A4_cmphgti : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmph.gt($Rs32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_08d755, ImmRegRel { +tc_7a830544, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101001; @@ -2510,7 +2498,7 @@ def A4_cmphgtu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmph.gtu($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2522,7 +2510,7 @@ def A4_cmphgtui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = cmph.gtu($Rs32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_02553a, ImmRegRel { +tc_7a830544, TypeALU64>, Enc_02553a, ImmRegRel { let Inst{4-2} = 0b010; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011101010; @@ -2539,7 +2527,7 @@ def A4_combineii : HInst< (outs DoubleRegs:$Rdd32), (ins s8_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = combine(#$Ii,#$II)", -tc_548f402d, TypeALU32_2op>, Enc_f0cca7 { +tc_b9488031, TypeALU32_2op>, Enc_f0cca7 { let Inst{31-21} = 0b01111100100; let isExtendable = 1; let opExtendable = 2; @@ -2551,7 +2539,7 @@ def A4_combineir : HInst< (outs DoubleRegs:$Rdd32), (ins s32_0Imm:$Ii, IntRegs:$Rs32), "$Rdd32 = combine(#$Ii,$Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_9cdba7 { +tc_b9488031, TypeALU32_2op>, Enc_9cdba7 { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011001; let isExtendable = 1; @@ -2564,7 +2552,7 @@ def A4_combineri : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rdd32 = combine($Rs32,#$Ii)", -tc_548f402d, TypeALU32_2op>, Enc_9cdba7 { +tc_b9488031, TypeALU32_2op>, Enc_9cdba7 { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011000; let isExtendable = 1; @@ -2577,7 +2565,7 @@ def A4_cround_ri : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = cround($Rs32,#$Ii)", -tc_63cd9d2d, TypeS_2op>, Enc_a05677 { +tc_2b6f77c6, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100111; @@ -2589,7 +2577,7 @@ def A4_cround_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cround($Rs32,$Rt32)", -tc_63cd9d2d, TypeS_3op>, Enc_5ab2be { +tc_2b6f77c6, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110110; @@ -2601,14 +2589,14 @@ def A4_ext : HInst< (outs), (ins u26_6Imm:$Ii), "immext(#$Ii)", -tc_9a13af9d, TypeEXTENDER>, Enc_2b518f { +tc_452f85af, TypeEXTENDER>, Enc_2b518f { let Inst{31-28} = 0b0000; } def A4_modwrapu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = modwrap($Rs32,$Rt32)", -tc_47ab9233, TypeALU64>, Enc_5ab2be { +tc_b44c6e2a, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2620,7 +2608,7 @@ def A4_orn : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = or($Rt32,~$Rs32)", -tc_548f402d, TypeALU32_3op>, Enc_bd6011 { +tc_b9488031, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001101; @@ -2632,7 +2620,7 @@ def A4_ornp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = or($Rtt32,~$Rss32)", -tc_9c18c9a5, TypeALU64>, Enc_ea23e4 { +tc_540fdfbc, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2641,7 +2629,7 @@ def A4_paslhf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = aslh($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000000; @@ -2655,7 +2643,7 @@ def A4_paslhfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = aslh($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000000; @@ -2670,7 +2658,7 @@ def A4_paslht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = aslh($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000000; @@ -2683,7 +2671,7 @@ def A4_paslhtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = aslh($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000000; @@ -2697,7 +2685,7 @@ def A4_pasrhf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = asrh($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000001; @@ -2711,7 +2699,7 @@ def A4_pasrhfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = asrh($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000001; @@ -2726,7 +2714,7 @@ def A4_pasrht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = asrh($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000001; @@ -2739,7 +2727,7 @@ def A4_pasrhtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = asrh($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000001; @@ -2753,7 +2741,7 @@ def A4_psxtbf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = sxtb($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000101; @@ -2767,7 +2755,7 @@ def A4_psxtbfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = sxtb($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000101; @@ -2782,7 +2770,7 @@ def A4_psxtbt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = sxtb($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000101; @@ -2795,7 +2783,7 @@ def A4_psxtbtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = sxtb($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000101; @@ -2809,7 +2797,7 @@ def A4_psxthf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = sxth($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000111; @@ -2823,7 +2811,7 @@ def A4_psxthfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = sxth($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000111; @@ -2838,7 +2826,7 @@ def A4_psxtht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = sxth($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000111; @@ -2851,7 +2839,7 @@ def A4_psxthtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = sxth($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000111; @@ -2865,7 +2853,7 @@ def A4_pzxtbf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = zxtb($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000100; @@ -2879,7 +2867,7 @@ def A4_pzxtbfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = zxtb($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000100; @@ -2894,7 +2882,7 @@ def A4_pzxtbt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = zxtb($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000100; @@ -2907,7 +2895,7 @@ def A4_pzxtbtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = zxtb($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000100; @@ -2921,7 +2909,7 @@ def A4_pzxthf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = zxth($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000110; @@ -2935,7 +2923,7 @@ def A4_pzxthfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = zxth($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000110; @@ -2950,7 +2938,7 @@ def A4_pzxtht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = zxth($Rs32)", -tc_548f402d, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_b9488031, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000110; @@ -2963,7 +2951,7 @@ def A4_pzxthtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = zxth($Rs32)", -tc_b08be45e, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_5f6847a1, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000110; @@ -2977,7 +2965,7 @@ def A4_rcmpeq : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmp.eq($Rs32,$Rt32)", -tc_548f402d, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { +tc_b9488031, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011010; @@ -2991,7 +2979,7 @@ def A4_rcmpeqi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = cmp.eq($Rs32,#$Ii)", -tc_548f402d, TypeALU32_2op>, Enc_b8c967, ImmRegRel { +tc_b9488031, TypeALU32_2op>, Enc_b8c967, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011010; let hasNewValue = 1; @@ -3008,7 +2996,7 @@ def A4_rcmpneq : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = !cmp.eq($Rs32,$Rt32)", -tc_548f402d, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { +tc_b9488031, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011011; @@ -3022,7 +3010,7 @@ def A4_rcmpneqi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = !cmp.eq($Rs32,#$Ii)", -tc_548f402d, TypeALU32_2op>, Enc_b8c967, ImmRegRel { +tc_b9488031, TypeALU32_2op>, Enc_b8c967, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011011; let hasNewValue = 1; @@ -3039,7 +3027,7 @@ def A4_round_ri : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = round($Rs32,#$Ii)", -tc_63cd9d2d, TypeS_2op>, Enc_a05677 { +tc_2b6f77c6, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100111; @@ -3051,7 +3039,7 @@ def A4_round_ri_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = round($Rs32,#$Ii):sat", -tc_63cd9d2d, TypeS_2op>, Enc_a05677 { +tc_2b6f77c6, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100111; @@ -3064,7 +3052,7 @@ def A4_round_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = round($Rs32,$Rt32)", -tc_63cd9d2d, TypeS_3op>, Enc_5ab2be { +tc_2b6f77c6, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110110; @@ -3076,7 +3064,7 @@ def A4_round_rr_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = round($Rs32,$Rt32):sat", -tc_63cd9d2d, TypeS_3op>, Enc_5ab2be { +tc_2b6f77c6, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110110; @@ -3089,7 +3077,7 @@ def A4_subp_c : HInst< (outs DoubleRegs:$Rdd32, PredRegs:$Px4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), "$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry", -tc_a87879e8, TypeS_3op>, Enc_2b3f60 { +tc_523fcf30, TypeS_3op>, Enc_2b3f60 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010111; @@ -3100,7 +3088,7 @@ def A4_tfrcpp : HInst< (outs DoubleRegs:$Rdd32), (ins CtrRegs64:$Css32), "$Rdd32 = $Css32", -tc_3b4892c6, TypeCR>, Enc_667b39 { +tc_29175780, TypeCR>, Enc_667b39 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01101000000; } @@ -3108,7 +3096,7 @@ def A4_tfrpcp : HInst< (outs CtrRegs64:$Cdd32), (ins DoubleRegs:$Rss32), "$Cdd32 = $Rss32", -tc_82f0f122, TypeCR>, Enc_0ed752 { +tc_a21dc435, TypeCR>, Enc_0ed752 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01100011001; } @@ -3116,7 +3104,7 @@ def A4_tlbmatch : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Pd4 = tlbmatch($Rss32,$Rt32)", -tc_e2c08bb4, TypeALU64>, Enc_03833b { +tc_04c9decc, TypeALU64>, Enc_03833b { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3126,7 +3114,7 @@ def A4_vcmpbeq_any : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3135,7 +3123,7 @@ def A4_vcmpbeqi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u8_0Imm:$Ii), "$Pd4 = vcmpb.eq($Rss32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_0d8adb { +tc_7a830544, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100000; @@ -3144,7 +3132,7 @@ def A4_vcmpbgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpb.gt($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3153,7 +3141,7 @@ def A4_vcmpbgti : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmpb.gt($Rss32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_0d8adb { +tc_7a830544, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100001; @@ -3162,7 +3150,7 @@ def A4_vcmpbgtui : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), "$Pd4 = vcmpb.gtu($Rss32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_3680c2 { +tc_7a830544, TypeALU64>, Enc_3680c2 { let Inst{4-2} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011100010; @@ -3171,7 +3159,7 @@ def A4_vcmpheqi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmph.eq($Rss32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_0d8adb { +tc_7a830544, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100000; @@ -3180,7 +3168,7 @@ def A4_vcmphgti : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmph.gt($Rss32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_0d8adb { +tc_7a830544, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100001; @@ -3189,7 +3177,7 @@ def A4_vcmphgtui : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), "$Pd4 = vcmph.gtu($Rss32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_3680c2 { +tc_7a830544, TypeALU64>, Enc_3680c2 { let Inst{4-2} = 0b010; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011100010; @@ -3198,7 +3186,7 @@ def A4_vcmpweqi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmpw.eq($Rss32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_0d8adb { +tc_7a830544, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100000; @@ -3207,7 +3195,7 @@ def A4_vcmpwgti : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmpw.gt($Rss32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_0d8adb { +tc_7a830544, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100001; @@ -3216,7 +3204,7 @@ def A4_vcmpwgtui : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), "$Pd4 = vcmpw.gtu($Rss32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_3680c2 { +tc_7a830544, TypeALU64>, Enc_3680c2 { let Inst{4-2} = 0b100; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011100010; @@ -3225,7 +3213,7 @@ def A4_vrmaxh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxh($Rss32,$Ru32)", -tc_2aaab1e0, TypeS_3op>, Enc_412ff0 { +tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3236,7 +3224,7 @@ def A4_vrmaxuh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxuh($Rss32,$Ru32)", -tc_2aaab1e0, TypeS_3op>, Enc_412ff0 { +tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3247,7 +3235,7 @@ def A4_vrmaxuw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxuw($Rss32,$Ru32)", -tc_2aaab1e0, TypeS_3op>, Enc_412ff0 { +tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3258,7 +3246,7 @@ def A4_vrmaxw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxw($Rss32,$Ru32)", -tc_2aaab1e0, TypeS_3op>, Enc_412ff0 { +tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3269,7 +3257,7 @@ def A4_vrminh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminh($Rss32,$Ru32)", -tc_2aaab1e0, TypeS_3op>, Enc_412ff0 { +tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3280,7 +3268,7 @@ def A4_vrminuh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminuh($Rss32,$Ru32)", -tc_2aaab1e0, TypeS_3op>, Enc_412ff0 { +tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3291,7 +3279,7 @@ def A4_vrminuw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminuw($Rss32,$Ru32)", -tc_2aaab1e0, TypeS_3op>, Enc_412ff0 { +tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3302,7 +3290,7 @@ def A4_vrminw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminw($Rss32,$Ru32)", -tc_2aaab1e0, TypeS_3op>, Enc_412ff0 { +tc_c6ce9b3f, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3313,7 +3301,7 @@ def A5_ACS : HInst< (outs DoubleRegs:$Rxx32, PredRegs:$Pe4), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)", -tc_ae0722f7, TypeM>, Enc_831a7d, Requires<[HasV55T]> { +tc_caaebcba, TypeM>, Enc_831a7d, Requires<[HasV55T]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -3326,7 +3314,7 @@ def A5_vaddhubs : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vaddhub($Rss32,$Rtt32):sat", -tc_63cd9d2d, TypeS_3op>, Enc_d2216a, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_3op>, Enc_d2216a, Requires<[HasV5T]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -3335,11 +3323,20 @@ let opNewValue = 0; let prefersSlot3 = 1; let Defs = [USR_OVF]; } +def A6_vcmpbeq_notany : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))", +tc_55050d58, TypeALU64>, Enc_fcf7a7, Requires<[HasV65T]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11010010000; +} def A6_vminub_RdP : HInst< (outs DoubleRegs:$Rdd32, PredRegs:$Pe4), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)", -tc_583510c7, TypeM>, Enc_d2c7f1, Requires<[HasV62T]> { +tc_ef84f62f, TypeM>, Enc_d2c7f1, Requires<[HasV62T]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -3350,7 +3347,7 @@ def C2_all8 : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = all8($Ps4)", -tc_81a23d44, TypeCR>, Enc_65d691 { +tc_f2704b9a, TypeCR>, Enc_65d691 { let Inst{13-2} = 0b000000000000; let Inst{31-18} = 0b01101011101000; } @@ -3358,7 +3355,7 @@ def C2_and : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = and($Pt4,$Ps4)", -tc_d63b71d1, TypeCR>, Enc_454a26 { +tc_53bc8a6a, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011000000; @@ -3367,7 +3364,7 @@ def C2_andn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = and($Pt4,!$Ps4)", -tc_d63b71d1, TypeCR>, Enc_454a26 { +tc_53bc8a6a, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011011000; @@ -3376,7 +3373,7 @@ def C2_any8 : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = any8($Ps4)", -tc_81a23d44, TypeCR>, Enc_65d691 { +tc_f2704b9a, TypeCR>, Enc_65d691 { let Inst{13-2} = 0b000000000000; let Inst{31-18} = 0b01101011100000; } @@ -3384,7 +3381,7 @@ def C2_bitsclr : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = bitsclr($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e { +tc_1e856f58, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111100; @@ -3393,7 +3390,7 @@ def C2_bitsclri : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u6_0Imm:$Ii), "$Pd4 = bitsclr($Rs32,#$Ii)", -tc_5fa2857c, TypeS_2op>, Enc_5d6c34 { +tc_7a830544, TypeS_2op>, Enc_5d6c34 { let Inst{7-2} = 0b000000; let Inst{31-21} = 0b10000101100; } @@ -3401,7 +3398,7 @@ def C2_bitsset : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = bitsset($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e { +tc_1e856f58, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111010; @@ -3410,7 +3407,7 @@ def C2_ccombinewf : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)", -tc_1b6011fb, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_d6bf0472, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111101000; @@ -3422,7 +3419,7 @@ def C2_ccombinewnewf : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", -tc_28d296df, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_2b2f4060, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111101000; @@ -3435,7 +3432,7 @@ def C2_ccombinewnewt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", -tc_28d296df, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_2b2f4060, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111101000; @@ -3447,7 +3444,7 @@ def C2_ccombinewt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)", -tc_1b6011fb, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_d6bf0472, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111101000; @@ -3458,7 +3455,7 @@ def C2_cmoveif : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if (!$Pu4) $Rd32 = #$Ii", -tc_548f402d, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_b9488031, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111101; @@ -3480,7 +3477,7 @@ def C2_cmoveit : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if ($Pu4) $Rd32 = #$Ii", -tc_548f402d, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_b9488031, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111100; @@ -3501,7 +3498,7 @@ def C2_cmovenewif : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if (!$Pu4.new) $Rd32 = #$Ii", -tc_b08be45e, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_5f6847a1, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111101; @@ -3524,7 +3521,7 @@ def C2_cmovenewit : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if ($Pu4.new) $Rd32 = #$Ii", -tc_b08be45e, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_5f6847a1, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111100; @@ -3546,7 +3543,7 @@ def C2_cmpeq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.eq($Rs32,$Rt32)", -tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010000; @@ -3559,7 +3556,7 @@ def C2_cmpeqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmp.eq($Rs32,#$Ii)", -tc_9df8b0dc, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b000; let Inst{31-22} = 0b0111010100; let CextOpcode = "C2_cmpeq"; @@ -3575,7 +3572,7 @@ def C2_cmpeqp : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = cmp.eq($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010100; @@ -3586,7 +3583,7 @@ def C2_cmpgei : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s8_0Imm:$Ii), "$Pd4 = cmp.ge($Rs32,#$Ii)", -tc_9df8b0dc, TypeALU32_2op> { +tc_6ebb4a12, TypeALU32_2op> { let isCompare = 1; let isPseudo = 1; } @@ -3594,7 +3591,7 @@ def C2_cmpgeui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u8_0Imm:$Ii), "$Pd4 = cmp.geu($Rs32,#$Ii)", -tc_9df8b0dc, TypeALU32_2op> { +tc_6ebb4a12, TypeALU32_2op> { let isCompare = 1; let isPseudo = 1; } @@ -3602,7 +3599,7 @@ def C2_cmpgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.gt($Rs32,$Rt32)", -tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010010; @@ -3614,7 +3611,7 @@ def C2_cmpgti : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmp.gt($Rs32,#$Ii)", -tc_9df8b0dc, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b000; let Inst{31-22} = 0b0111010101; let CextOpcode = "C2_cmpgt"; @@ -3630,7 +3627,7 @@ def C2_cmpgtp : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = cmp.gt($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010100; @@ -3640,7 +3637,7 @@ def C2_cmpgtu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.gtu($Rs32,$Rt32)", -tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010011; @@ -3652,7 +3649,7 @@ def C2_cmpgtui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = cmp.gtu($Rs32,#$Ii)", -tc_9df8b0dc, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { +tc_6ebb4a12, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { let Inst{4-2} = 0b000; let Inst{31-21} = 0b01110101100; let CextOpcode = "C2_cmpgtu"; @@ -3668,7 +3665,7 @@ def C2_cmpgtup : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = cmp.gtu($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7 { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010100; @@ -3678,7 +3675,7 @@ def C2_cmplt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.lt($Rs32,$Rt32)", -tc_9df8b0dc, TypeALU32_3op> { +tc_6ebb4a12, TypeALU32_3op> { let isCompare = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -3687,7 +3684,7 @@ def C2_cmpltu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.ltu($Rs32,$Rt32)", -tc_9df8b0dc, TypeALU32_3op> { +tc_6ebb4a12, TypeALU32_3op> { let isCompare = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -3696,7 +3693,7 @@ def C2_mask : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4), "$Rdd32 = mask($Pt4)", -tc_b86c7e8b, TypeS_2op>, Enc_78e566 { +tc_cde8b071, TypeS_2op>, Enc_78e566 { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0000; let Inst{31-16} = 0b1000011000000000; @@ -3705,7 +3702,7 @@ def C2_mux : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mux($Pu4,$Rs32,$Rt32)", -tc_1b6011fb, TypeALU32_3op>, Enc_ea4c54 { +tc_d6bf0472, TypeALU32_3op>, Enc_ea4c54 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110100000; @@ -3717,7 +3714,7 @@ def C2_muxii : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II), "$Rd32 = mux($Pu4,#$Ii,#$II)", -tc_1b6011fb, TypeALU32_2op>, Enc_830e5d { +tc_d6bf0472, TypeALU32_2op>, Enc_830e5d { let Inst{31-25} = 0b0111101; let hasNewValue = 1; let opNewValue = 0; @@ -3731,7 +3728,7 @@ def C2_muxir : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = mux($Pu4,$Rs32,#$Ii)", -tc_1b6011fb, TypeALU32_2op>, Enc_e38e1f { +tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011100110; let hasNewValue = 1; @@ -3747,7 +3744,7 @@ def C2_muxri : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32), "$Rd32 = mux($Pu4,#$Ii,$Rs32)", -tc_1b6011fb, TypeALU32_2op>, Enc_e38e1f { +tc_d6bf0472, TypeALU32_2op>, Enc_e38e1f { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011100111; let hasNewValue = 1; @@ -3763,7 +3760,7 @@ def C2_not : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = not($Ps4)", -tc_81a23d44, TypeCR>, Enc_65d691 { +tc_f2704b9a, TypeCR>, Enc_65d691 { let Inst{13-2} = 0b000000000000; let Inst{31-18} = 0b01101011110000; } @@ -3771,7 +3768,7 @@ def C2_or : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = or($Pt4,$Ps4)", -tc_d63b71d1, TypeCR>, Enc_454a26 { +tc_53bc8a6a, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011001000; @@ -3780,7 +3777,7 @@ def C2_orn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = or($Pt4,!$Ps4)", -tc_d63b71d1, TypeCR>, Enc_454a26 { +tc_53bc8a6a, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011111000; @@ -3789,7 +3786,7 @@ def C2_pxfer_map : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = $Ps4", -tc_d63b71d1, TypeMAPPING> { +tc_53bc8a6a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -3797,7 +3794,7 @@ def C2_tfrpr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Ps4), "$Rd32 = $Ps4", -tc_b86c7e8b, TypeS_2op>, Enc_f5e933 { +tc_cde8b071, TypeS_2op>, Enc_f5e933 { let Inst{13-5} = 0b000000000; let Inst{31-18} = 0b10001001010000; let hasNewValue = 1; @@ -3807,7 +3804,7 @@ def C2_tfrrp : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32), "$Pd4 = $Rs32", -tc_47f0b7ad, TypeS_2op>, Enc_48b75f { +tc_351fed2d, TypeS_2op>, Enc_48b75f { let Inst{13-2} = 0b000000000000; let Inst{31-21} = 0b10000101010; } @@ -3815,7 +3812,7 @@ def C2_vitpack : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Rd32 = vitpack($Ps4,$Pt4)", -tc_7ca2ea10, TypeS_2op>, Enc_527412 { +tc_1b9c9ee5, TypeS_2op>, Enc_527412 { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b10001001000000; @@ -3827,7 +3824,7 @@ def C2_vmux : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)", -tc_d1b5a4b6, TypeALU64>, Enc_329361 { +tc_f8eeed7a, TypeALU64>, Enc_329361 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010001000; @@ -3836,7 +3833,7 @@ def C2_xor : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Pd4 = xor($Ps4,$Pt4)", -tc_d63b71d1, TypeCR>, Enc_284ebb { +tc_53bc8a6a, TypeCR>, Enc_284ebb { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011010000; @@ -3845,7 +3842,7 @@ def C4_addipc : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = add(pc,#$Ii)", -tc_1fe8323c, TypeCR>, Enc_607661 { +tc_b9c4623f, TypeCR>, Enc_607661 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0110101001001001; @@ -3861,7 +3858,7 @@ def C4_and_and : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,and($Pt4,$Pu4))", -tc_43068634, TypeCR>, Enc_9ac432 { +tc_481e5e5c, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011000100; @@ -3870,7 +3867,7 @@ def C4_and_andn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,and($Pt4,!$Pu4))", -tc_43068634, TypeCR>, Enc_9ac432 { +tc_481e5e5c, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011100100; @@ -3879,7 +3876,7 @@ def C4_and_or : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,or($Pt4,$Pu4))", -tc_43068634, TypeCR>, Enc_9ac432 { +tc_481e5e5c, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011001100; @@ -3888,7 +3885,7 @@ def C4_and_orn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,or($Pt4,!$Pu4))", -tc_43068634, TypeCR>, Enc_9ac432 { +tc_481e5e5c, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011101100; @@ -3897,7 +3894,7 @@ def C4_cmplte : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !cmp.gt($Rs32,$Rt32)", -tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010010; @@ -3909,7 +3906,7 @@ def C4_cmpltei : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = !cmp.gt($Rs32,#$Ii)", -tc_9df8b0dc, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b100; let Inst{31-22} = 0b0111010101; let CextOpcode = "C4_cmplte"; @@ -3925,7 +3922,7 @@ def C4_cmplteu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !cmp.gtu($Rs32,$Rt32)", -tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010011; @@ -3937,7 +3934,7 @@ def C4_cmplteui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = !cmp.gtu($Rs32,#$Ii)", -tc_9df8b0dc, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { +tc_6ebb4a12, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { let Inst{4-2} = 0b100; let Inst{31-21} = 0b01110101100; let CextOpcode = "C4_cmplteu"; @@ -3953,7 +3950,7 @@ def C4_cmpneq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !cmp.eq($Rs32,$Rt32)", -tc_5fe9fcd0, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_c6aa82f7, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010000; @@ -3966,7 +3963,7 @@ def C4_cmpneqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = !cmp.eq($Rs32,#$Ii)", -tc_9df8b0dc, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_6ebb4a12, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b100; let Inst{31-22} = 0b0111010100; let CextOpcode = "C4_cmpneq"; @@ -3982,7 +3979,7 @@ def C4_fastcorner9 : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Pd4 = fastcorner9($Ps4,$Pt4)", -tc_d63b71d1, TypeCR>, Enc_284ebb { +tc_53bc8a6a, TypeCR>, Enc_284ebb { let Inst{7-2} = 0b100100; let Inst{13-10} = 0b1000; let Inst{31-18} = 0b01101011000000; @@ -3991,7 +3988,7 @@ def C4_fastcorner9_not : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Pd4 = !fastcorner9($Ps4,$Pt4)", -tc_d63b71d1, TypeCR>, Enc_284ebb { +tc_53bc8a6a, TypeCR>, Enc_284ebb { let Inst{7-2} = 0b100100; let Inst{13-10} = 0b1000; let Inst{31-18} = 0b01101011000100; @@ -4000,7 +3997,7 @@ def C4_nbitsclr : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !bitsclr($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e { +tc_1e856f58, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111101; @@ -4009,7 +4006,7 @@ def C4_nbitsclri : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u6_0Imm:$Ii), "$Pd4 = !bitsclr($Rs32,#$Ii)", -tc_5fa2857c, TypeS_2op>, Enc_5d6c34 { +tc_7a830544, TypeS_2op>, Enc_5d6c34 { let Inst{7-2} = 0b000000; let Inst{31-21} = 0b10000101101; } @@ -4017,7 +4014,7 @@ def C4_nbitsset : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !bitsset($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e { +tc_1e856f58, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111011; @@ -4026,7 +4023,7 @@ def C4_or_and : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,and($Pt4,$Pu4))", -tc_43068634, TypeCR>, Enc_9ac432 { +tc_481e5e5c, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011010100; @@ -4035,7 +4032,7 @@ def C4_or_andn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,and($Pt4,!$Pu4))", -tc_43068634, TypeCR>, Enc_9ac432 { +tc_481e5e5c, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011110100; @@ -4044,7 +4041,7 @@ def C4_or_or : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,or($Pt4,$Pu4))", -tc_43068634, TypeCR>, Enc_9ac432 { +tc_481e5e5c, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011011100; @@ -4053,7 +4050,7 @@ def C4_or_orn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,or($Pt4,!$Pu4))", -tc_43068634, TypeCR>, Enc_9ac432 { +tc_481e5e5c, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011111100; @@ -4062,7 +4059,7 @@ def F2_conv_d2df : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_d2df($Rss32)", -tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4072,7 +4069,7 @@ def F2_conv_d2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_d2sf($Rss32)", -tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -4084,7 +4081,7 @@ def F2_conv_df2d : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2d($Rss32)", -tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4094,7 +4091,7 @@ def F2_conv_df2d_chop : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2d($Rss32):chop", -tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4104,7 +4101,7 @@ def F2_conv_df2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2sf($Rss32)", -tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -4116,7 +4113,7 @@ def F2_conv_df2ud : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2ud($Rss32)", -tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4126,7 +4123,7 @@ def F2_conv_df2ud_chop : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2ud($Rss32):chop", -tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4136,7 +4133,7 @@ def F2_conv_df2uw : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2uw($Rss32)", -tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -4148,7 +4145,7 @@ def F2_conv_df2uw_chop : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2uw($Rss32):chop", -tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000101; let hasNewValue = 1; @@ -4160,7 +4157,7 @@ def F2_conv_df2w : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2w($Rss32)", -tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -4172,7 +4169,7 @@ def F2_conv_df2w_chop : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2w($Rss32):chop", -tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000111; let hasNewValue = 1; @@ -4184,7 +4181,7 @@ def F2_conv_sf2d : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2d($Rs32)", -tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4194,7 +4191,7 @@ def F2_conv_sf2d_chop : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2d($Rs32):chop", -tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4204,7 +4201,7 @@ def F2_conv_sf2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2df($Rs32)", -tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4214,7 +4211,7 @@ def F2_conv_sf2ud : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2ud($Rs32)", -tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4224,7 +4221,7 @@ def F2_conv_sf2ud_chop : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2ud($Rs32):chop", -tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4234,7 +4231,7 @@ def F2_conv_sf2uw : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2uw($Rs32)", -tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011011; let hasNewValue = 1; @@ -4246,7 +4243,7 @@ def F2_conv_sf2uw_chop : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2uw($Rs32):chop", -tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001011011; let hasNewValue = 1; @@ -4258,7 +4255,7 @@ def F2_conv_sf2w : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2w($Rs32)", -tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011100; let hasNewValue = 1; @@ -4270,7 +4267,7 @@ def F2_conv_sf2w_chop : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2w($Rs32):chop", -tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001011100; let hasNewValue = 1; @@ -4282,7 +4279,7 @@ def F2_conv_ud2df : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_ud2df($Rss32)", -tc_e836c161, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5T]> { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4292,7 +4289,7 @@ def F2_conv_ud2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_ud2sf($Rss32)", -tc_e836c161, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000001; let hasNewValue = 1; @@ -4304,7 +4301,7 @@ def F2_conv_uw2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_uw2df($Rs32)", -tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4314,7 +4311,7 @@ def F2_conv_uw2sf : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_uw2sf($Rs32)", -tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011001; let hasNewValue = 1; @@ -4326,7 +4323,7 @@ def F2_conv_w2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_w2df($Rs32)", -tc_e836c161, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5T]> { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4336,7 +4333,7 @@ def F2_conv_w2sf : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_w2sf($Rs32)", -tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011010; let hasNewValue = 1; @@ -4348,7 +4345,7 @@ def F2_dfclass : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Pd4 = dfclass($Rss32,#$Ii)", -tc_5fa2857c, TypeALU64>, Enc_1f19b5, Requires<[HasV5T]> { +tc_7a830544, TypeALU64>, Enc_1f19b5, Requires<[HasV5T]> { let Inst{4-2} = 0b100; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b11011100100; @@ -4359,7 +4356,7 @@ def F2_dfcmpeq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.eq($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4371,7 +4368,7 @@ def F2_dfcmpge : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.ge($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4383,7 +4380,7 @@ def F2_dfcmpgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.gt($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4395,7 +4392,7 @@ def F2_dfcmpuo : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.uo($Rss32,$Rtt32)", -tc_c58f771a, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5T]> { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4407,7 +4404,7 @@ def F2_dfimm_n : HInst< (outs DoubleRegs:$Rdd32), (ins u10_0Imm:$Ii), "$Rdd32 = dfmake(#$Ii):neg", -tc_485bb57c, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> { +tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101100101; let prefersSlot3 = 1; @@ -4416,7 +4413,7 @@ def F2_dfimm_p : HInst< (outs DoubleRegs:$Rdd32), (ins u10_0Imm:$Ii), "$Rdd32 = dfmake(#$Ii):pos", -tc_485bb57c, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> { +tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5T]> { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101100100; let prefersSlot3 = 1; @@ -4425,7 +4422,7 @@ def F2_sfadd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfadd($Rs32,$Rt32)", -tc_3bea1824, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011000; @@ -4439,7 +4436,7 @@ def F2_sfclass : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Pd4 = sfclass($Rs32,#$Ii)", -tc_5fa2857c, TypeS_2op>, Enc_83ee64, Requires<[HasV5T]> { +tc_7a830544, TypeS_2op>, Enc_83ee64, Requires<[HasV5T]> { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000101111; @@ -4450,7 +4447,7 @@ def F2_sfcmpeq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.eq($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4462,7 +4459,7 @@ def F2_sfcmpge : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.ge($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4474,7 +4471,7 @@ def F2_sfcmpgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.gt($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4486,7 +4483,7 @@ def F2_sfcmpuo : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.uo($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5T]> { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4498,7 +4495,7 @@ def F2_sffixupd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sffixupd($Rs32,$Rt32)", -tc_3bea1824, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011110; @@ -4510,7 +4507,7 @@ def F2_sffixupn : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sffixupn($Rs32,$Rt32)", -tc_3bea1824, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011110; @@ -4522,7 +4519,7 @@ def F2_sffixupr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sffixupr($Rs32)", -tc_e836c161, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5T]> { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011101; let hasNewValue = 1; @@ -4533,7 +4530,7 @@ def F2_sffma : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += sfmpy($Rs32,$Rt32)", -tc_2d1e6f5c, TypeM>, Enc_2ae154, Requires<[HasV5T]> { +tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4547,7 +4544,7 @@ def F2_sffma_lib : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += sfmpy($Rs32,$Rt32):lib", -tc_2d1e6f5c, TypeM>, Enc_2ae154, Requires<[HasV5T]> { +tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4561,7 +4558,7 @@ def F2_sffma_sc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4), "$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale", -tc_2e55aa16, TypeM>, Enc_437f33, Requires<[HasV5T]> { +tc_038a1342, TypeM>, Enc_437f33, Requires<[HasV5T]> { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111011; @@ -4575,7 +4572,7 @@ def F2_sffms : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= sfmpy($Rs32,$Rt32)", -tc_2d1e6f5c, TypeM>, Enc_2ae154, Requires<[HasV5T]> { +tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4589,7 +4586,7 @@ def F2_sffms_lib : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= sfmpy($Rs32,$Rt32):lib", -tc_2d1e6f5c, TypeM>, Enc_2ae154, Requires<[HasV5T]> { +tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5T]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4603,7 +4600,7 @@ def F2_sfimm_n : HInst< (outs IntRegs:$Rd32), (ins u10_0Imm:$Ii), "$Rd32 = sfmake(#$Ii):neg", -tc_485bb57c, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> { +tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101011001; let hasNewValue = 1; @@ -4614,7 +4611,7 @@ def F2_sfimm_p : HInst< (outs IntRegs:$Rd32), (ins u10_0Imm:$Ii), "$Rd32 = sfmake(#$Ii):pos", -tc_485bb57c, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> { +tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5T]> { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101011000; let hasNewValue = 1; @@ -4625,7 +4622,7 @@ def F2_sfinvsqrta : HInst< (outs IntRegs:$Rd32, PredRegs:$Pe4), (ins IntRegs:$Rs32), "$Rd32,$Pe4 = sfinvsqrta($Rs32)", -tc_f1aa2cdb, TypeS_2op>, Enc_890909, Requires<[HasV5T]> { +tc_4d99bca9, TypeS_2op>, Enc_890909, Requires<[HasV5T]> { let Inst{13-7} = 0b0000000; let Inst{31-21} = 0b10001011111; let hasNewValue = 1; @@ -4637,7 +4634,7 @@ def F2_sfmax : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmax($Rs32,$Rt32)", -tc_f1240c08, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011100; @@ -4651,7 +4648,7 @@ def F2_sfmin : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmin($Rs32,$Rt32)", -tc_f1240c08, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011100; @@ -4665,7 +4662,7 @@ def F2_sfmpy : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmpy($Rs32,$Rt32)", -tc_3bea1824, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011010; @@ -4679,7 +4676,7 @@ def F2_sfrecipa : HInst< (outs IntRegs:$Rd32, PredRegs:$Pe4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)", -tc_09c86199, TypeM>, Enc_a94f3b, Requires<[HasV5T]> { +tc_9c00ce8d, TypeM>, Enc_a94f3b, Requires<[HasV5T]> { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011111; @@ -4692,7 +4689,7 @@ def F2_sfsub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfsub($Rs32,$Rt32)", -tc_3bea1824, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { +tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5T]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011000; @@ -4705,11 +4702,13 @@ def J2_call : HInst< (outs), (ins a30_2Imm:$Ii), "call $Ii", -tc_639d93ee, TypeJ>, Enc_81ac1d, PredRel { +tc_a27582fa, TypeJ>, Enc_81ac1d, PredRel { let Inst{0-0} = 0b0; let Inst{31-25} = 0b0101101; let isCall = 1; let prefersSlot3 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [R29]; let Defs = [PC, R31]; let BaseOpcode = "J2_call"; @@ -4725,7 +4724,7 @@ def J2_callf : HInst< (outs), (ins PredRegs:$Pu4, a30_2Imm:$Ii), "if (!$Pu4) call $Ii", -tc_0767081f, TypeJ>, Enc_daea09, PredRel { +tc_2f185f5c, TypeJ>, Enc_daea09, PredRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b1; @@ -4734,6 +4733,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isCall = 1; let prefersSlot3 = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [R29]; let Defs = [PC, R31]; let BaseOpcode = "J2_call"; @@ -4749,12 +4751,12 @@ def J2_callr : HInst< (outs), (ins IntRegs:$Rs32), "callr $Rs32", -tc_ecfaae86, TypeJ>, Enc_ecbcc8 { +tc_15411484, TypeJ>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010000101; -let cofMax1 = 1; let isCall = 1; let prefersSlot3 = 1; +let cofMax1 = 1; let Uses = [R29]; let Defs = [PC, R31]; let hasSideEffects = 1; @@ -4763,15 +4765,15 @@ def J2_callrf : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) callr $Rs32", -tc_84630363, TypeJ>, Enc_88d4d9 { +tc_10b97e27, TypeJ>, Enc_88d4d9 { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010001001; let isPredicated = 1; let isPredicatedFalse = 1; -let cofMax1 = 1; let isCall = 1; let prefersSlot3 = 1; +let cofMax1 = 1; let Uses = [R29]; let Defs = [PC, R31]; let hasSideEffects = 1; @@ -4781,14 +4783,14 @@ def J2_callrt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) callr $Rs32", -tc_84630363, TypeJ>, Enc_88d4d9 { +tc_10b97e27, TypeJ>, Enc_88d4d9 { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010001000; let isPredicated = 1; -let cofMax1 = 1; let isCall = 1; let prefersSlot3 = 1; +let cofMax1 = 1; let Uses = [R29]; let Defs = [PC, R31]; let hasSideEffects = 1; @@ -4798,7 +4800,7 @@ def J2_callt : HInst< (outs), (ins PredRegs:$Pu4, a30_2Imm:$Ii), "if ($Pu4) call $Ii", -tc_0767081f, TypeJ>, Enc_daea09, PredRel { +tc_2f185f5c, TypeJ>, Enc_daea09, PredRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b0; @@ -4806,6 +4808,9 @@ let Inst{31-24} = 0b01011101; let isPredicated = 1; let isCall = 1; let prefersSlot3 = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [R29]; let Defs = [PC, R31]; let BaseOpcode = "J2_call"; @@ -4821,7 +4826,7 @@ def J2_endloop0 : HInst< (outs), (ins), "endloop0", -tc_aad55963, TypeJ> { +tc_52d7bbea, TypeJ> { let Uses = [LC0, SA0]; let Defs = [LC0, P3, PC, USR]; let isBranch = 1; @@ -4832,7 +4837,7 @@ def J2_endloop01 : HInst< (outs), (ins), "endloop01", -tc_aad55963, TypeJ> { +tc_52d7bbea, TypeJ> { let Uses = [LC0, LC1, SA0, SA1]; let Defs = [LC0, LC1, P3, PC, USR]; let isPseudo = 1; @@ -4841,7 +4846,7 @@ def J2_endloop1 : HInst< (outs), (ins), "endloop1", -tc_aad55963, TypeJ> { +tc_52d7bbea, TypeJ> { let Uses = [LC1, SA1]; let Defs = [LC1, PC]; let isBranch = 1; @@ -4852,11 +4857,13 @@ def J2_jump : HInst< (outs), (ins b30_2Imm:$Ii), "jump $Ii", -tc_a333d2a9, TypeJ>, Enc_81ac1d, PredNewRel { +tc_3669266a, TypeJ>, Enc_81ac1d, PredNewRel { let Inst{0-0} = 0b0; let Inst{31-25} = 0b0101100; let isTerminator = 1; let isBranch = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "imm"; let BaseOpcode = "J2_jump"; @@ -4872,7 +4879,7 @@ def J2_jumpf : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4) jump:nt $Ii", -tc_1b834fe7, TypeJ>, Enc_daea09, PredNewRel { +tc_e9fae2d6, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b1; @@ -4881,6 +4888,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "imm"; let BaseOpcode = "J2_jump"; @@ -4895,7 +4905,7 @@ def J2_jumpf_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, b15_2Imm:$Ii), "if (!$Pu4) jump $Ii", -tc_1b834fe7, TypeMAPPING>, Requires<[HasV60T]> { +tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60T]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -4903,7 +4913,7 @@ def J2_jumpfnew : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4.new) jump:nt $Ii", -tc_537e2013, TypeJ>, Enc_daea09, PredNewRel { +tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b010; let Inst{21-21} = 0b1; @@ -4913,6 +4923,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "imm"; let BaseOpcode = "J2_jump"; @@ -4927,7 +4940,7 @@ def J2_jumpfnewpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4.new) jump:t $Ii", -tc_537e2013, TypeJ>, Enc_daea09, PredNewRel { +tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b110; let Inst{21-21} = 0b1; @@ -4937,6 +4950,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "imm"; let BaseOpcode = "J2_jump"; @@ -4951,7 +4967,7 @@ def J2_jumpfpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4) jump:t $Ii", -tc_b5bfaa60, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel { +tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b100; let Inst{21-21} = 0b1; @@ -4960,6 +4976,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "imm"; let BaseOpcode = "J2_jump"; @@ -4974,7 +4993,7 @@ def J2_jumpr : HInst< (outs), (ins IntRegs:$Rs32), "jumpr $Rs32", -tc_b08b653e, TypeJ>, Enc_ecbcc8, PredNewRel { +tc_9faf76ae, TypeJ>, Enc_ecbcc8, PredNewRel { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010010100; let isTerminator = 1; @@ -4991,7 +5010,7 @@ def J2_jumprf : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) jumpr:nt $Rs32", -tc_07ac815d, TypeJ>, Enc_88d4d9, PredNewRel { +tc_e0739b8c, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010011011; @@ -5010,7 +5029,7 @@ def J2_jumprf_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) jumpr $Rs32", -tc_07ac815d, TypeMAPPING>, Requires<[HasV60T]> { +tc_e0739b8c, TypeMAPPING>, Requires<[HasV60T]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5018,7 +5037,7 @@ def J2_jumprfnew : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) jumpr:nt $Rs32", -tc_1f9668cc, TypeJ>, Enc_88d4d9, PredNewRel { +tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0010; let Inst{31-21} = 0b01010011011; @@ -5027,8 +5046,8 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isIndirectBranch = 1; let isBranch = 1; -let cofMax1 = 1; let isPredicatedNew = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "reg"; let BaseOpcode = "J2_jumpr"; @@ -5038,7 +5057,7 @@ def J2_jumprfnewpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) jumpr:t $Rs32", -tc_1f9668cc, TypeJ>, Enc_88d4d9, PredNewRel { +tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0110; let Inst{31-21} = 0b01010011011; @@ -5047,8 +5066,8 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isIndirectBranch = 1; let isBranch = 1; -let cofMax1 = 1; let isPredicatedNew = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "reg"; let BaseOpcode = "J2_jumpr"; @@ -5058,7 +5077,7 @@ def J2_jumprfpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) jumpr:t $Rs32", -tc_a1fb80e1, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel { +tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0100; let Inst{31-21} = 0b01010011011; @@ -5077,7 +5096,7 @@ def J2_jumprgtez : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32>=#0) jump:nt $Ii", -tc_b324366f, TypeCR>, Enc_0fa531 { +tc_73043bf4, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000101; @@ -5085,6 +5104,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let isTaken = Inst{12}; } @@ -5092,7 +5114,7 @@ def J2_jumprgtezpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32>=#0) jump:t $Ii", -tc_b324366f, TypeCR>, Enc_0fa531 { +tc_73043bf4, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000101; @@ -5100,6 +5122,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let isTaken = Inst{12}; } @@ -5107,7 +5132,7 @@ def J2_jumprltez : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32<=#0) jump:nt $Ii", -tc_b324366f, TypeCR>, Enc_0fa531 { +tc_73043bf4, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000111; @@ -5115,6 +5140,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let isTaken = Inst{12}; } @@ -5122,7 +5150,7 @@ def J2_jumprltezpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32<=#0) jump:t $Ii", -tc_b324366f, TypeCR>, Enc_0fa531 { +tc_73043bf4, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000111; @@ -5130,6 +5158,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let isTaken = Inst{12}; } @@ -5137,7 +5168,7 @@ def J2_jumprnz : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32==#0) jump:nt $Ii", -tc_b324366f, TypeCR>, Enc_0fa531 { +tc_73043bf4, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000110; @@ -5145,6 +5176,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let isTaken = Inst{12}; } @@ -5152,7 +5186,7 @@ def J2_jumprnzpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32==#0) jump:t $Ii", -tc_b324366f, TypeCR>, Enc_0fa531 { +tc_73043bf4, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000110; @@ -5160,6 +5194,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let isTaken = Inst{12}; } @@ -5167,7 +5204,7 @@ def J2_jumprt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) jumpr:nt $Rs32", -tc_07ac815d, TypeJ>, Enc_88d4d9, PredNewRel { +tc_e0739b8c, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010011010; @@ -5185,7 +5222,7 @@ def J2_jumprt_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) jumpr $Rs32", -tc_07ac815d, TypeMAPPING>, Requires<[HasV60T]> { +tc_e0739b8c, TypeMAPPING>, Requires<[HasV60T]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5193,7 +5230,7 @@ def J2_jumprtnew : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) jumpr:nt $Rs32", -tc_1f9668cc, TypeJ>, Enc_88d4d9, PredNewRel { +tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0010; let Inst{31-21} = 0b01010011010; @@ -5201,8 +5238,8 @@ let isPredicated = 1; let isTerminator = 1; let isIndirectBranch = 1; let isBranch = 1; -let cofMax1 = 1; let isPredicatedNew = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "reg"; let BaseOpcode = "J2_jumpr"; @@ -5212,7 +5249,7 @@ def J2_jumprtnewpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) jumpr:t $Rs32", -tc_1f9668cc, TypeJ>, Enc_88d4d9, PredNewRel { +tc_181af5d0, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0110; let Inst{31-21} = 0b01010011010; @@ -5220,8 +5257,8 @@ let isPredicated = 1; let isTerminator = 1; let isIndirectBranch = 1; let isBranch = 1; -let cofMax1 = 1; let isPredicatedNew = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "reg"; let BaseOpcode = "J2_jumpr"; @@ -5231,7 +5268,7 @@ def J2_jumprtpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) jumpr:t $Rs32", -tc_a1fb80e1, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel { +tc_97743097, TypeJ>, Enc_88d4d9, Requires<[HasV60T]>, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0100; let Inst{31-21} = 0b01010011010; @@ -5249,7 +5286,7 @@ def J2_jumprz : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32!=#0) jump:nt $Ii", -tc_b324366f, TypeCR>, Enc_0fa531 { +tc_73043bf4, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000100; @@ -5257,6 +5294,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let isTaken = Inst{12}; } @@ -5264,7 +5304,7 @@ def J2_jumprzpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32!=#0) jump:t $Ii", -tc_b324366f, TypeCR>, Enc_0fa531 { +tc_73043bf4, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000100; @@ -5272,6 +5312,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let isTaken = Inst{12}; } @@ -5279,7 +5322,7 @@ def J2_jumpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4) jump:nt $Ii", -tc_1b834fe7, TypeJ>, Enc_daea09, PredNewRel { +tc_e9fae2d6, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b0; @@ -5287,6 +5330,9 @@ let Inst{31-24} = 0b01011100; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "imm"; let BaseOpcode = "J2_jump"; @@ -5301,7 +5347,7 @@ def J2_jumpt_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, b15_2Imm:$Ii), "if ($Pu4) jump $Ii", -tc_1b834fe7, TypeMAPPING>, Requires<[HasV60T]> { +tc_e9fae2d6, TypeMAPPING>, Requires<[HasV60T]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5309,7 +5355,7 @@ def J2_jumptnew : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4.new) jump:nt $Ii", -tc_537e2013, TypeJ>, Enc_daea09, PredNewRel { +tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b010; let Inst{21-21} = 0b0; @@ -5318,6 +5364,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "imm"; let BaseOpcode = "J2_jump"; @@ -5332,7 +5381,7 @@ def J2_jumptnewpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4.new) jump:t $Ii", -tc_537e2013, TypeJ>, Enc_daea09, PredNewRel { +tc_a46f0df5, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b110; let Inst{21-21} = 0b0; @@ -5341,6 +5390,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "imm"; let BaseOpcode = "J2_jump"; @@ -5355,7 +5407,7 @@ def J2_jumptpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4) jump:t $Ii", -tc_b5bfaa60, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel { +tc_e1e99bfa, TypeJ>, Enc_daea09, Requires<[HasV60T]>, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b100; let Inst{21-21} = 0b0; @@ -5363,6 +5415,9 @@ let Inst{31-24} = 0b01011100; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let InputType = "imm"; let BaseOpcode = "J2_jump"; @@ -5377,10 +5432,12 @@ def J2_loop0i : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "loop0($Ii,#$II)", -tc_1000eb10, TypeCR>, Enc_4dc228 { +tc_cf59f215, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001000; +let cofRelax1 = 1; +let cofRelax2 = 1; let Defs = [LC0, SA0, USR]; let isExtendable = 1; let opExtendable = 0; @@ -5392,11 +5449,13 @@ def J2_loop0r : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "loop0($Ii,$Rs32)", -tc_f055fbb6, TypeCR>, Enc_864a5a { +tc_7934b9df, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01100000000; +let cofRelax1 = 1; +let cofRelax2 = 1; let Defs = [LC0, SA0, USR]; let isExtendable = 1; let opExtendable = 0; @@ -5408,10 +5467,12 @@ def J2_loop1i : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "loop1($Ii,#$II)", -tc_1000eb10, TypeCR>, Enc_4dc228 { +tc_cf59f215, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001001; +let cofRelax1 = 1; +let cofRelax2 = 1; let Defs = [LC1, SA1]; let isExtendable = 1; let opExtendable = 0; @@ -5423,11 +5484,13 @@ def J2_loop1r : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "loop1($Ii,$Rs32)", -tc_f055fbb6, TypeCR>, Enc_864a5a { +tc_7934b9df, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01100000001; +let cofRelax1 = 1; +let cofRelax2 = 1; let Defs = [LC1, SA1]; let isExtendable = 1; let opExtendable = 0; @@ -5439,7 +5502,7 @@ def J2_pause : HInst< (outs), (ins u8_0Imm:$Ii), "pause(#$Ii)", -tc_b189ad4c, TypeJ>, Enc_a51a9a { +tc_681a2300, TypeJ>, Enc_a51a9a { let Inst{1-0} = 0b00; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5450,11 +5513,13 @@ def J2_ploop1si : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "p3 = sp1loop0($Ii,#$II)", -tc_feb4974b, TypeCR>, Enc_4dc228 { +tc_c5e2426d, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001101; let isPredicateLate = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; let Defs = [LC0, P3, SA0, USR]; let isExtendable = 1; let opExtendable = 0; @@ -5466,12 +5531,14 @@ def J2_ploop1sr : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "p3 = sp1loop0($Ii,$Rs32)", -tc_d6a805a8, TypeCR>, Enc_864a5a { +tc_4f7cd700, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01100000101; let isPredicateLate = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; let Defs = [LC0, P3, SA0, USR]; let isExtendable = 1; let opExtendable = 0; @@ -5483,11 +5550,13 @@ def J2_ploop2si : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "p3 = sp2loop0($Ii,#$II)", -tc_feb4974b, TypeCR>, Enc_4dc228 { +tc_c5e2426d, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001110; let isPredicateLate = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; let Defs = [LC0, P3, SA0, USR]; let isExtendable = 1; let opExtendable = 0; @@ -5499,12 +5568,14 @@ def J2_ploop2sr : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "p3 = sp2loop0($Ii,$Rs32)", -tc_d6a805a8, TypeCR>, Enc_864a5a { +tc_4f7cd700, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01100000110; let isPredicateLate = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; let Defs = [LC0, P3, SA0, USR]; let isExtendable = 1; let opExtendable = 0; @@ -5516,11 +5587,13 @@ def J2_ploop3si : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "p3 = sp3loop0($Ii,#$II)", -tc_feb4974b, TypeCR>, Enc_4dc228 { +tc_c5e2426d, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001111; let isPredicateLate = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; let Defs = [LC0, P3, SA0, USR]; let isExtendable = 1; let opExtendable = 0; @@ -5532,12 +5605,14 @@ def J2_ploop3sr : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "p3 = sp3loop0($Ii,$Rs32)", -tc_d6a805a8, TypeCR>, Enc_864a5a { +tc_4f7cd700, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01100000111; let isPredicateLate = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; let Defs = [LC0, P3, SA0, USR]; let isExtendable = 1; let opExtendable = 0; @@ -5549,7 +5624,7 @@ def J2_trap0 : HInst< (outs), (ins u8_0Imm:$Ii), "trap0(#$Ii)", -tc_cbe45117, TypeJ>, Enc_a51a9a { +tc_14cd4cfa, TypeJ>, Enc_a51a9a { let Inst{1-0} = 0b00; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5560,7 +5635,7 @@ def J4_cmpeq_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -5569,8 +5644,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqr"; let isTaken = Inst{13}; @@ -5585,7 +5661,7 @@ def J4_cmpeq_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -5594,8 +5670,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqr"; let isTaken = Inst{13}; @@ -5610,7 +5687,7 @@ def J4_cmpeq_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010001; @@ -5619,6 +5696,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqp0"; @@ -5633,7 +5713,7 @@ def J4_cmpeq_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010001; @@ -5642,6 +5722,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqp0"; @@ -5656,7 +5739,7 @@ def J4_cmpeq_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010001; @@ -5665,6 +5748,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqp1"; @@ -5679,7 +5765,7 @@ def J4_cmpeq_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010001; @@ -5688,6 +5774,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqp1"; @@ -5702,7 +5791,7 @@ def J4_cmpeq_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -5710,8 +5799,9 @@ let Inst{31-22} = 0b0010000000; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqr"; let isTaken = Inst{13}; @@ -5726,7 +5816,7 @@ def J4_cmpeq_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -5734,8 +5824,9 @@ let Inst{31-22} = 0b0010000000; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqr"; let isTaken = Inst{13}; @@ -5750,7 +5841,7 @@ def J4_cmpeq_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010000; @@ -5758,6 +5849,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqp0"; @@ -5772,7 +5866,7 @@ def J4_cmpeq_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010000; @@ -5780,6 +5874,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqp0"; @@ -5794,7 +5891,7 @@ def J4_cmpeq_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010000; @@ -5802,6 +5899,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqp1"; @@ -5816,7 +5916,7 @@ def J4_cmpeq_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010000; @@ -5824,6 +5924,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqp1"; @@ -5838,7 +5941,7 @@ def J4_cmpeqi_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -5847,8 +5950,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqi"; let isTaken = Inst{13}; @@ -5863,7 +5967,7 @@ def J4_cmpeqi_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -5872,8 +5976,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqi"; let isTaken = Inst{13}; @@ -5888,7 +5993,7 @@ def J4_cmpeqi_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000001; @@ -5897,6 +6002,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqip0"; @@ -5911,7 +6019,7 @@ def J4_cmpeqi_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000001; @@ -5920,6 +6028,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqip0"; @@ -5934,7 +6045,7 @@ def J4_cmpeqi_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001001; @@ -5943,6 +6054,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqip1"; @@ -5957,7 +6071,7 @@ def J4_cmpeqi_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001001; @@ -5966,6 +6080,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqip1"; @@ -5980,7 +6097,7 @@ def J4_cmpeqi_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -5988,8 +6105,9 @@ let Inst{31-22} = 0b0010010000; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqi"; let isTaken = Inst{13}; @@ -6004,7 +6122,7 @@ def J4_cmpeqi_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$II)) jump:t $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6012,8 +6130,9 @@ let Inst{31-22} = 0b0010010000; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqi"; let isTaken = Inst{13}; @@ -6028,7 +6147,7 @@ def J4_cmpeqi_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000000; @@ -6036,6 +6155,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqip0"; @@ -6050,7 +6172,7 @@ def J4_cmpeqi_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000000; @@ -6058,6 +6180,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqip0"; @@ -6072,7 +6197,7 @@ def J4_cmpeqi_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001000; @@ -6080,6 +6205,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqip1"; @@ -6094,7 +6222,7 @@ def J4_cmpeqi_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001000; @@ -6102,6 +6230,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqip1"; @@ -6116,7 +6247,7 @@ def J4_cmpeqn1_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", -tc_09faec3b, TypeNCJ>, Enc_e90a15, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_e90a15, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -6125,8 +6256,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqn1r"; let isTaken = Inst{13}; @@ -6141,7 +6273,7 @@ def J4_cmpeqn1_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii", -tc_09faec3b, TypeNCJ>, Enc_5a18b3, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_5a18b3, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -6150,8 +6282,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqn1r"; let isTaken = Inst{13}; @@ -6166,7 +6299,7 @@ def J4_cmpeqn1_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_1de724, PredRel { +tc_99be14ca, TypeCJ>, Enc_1de724, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001000111; @@ -6175,6 +6308,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqn1p0"; @@ -6189,7 +6325,7 @@ def J4_cmpeqn1_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14640c, PredRel { +tc_99be14ca, TypeCJ>, Enc_14640c, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001000111; @@ -6198,6 +6334,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqn1p0"; @@ -6212,7 +6351,7 @@ def J4_cmpeqn1_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_668704, PredRel { +tc_99be14ca, TypeCJ>, Enc_668704, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001001111; @@ -6221,6 +6360,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqn1p1"; @@ -6235,7 +6377,7 @@ def J4_cmpeqn1_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_800e04, PredRel { +tc_99be14ca, TypeCJ>, Enc_800e04, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001001111; @@ -6244,6 +6386,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqn1p1"; @@ -6258,7 +6403,7 @@ def J4_cmpeqn1_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", -tc_09faec3b, TypeNCJ>, Enc_4aca3a, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_4aca3a, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -6266,8 +6411,9 @@ let Inst{31-22} = 0b0010011000; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqn1r"; let isTaken = Inst{13}; @@ -6282,7 +6428,7 @@ def J4_cmpeqn1_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii", -tc_09faec3b, TypeNCJ>, Enc_f7ea77, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_f7ea77, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -6290,8 +6436,9 @@ let Inst{31-22} = 0b0010011000; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpeqn1r"; let isTaken = Inst{13}; @@ -6306,7 +6453,7 @@ def J4_cmpeqn1_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_405228, PredRel { +tc_99be14ca, TypeCJ>, Enc_405228, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001000110; @@ -6314,6 +6461,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqn1p0"; @@ -6328,7 +6478,7 @@ def J4_cmpeqn1_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_3a2484, PredRel { +tc_99be14ca, TypeCJ>, Enc_3a2484, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001000110; @@ -6336,6 +6486,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpeqn1p0"; @@ -6350,7 +6503,7 @@ def J4_cmpeqn1_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_736575, PredRel { +tc_99be14ca, TypeCJ>, Enc_736575, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001001110; @@ -6358,6 +6511,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqn1p1"; @@ -6372,7 +6528,7 @@ def J4_cmpeqn1_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_8e583a, PredRel { +tc_99be14ca, TypeCJ>, Enc_8e583a, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001001110; @@ -6380,6 +6536,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpeqn1p1"; @@ -6394,7 +6553,7 @@ def J4_cmpgt_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6403,8 +6562,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtr"; let isTaken = Inst{13}; @@ -6419,7 +6579,7 @@ def J4_cmpgt_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6428,8 +6588,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtr"; let isTaken = Inst{13}; @@ -6444,7 +6605,7 @@ def J4_cmpgt_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010011; @@ -6453,6 +6614,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtp0"; @@ -6467,7 +6631,7 @@ def J4_cmpgt_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010011; @@ -6476,6 +6640,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtp0"; @@ -6490,7 +6657,7 @@ def J4_cmpgt_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010011; @@ -6499,6 +6666,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtp1"; @@ -6513,7 +6683,7 @@ def J4_cmpgt_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010011; @@ -6522,6 +6692,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtp1"; @@ -6536,7 +6709,7 @@ def J4_cmpgt_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6544,8 +6717,9 @@ let Inst{31-22} = 0b0010000010; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtr"; let isTaken = Inst{13}; @@ -6560,7 +6734,7 @@ def J4_cmpgt_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6568,8 +6742,9 @@ let Inst{31-22} = 0b0010000010; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtr"; let isTaken = Inst{13}; @@ -6584,7 +6759,7 @@ def J4_cmpgt_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010010; @@ -6592,6 +6767,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtp0"; @@ -6606,7 +6784,7 @@ def J4_cmpgt_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010010; @@ -6614,6 +6792,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtp0"; @@ -6628,7 +6809,7 @@ def J4_cmpgt_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010010; @@ -6636,6 +6817,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtp1"; @@ -6650,7 +6834,7 @@ def J4_cmpgt_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010010; @@ -6658,6 +6842,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtp1"; @@ -6672,7 +6859,7 @@ def J4_cmpgti_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6681,8 +6868,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtir"; let isTaken = Inst{13}; @@ -6697,7 +6885,7 @@ def J4_cmpgti_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6706,8 +6894,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtir"; let isTaken = Inst{13}; @@ -6722,7 +6911,7 @@ def J4_cmpgti_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000011; @@ -6731,6 +6920,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtip0"; @@ -6745,7 +6937,7 @@ def J4_cmpgti_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000011; @@ -6754,6 +6946,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtip0"; @@ -6768,7 +6963,7 @@ def J4_cmpgti_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001011; @@ -6777,6 +6972,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtip1"; @@ -6791,7 +6989,7 @@ def J4_cmpgti_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001011; @@ -6800,6 +6998,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtip1"; @@ -6814,7 +7015,7 @@ def J4_cmpgti_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6822,8 +7023,9 @@ let Inst{31-22} = 0b0010010010; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtir"; let isTaken = Inst{13}; @@ -6838,7 +7040,7 @@ def J4_cmpgti_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$II)) jump:t $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6846,8 +7048,9 @@ let Inst{31-22} = 0b0010010010; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtir"; let isTaken = Inst{13}; @@ -6862,7 +7065,7 @@ def J4_cmpgti_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000010; @@ -6870,6 +7073,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtip0"; @@ -6884,7 +7090,7 @@ def J4_cmpgti_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000010; @@ -6892,6 +7098,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtip0"; @@ -6906,7 +7115,7 @@ def J4_cmpgti_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001010; @@ -6914,6 +7123,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtip1"; @@ -6928,7 +7140,7 @@ def J4_cmpgti_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001010; @@ -6936,6 +7148,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtip1"; @@ -6950,7 +7165,7 @@ def J4_cmpgtn1_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", -tc_09faec3b, TypeNCJ>, Enc_3694bd, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_3694bd, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -6959,8 +7174,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtn1r"; let isTaken = Inst{13}; @@ -6975,7 +7191,7 @@ def J4_cmpgtn1_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii", -tc_09faec3b, TypeNCJ>, Enc_a6853f, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_a6853f, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -6984,8 +7200,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtn1r"; let isTaken = Inst{13}; @@ -7000,7 +7217,7 @@ def J4_cmpgtn1_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_a42857, PredRel { +tc_99be14ca, TypeCJ>, Enc_a42857, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001000111; @@ -7009,6 +7226,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtn1p0"; @@ -7023,7 +7243,7 @@ def J4_cmpgtn1_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_f6fe0b, PredRel { +tc_99be14ca, TypeCJ>, Enc_f6fe0b, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001000111; @@ -7032,6 +7252,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtn1p0"; @@ -7046,7 +7269,7 @@ def J4_cmpgtn1_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_3e3989, PredRel { +tc_99be14ca, TypeCJ>, Enc_3e3989, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001001111; @@ -7055,6 +7278,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtn1p1"; @@ -7069,7 +7295,7 @@ def J4_cmpgtn1_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_b909d2, PredRel { +tc_99be14ca, TypeCJ>, Enc_b909d2, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001001111; @@ -7078,6 +7304,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtn1p1"; @@ -7092,7 +7321,7 @@ def J4_cmpgtn1_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", -tc_09faec3b, TypeNCJ>, Enc_f82302, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_f82302, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -7100,8 +7329,9 @@ let Inst{31-22} = 0b0010011010; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtn1r"; let isTaken = Inst{13}; @@ -7116,7 +7346,7 @@ def J4_cmpgtn1_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii", -tc_09faec3b, TypeNCJ>, Enc_6413b6, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_6413b6, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -7124,8 +7354,9 @@ let Inst{31-22} = 0b0010011010; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtn1r"; let isTaken = Inst{13}; @@ -7140,7 +7371,7 @@ def J4_cmpgtn1_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_b78edd, PredRel { +tc_99be14ca, TypeCJ>, Enc_b78edd, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001000110; @@ -7148,6 +7379,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtn1p0"; @@ -7162,7 +7396,7 @@ def J4_cmpgtn1_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_041d7b, PredRel { +tc_99be14ca, TypeCJ>, Enc_041d7b, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001000110; @@ -7170,6 +7404,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtn1p0"; @@ -7184,7 +7421,7 @@ def J4_cmpgtn1_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_b1e1fb, PredRel { +tc_99be14ca, TypeCJ>, Enc_b1e1fb, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001001110; @@ -7192,6 +7429,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtn1p1"; @@ -7206,7 +7446,7 @@ def J4_cmpgtn1_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_178717, PredRel { +tc_99be14ca, TypeCJ>, Enc_178717, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001001110; @@ -7214,6 +7454,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtn1p1"; @@ -7228,7 +7471,7 @@ def J4_cmpgtu_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7237,8 +7480,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtur"; let isTaken = Inst{13}; @@ -7253,7 +7497,7 @@ def J4_cmpgtu_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7262,8 +7506,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtur"; let isTaken = Inst{13}; @@ -7278,7 +7523,7 @@ def J4_cmpgtu_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010101; @@ -7287,6 +7532,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtup0"; @@ -7301,7 +7549,7 @@ def J4_cmpgtu_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010101; @@ -7310,6 +7558,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtup0"; @@ -7324,7 +7575,7 @@ def J4_cmpgtu_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010101; @@ -7333,6 +7584,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtup1"; @@ -7347,7 +7601,7 @@ def J4_cmpgtu_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010101; @@ -7356,6 +7610,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtup1"; @@ -7370,7 +7627,7 @@ def J4_cmpgtu_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7378,8 +7635,9 @@ let Inst{31-22} = 0b0010000100; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtur"; let isTaken = Inst{13}; @@ -7394,7 +7652,7 @@ def J4_cmpgtu_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", -tc_580a779c, TypeNCJ>, Enc_c9a18e, PredRel { +tc_51b866be, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7402,8 +7660,9 @@ let Inst{31-22} = 0b0010000100; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtur"; let isTaken = Inst{13}; @@ -7418,7 +7677,7 @@ def J4_cmpgtu_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010100; @@ -7426,6 +7685,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtup0"; @@ -7440,7 +7702,7 @@ def J4_cmpgtu_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010100; @@ -7448,6 +7710,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtup0"; @@ -7462,7 +7727,7 @@ def J4_cmpgtu_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010100; @@ -7470,6 +7735,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtup1"; @@ -7484,7 +7752,7 @@ def J4_cmpgtu_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii", -tc_92d1833c, TypeCJ>, Enc_6a5972, PredRel { +tc_855b0b61, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010100; @@ -7492,6 +7760,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtup1"; @@ -7506,7 +7777,7 @@ def J4_cmpgtui_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7515,8 +7786,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtuir"; let isTaken = Inst{13}; @@ -7531,7 +7803,7 @@ def J4_cmpgtui_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7540,8 +7812,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtuir"; let isTaken = Inst{13}; @@ -7556,7 +7829,7 @@ def J4_cmpgtui_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000101; @@ -7565,6 +7838,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtuip0"; @@ -7579,7 +7855,7 @@ def J4_cmpgtui_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000101; @@ -7588,6 +7864,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtuip0"; @@ -7602,7 +7881,7 @@ def J4_cmpgtui_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001101; @@ -7611,6 +7890,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtuip1"; @@ -7625,7 +7907,7 @@ def J4_cmpgtui_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001101; @@ -7634,6 +7916,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtuip1"; @@ -7648,7 +7933,7 @@ def J4_cmpgtui_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7656,8 +7941,9 @@ let Inst{31-22} = 0b0010010100; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtuir"; let isTaken = Inst{13}; @@ -7672,7 +7958,7 @@ def J4_cmpgtui_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii", -tc_09faec3b, TypeNCJ>, Enc_eafd18, PredRel { +tc_bde7aaf4, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7680,8 +7966,9 @@ let Inst{31-22} = 0b0010010100; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpgtuir"; let isTaken = Inst{13}; @@ -7696,7 +7983,7 @@ def J4_cmpgtui_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000100; @@ -7704,6 +7991,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtuip0"; @@ -7718,7 +8008,7 @@ def J4_cmpgtui_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000100; @@ -7726,6 +8016,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let BaseOpcode = "J4_cmpgtuip0"; @@ -7740,7 +8033,7 @@ def J4_cmpgtui_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001100; @@ -7748,6 +8041,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtuip1"; @@ -7762,7 +8058,7 @@ def J4_cmpgtui_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii", -tc_d108a090, TypeCJ>, Enc_14d27a, PredRel { +tc_99be14ca, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001100; @@ -7770,6 +8066,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let BaseOpcode = "J4_cmpgtuip1"; @@ -7784,7 +8083,7 @@ def J4_cmplt_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", -tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel { +tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7793,8 +8092,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpltr"; let isTaken = Inst{13}; @@ -7809,7 +8109,7 @@ def J4_cmplt_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", -tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel { +tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7818,8 +8118,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpltr"; let isTaken = Inst{13}; @@ -7834,7 +8135,7 @@ def J4_cmplt_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", -tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel { +tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7842,8 +8143,9 @@ let Inst{31-22} = 0b0010000110; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpltr"; let isTaken = Inst{13}; @@ -7858,7 +8160,7 @@ def J4_cmplt_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", -tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel { +tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7866,8 +8168,9 @@ let Inst{31-22} = 0b0010000110; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpltr"; let isTaken = Inst{13}; @@ -7882,7 +8185,7 @@ def J4_cmpltu_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", -tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel { +tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7891,8 +8194,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpltur"; let isTaken = Inst{13}; @@ -7907,7 +8211,7 @@ def J4_cmpltu_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", -tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel { +tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7916,8 +8220,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpltur"; let isTaken = Inst{13}; @@ -7932,7 +8237,7 @@ def J4_cmpltu_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", -tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel { +tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7940,8 +8245,9 @@ let Inst{31-22} = 0b0010001000; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpltur"; let isTaken = Inst{13}; @@ -7956,7 +8262,7 @@ def J4_cmpltu_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", -tc_3e61d314, TypeNCJ>, Enc_5de85f, PredRel { +tc_5eb851fc, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7964,8 +8270,9 @@ let Inst{31-22} = 0b0010001000; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let BaseOpcode = "J4_cmpltur"; let isTaken = Inst{13}; @@ -7980,7 +8287,7 @@ def J4_hintjumpr : HInst< (outs), (ins IntRegs:$Rs32), "hintjr($Rs32)", -tc_b08b653e, TypeJ>, Enc_ecbcc8 { +tc_9faf76ae, TypeJ>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010010101; let isTerminator = 1; @@ -7992,13 +8299,15 @@ def J4_jumpseti : HInst< (outs GeneralSubRegs:$Rd16), (ins u6_0Imm:$II, b30_2Imm:$Ii), "$Rd16 = #$II ; jump $Ii", -tc_1e062b18, TypeCJ>, Enc_9e4c3f { +tc_49eb22c8, TypeCJ>, Enc_9e4c3f { let Inst{0-0} = 0b0; let Inst{31-22} = 0b0001011000; let hasNewValue = 1; let opNewValue = 0; let isTerminator = 1; let isBranch = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let isExtendable = 1; let opExtendable = 2; @@ -8010,7 +8319,7 @@ def J4_jumpsetr : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "$Rd16 = $Rs16 ; jump $Ii", -tc_1e062b18, TypeCJ>, Enc_66bce1 { +tc_49eb22c8, TypeCJ>, Enc_66bce1 { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001011100; @@ -8018,6 +8327,8 @@ let hasNewValue = 1; let opNewValue = 0; let isTerminator = 1; let isBranch = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Defs = [PC]; let isExtendable = 1; let opExtendable = 2; @@ -8029,7 +8340,7 @@ def J4_tstbit0_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (!tstbit($Ns8.new,#0)) jump:nt $Ii", -tc_dbe218dd, TypeNCJ>, Enc_69d63b { +tc_746baa8e, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -8038,8 +8349,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let isTaken = Inst{13}; let isExtendable = 1; @@ -8053,7 +8365,7 @@ def J4_tstbit0_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (!tstbit($Ns8.new,#0)) jump:t $Ii", -tc_dbe218dd, TypeNCJ>, Enc_69d63b { +tc_746baa8e, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -8062,8 +8374,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let isTaken = Inst{13}; let isExtendable = 1; @@ -8077,7 +8390,7 @@ def J4_tstbit0_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii", -tc_eb07ef6f, TypeCJ>, Enc_ad1c74 { +tc_3cb8ea06, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001000111; @@ -8086,6 +8399,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let isTaken = Inst{13}; @@ -8099,7 +8415,7 @@ def J4_tstbit0_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii", -tc_eb07ef6f, TypeCJ>, Enc_ad1c74 { +tc_3cb8ea06, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001000111; @@ -8108,6 +8424,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let isTaken = Inst{13}; @@ -8121,7 +8440,7 @@ def J4_tstbit0_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii", -tc_eb07ef6f, TypeCJ>, Enc_ad1c74 { +tc_3cb8ea06, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001001111; @@ -8130,6 +8449,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let isTaken = Inst{13}; @@ -8143,7 +8465,7 @@ def J4_tstbit0_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii", -tc_eb07ef6f, TypeCJ>, Enc_ad1c74 { +tc_3cb8ea06, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001001111; @@ -8152,6 +8474,9 @@ let isPredicatedFalse = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let isTaken = Inst{13}; @@ -8165,7 +8490,7 @@ def J4_tstbit0_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (tstbit($Ns8.new,#0)) jump:nt $Ii", -tc_dbe218dd, TypeNCJ>, Enc_69d63b { +tc_746baa8e, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -8173,8 +8498,9 @@ let Inst{31-22} = 0b0010010110; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let isTaken = Inst{13}; let isExtendable = 1; @@ -8188,7 +8514,7 @@ def J4_tstbit0_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (tstbit($Ns8.new,#0)) jump:t $Ii", -tc_dbe218dd, TypeNCJ>, Enc_69d63b { +tc_746baa8e, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -8196,8 +8522,9 @@ let Inst{31-22} = 0b0010010110; let isPredicated = 1; let isTerminator = 1; let isBranch = 1; -let cofMax1 = 1; let isNewValue = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let Defs = [PC]; let isTaken = Inst{13}; let isExtendable = 1; @@ -8211,7 +8538,7 @@ def J4_tstbit0_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii", -tc_eb07ef6f, TypeCJ>, Enc_ad1c74 { +tc_3cb8ea06, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001000110; @@ -8219,6 +8546,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let isTaken = Inst{13}; @@ -8232,7 +8562,7 @@ def J4_tstbit0_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii", -tc_eb07ef6f, TypeCJ>, Enc_ad1c74 { +tc_3cb8ea06, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001000110; @@ -8240,6 +8570,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P0]; let Defs = [P0, PC]; let isTaken = Inst{13}; @@ -8253,7 +8586,7 @@ def J4_tstbit0_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii", -tc_eb07ef6f, TypeCJ>, Enc_ad1c74 { +tc_3cb8ea06, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001001110; @@ -8261,6 +8594,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let isTaken = Inst{13}; @@ -8274,7 +8610,7 @@ def J4_tstbit0_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii", -tc_eb07ef6f, TypeCJ>, Enc_ad1c74 { +tc_3cb8ea06, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001001110; @@ -8282,6 +8618,9 @@ let isPredicated = 1; let isTerminator = 1; let isBranch = 1; let isPredicatedNew = 1; +let cofRelax1 = 1; +let cofRelax2 = 1; +let cofMax1 = 1; let Uses = [P1]; let Defs = [P1, PC]; let isTaken = Inst{13}; @@ -8292,24 +8631,22 @@ let opExtentBits = 11; let opExtentAlign = 2; } def L2_deallocframe : HInst< -(outs), -(ins), -"deallocframe", -tc_c1dbc916, TypeLD>, Enc_3a3d62 { -let Inst{4-0} = 0b11110; +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = deallocframe($Rs32):raw", +tc_d1090e34, TypeLD>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10010000000; -let Inst{20-16} = 0b11110; let accessSize = DoubleWordAccess; let mayLoad = 1; -let Uses = [R30]; -let Defs = [R29, R30, R31]; +let Uses = [FRAMEKEY]; +let Defs = [R29]; } def L2_loadalignb_io : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Ryy32 = memb_fifo($Rs32+#$Ii)", -tc_14da557c, TypeLD>, Enc_a27588 { +tc_ef52ed71, TypeLD>, Enc_a27588 { let Inst{24-21} = 0b0100; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -8326,7 +8663,7 @@ def L2_loadalignb_pbr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++$Mu2:brev)", -tc_ae762521, TypeLD>, Enc_1f5d8f { +tc_bad2bcaf, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110100; let accessSize = ByteAccess; @@ -8337,7 +8674,7 @@ def L2_loadalignb_pci : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))", -tc_d2a33af5, TypeLD>, Enc_74aef2 { +tc_03220ffa, TypeLD>, Enc_74aef2 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000100; let addrMode = PostInc; @@ -8350,7 +8687,7 @@ def L2_loadalignb_pcr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))", -tc_ae762521, TypeLD>, Enc_1f5d8f { +tc_bad2bcaf, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000100; let addrMode = PostInc; @@ -8363,7 +8700,7 @@ def L2_loadalignb_pi : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii), "$Ryy32 = memb_fifo($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_6b197f { +tc_bad2bcaf, TypeLD>, Enc_6b197f { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010100; let addrMode = PostInc; @@ -8375,7 +8712,7 @@ def L2_loadalignb_pr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++$Mu2)", -tc_ae762521, TypeLD>, Enc_1f5d8f { +tc_bad2bcaf, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100100; let addrMode = PostInc; @@ -8387,7 +8724,7 @@ def L2_loadalignb_zomap : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), "$Ryy32 = memb_fifo($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let Constraints = "$Ryy32 = $Ryy32in"; @@ -8396,7 +8733,7 @@ def L2_loadalignh_io : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii), "$Ryy32 = memh_fifo($Rs32+#$Ii)", -tc_14da557c, TypeLD>, Enc_5cd7e9 { +tc_ef52ed71, TypeLD>, Enc_5cd7e9 { let Inst{24-21} = 0b0010; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -8413,7 +8750,7 @@ def L2_loadalignh_pbr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++$Mu2:brev)", -tc_ae762521, TypeLD>, Enc_1f5d8f { +tc_bad2bcaf, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110010; let accessSize = HalfWordAccess; @@ -8424,7 +8761,7 @@ def L2_loadalignh_pci : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))", -tc_d2a33af5, TypeLD>, Enc_9e2e1c { +tc_03220ffa, TypeLD>, Enc_9e2e1c { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000010; let addrMode = PostInc; @@ -8437,7 +8774,7 @@ def L2_loadalignh_pcr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))", -tc_ae762521, TypeLD>, Enc_1f5d8f { +tc_bad2bcaf, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000010; let addrMode = PostInc; @@ -8450,7 +8787,7 @@ def L2_loadalignh_pi : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii), "$Ryy32 = memh_fifo($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_bd1cbc { +tc_bad2bcaf, TypeLD>, Enc_bd1cbc { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010010; let addrMode = PostInc; @@ -8462,7 +8799,7 @@ def L2_loadalignh_pr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++$Mu2)", -tc_ae762521, TypeLD>, Enc_1f5d8f { +tc_bad2bcaf, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100010; let addrMode = PostInc; @@ -8474,7 +8811,7 @@ def L2_loadalignh_zomap : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), "$Ryy32 = memh_fifo($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let Constraints = "$Ryy32 = $Ryy32in"; @@ -8483,7 +8820,7 @@ def L2_loadbsw2_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = membh($Rs32+#$Ii)", -tc_bf6fa601, TypeLD>, Enc_de0214 { +tc_7f881c76, TypeLD>, Enc_de0214 { let Inst{24-21} = 0b0001; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -8501,7 +8838,7 @@ def L2_loadbsw2_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = membh($Rx32++$Mu2:brev)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110001; let hasNewValue = 1; @@ -8514,7 +8851,7 @@ def L2_loadbsw2_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = membh($Rx32++#$Ii:circ($Mu2))", -tc_3eab77bd, TypeLD>, Enc_e83554 { +tc_4403ca65, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000001; let hasNewValue = 1; @@ -8529,7 +8866,7 @@ def L2_loadbsw2_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = membh($Rx32++I:circ($Mu2))", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000001; let hasNewValue = 1; @@ -8544,7 +8881,7 @@ def L2_loadbsw2_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = membh($Rx32++#$Ii)", -tc_65dc7cc4, TypeLD>, Enc_152467 { +tc_2fc0c436, TypeLD>, Enc_152467 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010001; let hasNewValue = 1; @@ -8558,7 +8895,7 @@ def L2_loadbsw2_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = membh($Rx32++$Mu2)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100001; let hasNewValue = 1; @@ -8572,7 +8909,7 @@ def L2_loadbsw2_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = membh($Rs32)", -tc_bf6fa601, TypeMAPPING> { +tc_7f881c76, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -8582,7 +8919,7 @@ def L2_loadbsw4_io : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s30_2Imm:$Ii), "$Rdd32 = membh($Rs32+#$Ii)", -tc_bf6fa601, TypeLD>, Enc_2d7491 { +tc_7f881c76, TypeLD>, Enc_2d7491 { let Inst{24-21} = 0b0111; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -8598,7 +8935,7 @@ def L2_loadbsw4_pbr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++$Mu2:brev)", -tc_65dc7cc4, TypeLD>, Enc_7eee72 { +tc_2fc0c436, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110111; let accessSize = WordAccess; @@ -8609,7 +8946,7 @@ def L2_loadbsw4_pci : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))", -tc_3eab77bd, TypeLD>, Enc_70b24b { +tc_4403ca65, TypeLD>, Enc_70b24b { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000111; let addrMode = PostInc; @@ -8622,7 +8959,7 @@ def L2_loadbsw4_pcr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++I:circ($Mu2))", -tc_65dc7cc4, TypeLD>, Enc_7eee72 { +tc_2fc0c436, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000111; let addrMode = PostInc; @@ -8635,7 +8972,7 @@ def L2_loadbsw4_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii), "$Rdd32 = membh($Rx32++#$Ii)", -tc_65dc7cc4, TypeLD>, Enc_71f1b4 { +tc_2fc0c436, TypeLD>, Enc_71f1b4 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010111; let addrMode = PostInc; @@ -8647,7 +8984,7 @@ def L2_loadbsw4_pr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++$Mu2)", -tc_65dc7cc4, TypeLD>, Enc_7eee72 { +tc_2fc0c436, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100111; let addrMode = PostInc; @@ -8659,7 +8996,7 @@ def L2_loadbsw4_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = membh($Rs32)", -tc_bf6fa601, TypeMAPPING> { +tc_7f881c76, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -8667,7 +9004,7 @@ def L2_loadbzw2_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = memubh($Rs32+#$Ii)", -tc_bf6fa601, TypeLD>, Enc_de0214 { +tc_7f881c76, TypeLD>, Enc_de0214 { let Inst{24-21} = 0b0011; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -8685,7 +9022,7 @@ def L2_loadbzw2_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++$Mu2:brev)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110011; let hasNewValue = 1; @@ -8698,7 +9035,7 @@ def L2_loadbzw2_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))", -tc_3eab77bd, TypeLD>, Enc_e83554 { +tc_4403ca65, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000011; let hasNewValue = 1; @@ -8713,7 +9050,7 @@ def L2_loadbzw2_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++I:circ($Mu2))", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000011; let hasNewValue = 1; @@ -8728,7 +9065,7 @@ def L2_loadbzw2_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = memubh($Rx32++#$Ii)", -tc_65dc7cc4, TypeLD>, Enc_152467 { +tc_2fc0c436, TypeLD>, Enc_152467 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010011; let hasNewValue = 1; @@ -8742,7 +9079,7 @@ def L2_loadbzw2_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++$Mu2)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100011; let hasNewValue = 1; @@ -8756,7 +9093,7 @@ def L2_loadbzw2_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memubh($Rs32)", -tc_bf6fa601, TypeMAPPING> { +tc_7f881c76, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -8766,7 +9103,7 @@ def L2_loadbzw4_io : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s30_2Imm:$Ii), "$Rdd32 = memubh($Rs32+#$Ii)", -tc_bf6fa601, TypeLD>, Enc_2d7491 { +tc_7f881c76, TypeLD>, Enc_2d7491 { let Inst{24-21} = 0b0101; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -8782,7 +9119,7 @@ def L2_loadbzw4_pbr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++$Mu2:brev)", -tc_65dc7cc4, TypeLD>, Enc_7eee72 { +tc_2fc0c436, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110101; let accessSize = WordAccess; @@ -8793,7 +9130,7 @@ def L2_loadbzw4_pci : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))", -tc_3eab77bd, TypeLD>, Enc_70b24b { +tc_4403ca65, TypeLD>, Enc_70b24b { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000101; let addrMode = PostInc; @@ -8806,7 +9143,7 @@ def L2_loadbzw4_pcr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++I:circ($Mu2))", -tc_65dc7cc4, TypeLD>, Enc_7eee72 { +tc_2fc0c436, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000101; let addrMode = PostInc; @@ -8819,7 +9156,7 @@ def L2_loadbzw4_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii), "$Rdd32 = memubh($Rx32++#$Ii)", -tc_65dc7cc4, TypeLD>, Enc_71f1b4 { +tc_2fc0c436, TypeLD>, Enc_71f1b4 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010101; let addrMode = PostInc; @@ -8831,7 +9168,7 @@ def L2_loadbzw4_pr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++$Mu2)", -tc_65dc7cc4, TypeLD>, Enc_7eee72 { +tc_2fc0c436, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100101; let addrMode = PostInc; @@ -8843,7 +9180,7 @@ def L2_loadbzw4_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = memubh($Rs32)", -tc_bf6fa601, TypeMAPPING> { +tc_7f881c76, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -8851,7 +9188,7 @@ def L2_loadrb_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = memb($Rs32+#$Ii)", -tc_bf6fa601, TypeLD>, Enc_211aaa, AddrModeRel { +tc_7f881c76, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -8872,7 +9209,7 @@ def L2_loadrb_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memb($Rx32++$Mu2:brev)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111000; let hasNewValue = 1; @@ -8885,7 +9222,7 @@ def L2_loadrb_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memb($Rx32++#$Ii:circ($Mu2))", -tc_3eab77bd, TypeLD>, Enc_e0a47a { +tc_4403ca65, TypeLD>, Enc_e0a47a { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001000; let hasNewValue = 1; @@ -8900,7 +9237,7 @@ def L2_loadrb_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memb($Rx32++I:circ($Mu2))", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001000; let hasNewValue = 1; @@ -8915,7 +9252,7 @@ def L2_loadrb_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii), "$Rd32 = memb($Rx32++#$Ii)", -tc_65dc7cc4, TypeLD>, Enc_222336, PredNewRel { +tc_2fc0c436, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011000; let hasNewValue = 1; @@ -8923,6 +9260,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = ByteAccess; let mayLoad = 1; +let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_pi"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -8931,7 +9269,7 @@ def L2_loadrb_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memb($Rx32++$Mu2)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101000; let hasNewValue = 1; @@ -8945,7 +9283,7 @@ def L2_loadrb_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memb($Rs32)", -tc_bf6fa601, TypeMAPPING> { +tc_7f881c76, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -8955,7 +9293,7 @@ def L2_loadrbgp : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memb(gp+#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -8974,7 +9312,7 @@ def L2_loadrd_io : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s29_3Imm:$Ii), "$Rdd32 = memd($Rs32+#$Ii)", -tc_bf6fa601, TypeLD>, Enc_fa3ba4, AddrModeRel { +tc_7f881c76, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -8993,7 +9331,7 @@ def L2_loadrd_pbr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++$Mu2:brev)", -tc_65dc7cc4, TypeLD>, Enc_7eee72 { +tc_2fc0c436, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111110; let accessSize = DoubleWordAccess; @@ -9004,7 +9342,7 @@ def L2_loadrd_pci : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))", -tc_3eab77bd, TypeLD>, Enc_b05839 { +tc_4403ca65, TypeLD>, Enc_b05839 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001110; let addrMode = PostInc; @@ -9017,7 +9355,7 @@ def L2_loadrd_pcr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++I:circ($Mu2))", -tc_65dc7cc4, TypeLD>, Enc_7eee72 { +tc_2fc0c436, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001110; let addrMode = PostInc; @@ -9030,12 +9368,13 @@ def L2_loadrd_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii), "$Rdd32 = memd($Rx32++#$Ii)", -tc_65dc7cc4, TypeLD>, Enc_5bdd42, PredNewRel { +tc_2fc0c436, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011110; let addrMode = PostInc; let accessSize = DoubleWordAccess; let mayLoad = 1; +let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_pi"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -9044,7 +9383,7 @@ def L2_loadrd_pr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++$Mu2)", -tc_65dc7cc4, TypeLD>, Enc_7eee72 { +tc_2fc0c436, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101110; let addrMode = PostInc; @@ -9056,7 +9395,7 @@ def L2_loadrd_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = memd($Rs32)", -tc_bf6fa601, TypeMAPPING> { +tc_7f881c76, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -9064,7 +9403,7 @@ def L2_loadrdgp : HInst< (outs DoubleRegs:$Rdd32), (ins u29_3Imm:$Ii), "$Rdd32 = memd(gp+#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_509701, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_509701, AddrModeRel { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b01001; let accessSize = DoubleWordAccess; @@ -9081,7 +9420,7 @@ def L2_loadrh_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = memh($Rs32+#$Ii)", -tc_bf6fa601, TypeLD>, Enc_de0214, AddrModeRel { +tc_7f881c76, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9102,7 +9441,7 @@ def L2_loadrh_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memh($Rx32++$Mu2:brev)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111010; let hasNewValue = 1; @@ -9115,7 +9454,7 @@ def L2_loadrh_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memh($Rx32++#$Ii:circ($Mu2))", -tc_3eab77bd, TypeLD>, Enc_e83554 { +tc_4403ca65, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001010; let hasNewValue = 1; @@ -9130,7 +9469,7 @@ def L2_loadrh_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memh($Rx32++I:circ($Mu2))", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001010; let hasNewValue = 1; @@ -9145,7 +9484,7 @@ def L2_loadrh_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = memh($Rx32++#$Ii)", -tc_65dc7cc4, TypeLD>, Enc_152467, PredNewRel { +tc_2fc0c436, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011010; let hasNewValue = 1; @@ -9153,6 +9492,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayLoad = 1; +let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_pi"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -9161,7 +9501,7 @@ def L2_loadrh_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memh($Rx32++$Mu2)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101010; let hasNewValue = 1; @@ -9175,7 +9515,7 @@ def L2_loadrh_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memh($Rs32)", -tc_bf6fa601, TypeMAPPING> { +tc_7f881c76, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9185,7 +9525,7 @@ def L2_loadrhgp : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memh(gp+#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9204,7 +9544,7 @@ def L2_loadri_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s30_2Imm:$Ii), "$Rd32 = memw($Rs32+#$Ii)", -tc_bf6fa601, TypeLD>, Enc_2a3787, AddrModeRel { +tc_7f881c76, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9225,7 +9565,7 @@ def L2_loadri_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memw($Rx32++$Mu2:brev)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111100; let hasNewValue = 1; @@ -9238,7 +9578,7 @@ def L2_loadri_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memw($Rx32++#$Ii:circ($Mu2))", -tc_3eab77bd, TypeLD>, Enc_27fd0e { +tc_4403ca65, TypeLD>, Enc_27fd0e { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001100; let hasNewValue = 1; @@ -9253,7 +9593,7 @@ def L2_loadri_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memw($Rx32++I:circ($Mu2))", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001100; let hasNewValue = 1; @@ -9268,7 +9608,7 @@ def L2_loadri_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii), "$Rd32 = memw($Rx32++#$Ii)", -tc_65dc7cc4, TypeLD>, Enc_3d920a, PredNewRel { +tc_2fc0c436, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011100; let hasNewValue = 1; @@ -9276,6 +9616,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = WordAccess; let mayLoad = 1; +let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_pi"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -9284,7 +9625,7 @@ def L2_loadri_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memw($Rx32++$Mu2)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101100; let hasNewValue = 1; @@ -9298,7 +9639,7 @@ def L2_loadri_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memw($Rs32)", -tc_bf6fa601, TypeMAPPING> { +tc_7f881c76, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9308,7 +9649,7 @@ def L2_loadrigp : HInst< (outs IntRegs:$Rd32), (ins u30_2Imm:$Ii), "$Rd32 = memw(gp+#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9327,7 +9668,7 @@ def L2_loadrub_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = memub($Rs32+#$Ii)", -tc_bf6fa601, TypeLD>, Enc_211aaa, AddrModeRel { +tc_7f881c76, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1001; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9348,7 +9689,7 @@ def L2_loadrub_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memub($Rx32++$Mu2:brev)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111001; let hasNewValue = 1; @@ -9361,7 +9702,7 @@ def L2_loadrub_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memub($Rx32++#$Ii:circ($Mu2))", -tc_3eab77bd, TypeLD>, Enc_e0a47a { +tc_4403ca65, TypeLD>, Enc_e0a47a { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001001; let hasNewValue = 1; @@ -9376,7 +9717,7 @@ def L2_loadrub_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memub($Rx32++I:circ($Mu2))", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001001; let hasNewValue = 1; @@ -9391,7 +9732,7 @@ def L2_loadrub_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii), "$Rd32 = memub($Rx32++#$Ii)", -tc_65dc7cc4, TypeLD>, Enc_222336, PredNewRel { +tc_2fc0c436, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011001; let hasNewValue = 1; @@ -9399,6 +9740,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = ByteAccess; let mayLoad = 1; +let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_pi"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -9407,7 +9749,7 @@ def L2_loadrub_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memub($Rx32++$Mu2)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101001; let hasNewValue = 1; @@ -9421,7 +9763,7 @@ def L2_loadrub_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memub($Rs32)", -tc_bf6fa601, TypeMAPPING> { +tc_7f881c76, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9431,7 +9773,7 @@ def L2_loadrubgp : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memub(gp+#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1001; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9450,7 +9792,7 @@ def L2_loadruh_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = memuh($Rs32+#$Ii)", -tc_bf6fa601, TypeLD>, Enc_de0214, AddrModeRel { +tc_7f881c76, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9471,7 +9813,7 @@ def L2_loadruh_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++$Mu2:brev)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111011; let hasNewValue = 1; @@ -9484,7 +9826,7 @@ def L2_loadruh_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))", -tc_3eab77bd, TypeLD>, Enc_e83554 { +tc_4403ca65, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001011; let hasNewValue = 1; @@ -9499,7 +9841,7 @@ def L2_loadruh_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++I:circ($Mu2))", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001011; let hasNewValue = 1; @@ -9514,7 +9856,7 @@ def L2_loadruh_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = memuh($Rx32++#$Ii)", -tc_65dc7cc4, TypeLD>, Enc_152467, PredNewRel { +tc_2fc0c436, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011011; let hasNewValue = 1; @@ -9522,6 +9864,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayLoad = 1; +let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_pi"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -9530,7 +9873,7 @@ def L2_loadruh_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++$Mu2)", -tc_65dc7cc4, TypeLD>, Enc_74d4e5 { +tc_2fc0c436, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101011; let hasNewValue = 1; @@ -9544,7 +9887,7 @@ def L2_loadruh_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memuh($Rs32)", -tc_bf6fa601, TypeMAPPING> { +tc_7f881c76, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9554,7 +9897,7 @@ def L2_loadruhgp : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memuh(gp+#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9573,7 +9916,7 @@ def L2_loadw_locked : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memw_locked($Rs32)", -tc_29c14515, TypeLD>, Enc_5e2823 { +tc_6aa5711a, TypeLD>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10010010000; let hasNewValue = 1; @@ -9586,7 +9929,7 @@ def L2_ploadrbf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101000; let isPredicated = 1; @@ -9608,7 +9951,7 @@ def L2_ploadrbf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_f4413a, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -9625,7 +9968,7 @@ def L2_ploadrbf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memb($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9635,7 +9978,7 @@ def L2_ploadrbfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111000; let isPredicated = 1; @@ -9658,7 +10001,7 @@ def L2_ploadrbfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_f4413a, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -9676,7 +10019,7 @@ def L2_ploadrbfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memb($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9686,7 +10029,7 @@ def L2_ploadrbt_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memb($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001000; let isPredicated = 1; @@ -9707,7 +10050,7 @@ def L2_ploadrbt_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4) $Rd32 = memb($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_f4413a, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -9723,7 +10066,7 @@ def L2_ploadrbt_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memb($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9733,7 +10076,7 @@ def L2_ploadrbtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011000; let isPredicated = 1; @@ -9755,7 +10098,7 @@ def L2_ploadrbtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_f4413a, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -9772,7 +10115,7 @@ def L2_ploadrbtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memb($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9782,7 +10125,7 @@ def L2_ploadrdf_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101110; let isPredicated = 1; @@ -9802,7 +10145,7 @@ def L2_ploadrdf_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_9d1247, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -9817,7 +10160,7 @@ def L2_ploadrdf_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rdd32 = memd($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -9825,7 +10168,7 @@ def L2_ploadrdfnew_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111110; let isPredicated = 1; @@ -9846,7 +10189,7 @@ def L2_ploadrdfnew_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_9d1247, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -9862,7 +10205,7 @@ def L2_ploadrdfnew_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rdd32 = memd($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -9870,7 +10213,7 @@ def L2_ploadrdt_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001110; let isPredicated = 1; @@ -9889,7 +10232,7 @@ def L2_ploadrdt_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_9d1247, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -9903,7 +10246,7 @@ def L2_ploadrdt_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rdd32 = memd($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -9911,7 +10254,7 @@ def L2_ploadrdtnew_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011110; let isPredicated = 1; @@ -9931,7 +10274,7 @@ def L2_ploadrdtnew_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_9d1247, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -9946,7 +10289,7 @@ def L2_ploadrdtnew_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rdd32 = memd($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -9954,7 +10297,7 @@ def L2_ploadrhf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101010; let isPredicated = 1; @@ -9976,7 +10319,7 @@ def L2_ploadrhf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_733b27, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -9993,7 +10336,7 @@ def L2_ploadrhf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memh($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10003,7 +10346,7 @@ def L2_ploadrhfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111010; let isPredicated = 1; @@ -10026,7 +10369,7 @@ def L2_ploadrhfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_733b27, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -10044,7 +10387,7 @@ def L2_ploadrhfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memh($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10054,7 +10397,7 @@ def L2_ploadrht_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4) $Rd32 = memh($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001010; let isPredicated = 1; @@ -10075,7 +10418,7 @@ def L2_ploadrht_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4) $Rd32 = memh($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_733b27, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -10091,7 +10434,7 @@ def L2_ploadrht_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memh($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10101,7 +10444,7 @@ def L2_ploadrhtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011010; let isPredicated = 1; @@ -10123,7 +10466,7 @@ def L2_ploadrhtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_733b27, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -10140,7 +10483,7 @@ def L2_ploadrhtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memh($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10150,7 +10493,7 @@ def L2_ploadrif_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101100; let isPredicated = 1; @@ -10172,7 +10515,7 @@ def L2_ploadrif_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_b97f71, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10189,7 +10532,7 @@ def L2_ploadrif_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memw($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10199,7 +10542,7 @@ def L2_ploadrifnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111100; let isPredicated = 1; @@ -10222,7 +10565,7 @@ def L2_ploadrifnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_b97f71, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10240,7 +10583,7 @@ def L2_ploadrifnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memw($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10250,7 +10593,7 @@ def L2_ploadrit_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if ($Pt4) $Rd32 = memw($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001100; let isPredicated = 1; @@ -10271,7 +10614,7 @@ def L2_ploadrit_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if ($Pt4) $Rd32 = memw($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_b97f71, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10287,7 +10630,7 @@ def L2_ploadrit_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memw($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10297,7 +10640,7 @@ def L2_ploadritnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011100; let isPredicated = 1; @@ -10319,7 +10662,7 @@ def L2_ploadritnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_b97f71, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10336,7 +10679,7 @@ def L2_ploadritnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memw($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10346,7 +10689,7 @@ def L2_ploadrubf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101001; let isPredicated = 1; @@ -10368,7 +10711,7 @@ def L2_ploadrubf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_f4413a, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10385,7 +10728,7 @@ def L2_ploadrubf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memub($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10395,7 +10738,7 @@ def L2_ploadrubfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111001; let isPredicated = 1; @@ -10418,7 +10761,7 @@ def L2_ploadrubfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_f4413a, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10436,7 +10779,7 @@ def L2_ploadrubfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memub($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10446,7 +10789,7 @@ def L2_ploadrubt_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memub($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001001; let isPredicated = 1; @@ -10467,7 +10810,7 @@ def L2_ploadrubt_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4) $Rd32 = memub($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_f4413a, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10483,7 +10826,7 @@ def L2_ploadrubt_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memub($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10493,7 +10836,7 @@ def L2_ploadrubtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011001; let isPredicated = 1; @@ -10515,7 +10858,7 @@ def L2_ploadrubtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_f4413a, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10532,7 +10875,7 @@ def L2_ploadrubtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memub($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10542,7 +10885,7 @@ def L2_ploadruhf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101011; let isPredicated = 1; @@ -10564,7 +10907,7 @@ def L2_ploadruhf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_733b27, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -10581,7 +10924,7 @@ def L2_ploadruhf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memuh($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10591,7 +10934,7 @@ def L2_ploadruhfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111011; let isPredicated = 1; @@ -10614,7 +10957,7 @@ def L2_ploadruhfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_733b27, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -10632,7 +10975,7 @@ def L2_ploadruhfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memuh($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10642,7 +10985,7 @@ def L2_ploadruht_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)", -tc_14da557c, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_ef52ed71, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001011; let isPredicated = 1; @@ -10663,7 +11006,7 @@ def L2_ploadruht_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)", -tc_ae762521, TypeLD>, Enc_733b27, PredNewRel { +tc_bad2bcaf, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -10679,7 +11022,7 @@ def L2_ploadruht_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memuh($Rs32)", -tc_14da557c, TypeMAPPING> { +tc_ef52ed71, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10689,7 +11032,7 @@ def L2_ploadruhtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", -tc_65dc7cc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_2fc0c436, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011011; let isPredicated = 1; @@ -10711,7 +11054,7 @@ def L2_ploadruhtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", -tc_e578178f, TypeLD>, Enc_733b27, PredNewRel { +tc_63fe3df7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -10728,7 +11071,7 @@ def L2_ploadruhtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memuh($Rs32)", -tc_65dc7cc4, TypeMAPPING> { +tc_2fc0c436, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10738,13 +11081,14 @@ def L4_add_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) += $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_d44e31 { +tc_44126683, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -10756,7 +11100,7 @@ def L4_add_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) += $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10764,13 +11108,14 @@ def L4_add_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) += $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_163a3c { +tc_44126683, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -10782,7 +11127,7 @@ def L4_add_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) += $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10790,13 +11135,14 @@ def L4_add_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) += $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_226535 { +tc_44126683, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -10808,7 +11154,7 @@ def L4_add_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) += $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10816,13 +11162,14 @@ def L4_and_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) &= $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_d44e31 { +tc_44126683, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -10834,7 +11181,7 @@ def L4_and_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) &= $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10842,13 +11189,14 @@ def L4_and_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) &= $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_163a3c { +tc_44126683, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -10860,7 +11208,7 @@ def L4_and_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) &= $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10868,13 +11216,14 @@ def L4_and_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) &= $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_226535 { +tc_44126683, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -10886,7 +11235,7 @@ def L4_and_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) &= $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10894,13 +11243,14 @@ def L4_iadd_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) += #$II", -tc_da79106e, TypeV4LDST>, Enc_46c951 { +tc_44126683, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -10912,7 +11262,7 @@ def L4_iadd_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) += #$II", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10920,13 +11270,14 @@ def L4_iadd_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) += #$II", -tc_da79106e, TypeV4LDST>, Enc_e66a97 { +tc_44126683, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -10938,7 +11289,7 @@ def L4_iadd_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) += #$II", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10946,13 +11297,14 @@ def L4_iadd_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) += #$II", -tc_da79106e, TypeV4LDST>, Enc_84b2cd { +tc_44126683, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -10964,7 +11316,7 @@ def L4_iadd_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) += #$II", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10972,13 +11324,14 @@ def L4_iand_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) = clrbit(#$II)", -tc_da79106e, TypeV4LDST>, Enc_46c951 { +tc_44126683, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -10990,7 +11343,7 @@ def L4_iand_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) = clrbit(#$II)", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10998,13 +11351,14 @@ def L4_iand_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) = clrbit(#$II)", -tc_da79106e, TypeV4LDST>, Enc_e66a97 { +tc_44126683, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -11016,7 +11370,7 @@ def L4_iand_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) = clrbit(#$II)", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11024,13 +11378,14 @@ def L4_iand_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) = clrbit(#$II)", -tc_da79106e, TypeV4LDST>, Enc_84b2cd { +tc_44126683, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -11042,7 +11397,7 @@ def L4_iand_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) = clrbit(#$II)", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11050,13 +11405,14 @@ def L4_ior_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) = setbit(#$II)", -tc_da79106e, TypeV4LDST>, Enc_46c951 { +tc_44126683, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -11068,7 +11424,7 @@ def L4_ior_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) = setbit(#$II)", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11076,13 +11432,14 @@ def L4_ior_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) = setbit(#$II)", -tc_da79106e, TypeV4LDST>, Enc_e66a97 { +tc_44126683, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -11094,7 +11451,7 @@ def L4_ior_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) = setbit(#$II)", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11102,13 +11459,14 @@ def L4_ior_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) = setbit(#$II)", -tc_da79106e, TypeV4LDST>, Enc_84b2cd { +tc_44126683, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -11120,7 +11478,7 @@ def L4_ior_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) = setbit(#$II)", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11128,13 +11486,14 @@ def L4_isub_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) -= #$II", -tc_da79106e, TypeV4LDST>, Enc_46c951 { +tc_44126683, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -11146,7 +11505,7 @@ def L4_isub_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) -= #$II", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11154,13 +11513,14 @@ def L4_isub_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) -= #$II", -tc_da79106e, TypeV4LDST>, Enc_e66a97 { +tc_44126683, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -11172,7 +11532,7 @@ def L4_isub_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) -= #$II", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11180,13 +11540,14 @@ def L4_isub_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) -= #$II", -tc_da79106e, TypeV4LDST>, Enc_84b2cd { +tc_44126683, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -11198,7 +11559,7 @@ def L4_isub_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) -= #$II", -tc_da79106e, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11206,12 +11567,10 @@ def L4_loadalignb_ap : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Re32), (ins DoubleRegs:$Ryy32in, u32_0Imm:$II), "$Ryy32 = memb_fifo($Re32=#$II)", -tc_261d9b78, TypeLD>, Enc_f394d3 { +tc_5acef64a, TypeLD>, Enc_f394d3 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010100; -let hasNewValue = 1; -let opNewValue = 1; let addrMode = AbsoluteSet; let accessSize = ByteAccess; let mayLoad = 1; @@ -11228,7 +11587,7 @@ def L4_loadalignb_ur : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)", -tc_baccf077, TypeLD>, Enc_04c959 { +tc_0cd51c76, TypeLD>, Enc_04c959 { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100100; let addrMode = BaseLongOffset; @@ -11248,12 +11607,10 @@ def L4_loadalignh_ap : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Re32), (ins DoubleRegs:$Ryy32in, u32_0Imm:$II), "$Ryy32 = memh_fifo($Re32=#$II)", -tc_261d9b78, TypeLD>, Enc_f394d3 { +tc_5acef64a, TypeLD>, Enc_f394d3 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010010; -let hasNewValue = 1; -let opNewValue = 1; let addrMode = AbsoluteSet; let accessSize = HalfWordAccess; let mayLoad = 1; @@ -11270,7 +11627,7 @@ def L4_loadalignh_ur : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)", -tc_baccf077, TypeLD>, Enc_04c959 { +tc_0cd51c76, TypeLD>, Enc_04c959 { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100010; let addrMode = BaseLongOffset; @@ -11290,14 +11647,12 @@ def L4_loadbsw2_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = membh($Re32=#$II)", -tc_b5f5a094, TypeLD>, Enc_323f2d { +tc_b77c481f, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010001; let hasNewValue = 1; let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; let addrMode = AbsoluteSet; let accessSize = HalfWordAccess; let mayLoad = 1; @@ -11313,7 +11668,7 @@ def L4_loadbsw2_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = membh($Rt32<<#$Ii+#$II)", -tc_7d9a56cd, TypeLD>, Enc_4f677b { +tc_cf47a43f, TypeLD>, Enc_4f677b { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100001; let hasNewValue = 1; @@ -11334,12 +11689,10 @@ def L4_loadbsw4_ap : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rdd32 = membh($Re32=#$II)", -tc_b5f5a094, TypeLD>, Enc_7fa7f6 { +tc_b77c481f, TypeLD>, Enc_7fa7f6 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010111; -let hasNewValue = 1; -let opNewValue = 1; let addrMode = AbsoluteSet; let accessSize = WordAccess; let mayLoad = 1; @@ -11355,7 +11708,7 @@ def L4_loadbsw4_ur : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = membh($Rt32<<#$Ii+#$II)", -tc_7d9a56cd, TypeLD>, Enc_6185fe { +tc_cf47a43f, TypeLD>, Enc_6185fe { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100111; let addrMode = BaseLongOffset; @@ -11374,14 +11727,12 @@ def L4_loadbzw2_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memubh($Re32=#$II)", -tc_b5f5a094, TypeLD>, Enc_323f2d { +tc_b77c481f, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010011; let hasNewValue = 1; let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; let addrMode = AbsoluteSet; let accessSize = HalfWordAccess; let mayLoad = 1; @@ -11397,7 +11748,7 @@ def L4_loadbzw2_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memubh($Rt32<<#$Ii+#$II)", -tc_7d9a56cd, TypeLD>, Enc_4f677b { +tc_cf47a43f, TypeLD>, Enc_4f677b { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100011; let hasNewValue = 1; @@ -11418,12 +11769,10 @@ def L4_loadbzw4_ap : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rdd32 = memubh($Re32=#$II)", -tc_b5f5a094, TypeLD>, Enc_7fa7f6 { +tc_b77c481f, TypeLD>, Enc_7fa7f6 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010101; -let hasNewValue = 1; -let opNewValue = 1; let addrMode = AbsoluteSet; let accessSize = WordAccess; let mayLoad = 1; @@ -11439,7 +11788,7 @@ def L4_loadbzw4_ur : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = memubh($Rt32<<#$Ii+#$II)", -tc_7d9a56cd, TypeLD>, Enc_6185fe { +tc_cf47a43f, TypeLD>, Enc_6185fe { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100101; let addrMode = BaseLongOffset; @@ -11458,7 +11807,7 @@ def L4_loadd_locked : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = memd_locked($Rs32)", -tc_29c14515, TypeLD>, Enc_3a3d62 { +tc_6aa5711a, TypeLD>, Enc_3a3d62 { let Inst{13-5} = 0b010000000; let Inst{31-21} = 0b10010010000; let accessSize = DoubleWordAccess; @@ -11469,14 +11818,12 @@ def L4_loadrb_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memb($Re32=#$II)", -tc_b5f5a094, TypeLD>, Enc_323f2d { +tc_b77c481f, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011000; let hasNewValue = 1; let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; let addrMode = AbsoluteSet; let accessSize = ByteAccess; let mayLoad = 1; @@ -11492,7 +11839,7 @@ def L4_loadrb_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_5625c6c1, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010000; let hasNewValue = 1; @@ -11509,7 +11856,7 @@ def L4_loadrb_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memb($Rt32<<#$Ii+#$II)", -tc_7d9a56cd, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101000; let hasNewValue = 1; @@ -11531,12 +11878,10 @@ def L4_loadrd_ap : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rdd32 = memd($Re32=#$II)", -tc_b5f5a094, TypeLD>, Enc_7fa7f6 { +tc_b77c481f, TypeLD>, Enc_7fa7f6 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011110; -let hasNewValue = 1; -let opNewValue = 1; let addrMode = AbsoluteSet; let accessSize = DoubleWordAccess; let mayLoad = 1; @@ -11552,7 +11897,7 @@ def L4_loadrd_rr : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_5625c6c1, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl { +tc_f47d212f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010110; let addrMode = BaseRegOffset; @@ -11567,7 +11912,7 @@ def L4_loadrd_ur : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = memd($Rt32<<#$Ii+#$II)", -tc_7d9a56cd, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl { +tc_cf47a43f, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101110; let addrMode = BaseLongOffset; @@ -11587,14 +11932,12 @@ def L4_loadrh_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memh($Re32=#$II)", -tc_b5f5a094, TypeLD>, Enc_323f2d { +tc_b77c481f, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011010; let hasNewValue = 1; let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; let addrMode = AbsoluteSet; let accessSize = HalfWordAccess; let mayLoad = 1; @@ -11610,7 +11953,7 @@ def L4_loadrh_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_5625c6c1, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010010; let hasNewValue = 1; @@ -11627,7 +11970,7 @@ def L4_loadrh_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memh($Rt32<<#$Ii+#$II)", -tc_7d9a56cd, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101010; let hasNewValue = 1; @@ -11649,14 +11992,12 @@ def L4_loadri_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memw($Re32=#$II)", -tc_b5f5a094, TypeLD>, Enc_323f2d { +tc_b77c481f, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011100; let hasNewValue = 1; let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; let addrMode = AbsoluteSet; let accessSize = WordAccess; let mayLoad = 1; @@ -11672,7 +12013,7 @@ def L4_loadri_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_5625c6c1, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010100; let hasNewValue = 1; @@ -11689,7 +12030,7 @@ def L4_loadri_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memw($Rt32<<#$Ii+#$II)", -tc_7d9a56cd, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101100; let hasNewValue = 1; @@ -11711,14 +12052,12 @@ def L4_loadrub_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memub($Re32=#$II)", -tc_b5f5a094, TypeLD>, Enc_323f2d { +tc_b77c481f, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011001; let hasNewValue = 1; let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; let addrMode = AbsoluteSet; let accessSize = ByteAccess; let mayLoad = 1; @@ -11734,7 +12073,7 @@ def L4_loadrub_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_5625c6c1, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010001; let hasNewValue = 1; @@ -11751,7 +12090,7 @@ def L4_loadrub_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memub($Rt32<<#$Ii+#$II)", -tc_7d9a56cd, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101001; let hasNewValue = 1; @@ -11773,14 +12112,12 @@ def L4_loadruh_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memuh($Re32=#$II)", -tc_b5f5a094, TypeLD>, Enc_323f2d { +tc_b77c481f, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011011; let hasNewValue = 1; let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; let addrMode = AbsoluteSet; let accessSize = HalfWordAccess; let mayLoad = 1; @@ -11796,7 +12133,7 @@ def L4_loadruh_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_5625c6c1, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_f47d212f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010011; let hasNewValue = 1; @@ -11813,7 +12150,7 @@ def L4_loadruh_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memuh($Rt32<<#$Ii+#$II)", -tc_7d9a56cd, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_cf47a43f, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101011; let hasNewValue = 1; @@ -11835,13 +12172,14 @@ def L4_or_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) |= $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_d44e31 { +tc_44126683, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -11853,7 +12191,7 @@ def L4_or_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) |= $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11861,13 +12199,14 @@ def L4_or_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) |= $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_163a3c { +tc_44126683, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -11879,7 +12218,7 @@ def L4_or_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) |= $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11887,13 +12226,14 @@ def L4_or_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) |= $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_226535 { +tc_44126683, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -11905,7 +12245,7 @@ def L4_or_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) |= $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11913,7 +12253,7 @@ def L4_ploadrbf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memb(#$Ii)", -tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111000; @@ -11938,7 +12278,7 @@ def L4_ploadrbf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001000; let isPredicated = 1; let isPredicatedFalse = 1; @@ -11955,7 +12295,7 @@ def L4_ploadrbfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memb(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111000; @@ -11981,7 +12321,7 @@ def L4_ploadrbfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011000; let isPredicated = 1; let isPredicatedFalse = 1; @@ -11999,7 +12339,7 @@ def L4_ploadrbt_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memb(#$Ii)", -tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111000; @@ -12023,7 +12363,7 @@ def L4_ploadrbt_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000000; let isPredicated = 1; let hasNewValue = 1; @@ -12039,7 +12379,7 @@ def L4_ploadrbtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memb(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111000; @@ -12064,7 +12404,7 @@ def L4_ploadrbtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010000; let isPredicated = 1; let hasNewValue = 1; @@ -12081,7 +12421,7 @@ def L4_ploadrdf_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rdd32 = memd(#$Ii)", -tc_136c4786, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111110; @@ -12104,7 +12444,7 @@ def L4_ploadrdf_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110001110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12119,7 +12459,7 @@ def L4_ploadrdfnew_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rdd32 = memd(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111110; @@ -12143,7 +12483,7 @@ def L4_ploadrdfnew_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110011110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12159,7 +12499,7 @@ def L4_ploadrdt_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rdd32 = memd(#$Ii)", -tc_136c4786, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111110; @@ -12181,7 +12521,7 @@ def L4_ploadrdt_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110000110; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -12195,7 +12535,7 @@ def L4_ploadrdtnew_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rdd32 = memd(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111110; @@ -12218,7 +12558,7 @@ def L4_ploadrdtnew_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110010110; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -12233,7 +12573,7 @@ def L4_ploadrhf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memh(#$Ii)", -tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111010; @@ -12258,7 +12598,7 @@ def L4_ploadrhf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001010; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12275,7 +12615,7 @@ def L4_ploadrhfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memh(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111010; @@ -12301,7 +12641,7 @@ def L4_ploadrhfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011010; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12319,7 +12659,7 @@ def L4_ploadrht_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memh(#$Ii)", -tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111010; @@ -12343,7 +12683,7 @@ def L4_ploadrht_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000010; let isPredicated = 1; let hasNewValue = 1; @@ -12359,7 +12699,7 @@ def L4_ploadrhtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memh(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111010; @@ -12384,7 +12724,7 @@ def L4_ploadrhtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010010; let isPredicated = 1; let hasNewValue = 1; @@ -12401,7 +12741,7 @@ def L4_ploadrif_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memw(#$Ii)", -tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111100; @@ -12426,7 +12766,7 @@ def L4_ploadrif_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12443,7 +12783,7 @@ def L4_ploadrifnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memw(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111100; @@ -12469,7 +12809,7 @@ def L4_ploadrifnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12487,7 +12827,7 @@ def L4_ploadrit_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memw(#$Ii)", -tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111100; @@ -12511,7 +12851,7 @@ def L4_ploadrit_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000100; let isPredicated = 1; let hasNewValue = 1; @@ -12527,7 +12867,7 @@ def L4_ploadritnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memw(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111100; @@ -12552,7 +12892,7 @@ def L4_ploadritnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010100; let isPredicated = 1; let hasNewValue = 1; @@ -12569,7 +12909,7 @@ def L4_ploadrubf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memub(#$Ii)", -tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111001; @@ -12594,7 +12934,7 @@ def L4_ploadrubf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001001; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12611,7 +12951,7 @@ def L4_ploadrubfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memub(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111001; @@ -12637,7 +12977,7 @@ def L4_ploadrubfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011001; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12655,7 +12995,7 @@ def L4_ploadrubt_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memub(#$Ii)", -tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111001; @@ -12679,7 +13019,7 @@ def L4_ploadrubt_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000001; let isPredicated = 1; let hasNewValue = 1; @@ -12695,7 +13035,7 @@ def L4_ploadrubtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memub(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111001; @@ -12720,7 +13060,7 @@ def L4_ploadrubtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010001; let isPredicated = 1; let hasNewValue = 1; @@ -12737,7 +13077,7 @@ def L4_ploadruhf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memuh(#$Ii)", -tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111011; @@ -12762,7 +13102,7 @@ def L4_ploadruhf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001011; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12779,7 +13119,7 @@ def L4_ploadruhfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memuh(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111011; @@ -12805,7 +13145,7 @@ def L4_ploadruhfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011011; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12823,7 +13163,7 @@ def L4_ploadruht_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memuh(#$Ii)", -tc_136c4786, TypeLD>, Enc_2301d6, AddrModeRel { +tc_1d5a38a8, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111011; @@ -12847,7 +13187,7 @@ def L4_ploadruht_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_9dafb7d3, TypeLD>, Enc_2e1979, AddrModeRel { +tc_9ef61e5c, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000011; let isPredicated = 1; let hasNewValue = 1; @@ -12863,7 +13203,7 @@ def L4_ploadruhtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memuh(#$Ii)", -tc_b5f5a094, TypeLD>, Enc_2301d6, AddrModeRel { +tc_b77c481f, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111011; @@ -12888,7 +13228,7 @@ def L4_ploadruhtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_128719e8, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7dd427e, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010011; let isPredicated = 1; let hasNewValue = 1; @@ -12902,163 +13242,204 @@ let InputType = "reg"; let BaseOpcode = "L4_loadruh_rr"; } def L4_return : HInst< -(outs), -(ins), -"dealloc_return", -tc_dcfee7ae, TypeLD>, Enc_3a3d62, PredNewRel { -let Inst{4-0} = 0b11110; +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = dealloc_return($Rs32):raw", +tc_3d04548d, TypeLD>, Enc_3a3d62, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10010110000; -let Inst{20-16} = 0b11110; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; +let mayLoad = 1; let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let mayLoad = 1; -let Uses = [R30]; -let Defs = [PC, R29, R30, R31]; +let Uses = [FRAMEKEY]; +let Defs = [PC, R29]; let BaseOpcode = "L4_return"; let isBarrier = 1; let isPredicable = 1; let isTaken = 1; } def L4_return_f : HInst< -(outs), -(ins PredRegs:$Pv4), -"if (!$Pv4) dealloc_return", -tc_9ce7a5ab, TypeLD>, Enc_b7fad3, PredNewRel { -let Inst{4-0} = 0b11110; +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32), +"if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw", +tc_513bef45, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1100; let Inst{31-21} = 0b10010110000; -let Inst{20-16} = 0b11110; let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; -let cofMax1 = 1; let mayLoad = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let Uses = [R30]; -let Defs = [PC, R29, R30, R31]; +let Uses = [FRAMEKEY]; +let Defs = [PC, R29]; let BaseOpcode = "L4_return"; let isTaken = Inst{12}; } def L4_return_fnew_pnt : HInst< -(outs), -(ins PredRegs:$Pv4), -"if (!$Pv4.new) dealloc_return:nt", -tc_3993c58b, TypeLD>, Enc_b7fad3, PredNewRel { -let Inst{4-0} = 0b11110; +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32), +"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw", +tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b10010110000; -let Inst{20-16} = 0b11110; let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; -let cofMax1 = 1; let isPredicatedNew = 1; let mayLoad = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let Uses = [R30]; -let Defs = [PC, R29, R30, R31]; +let Uses = [FRAMEKEY]; +let Defs = [PC, R29]; let BaseOpcode = "L4_return"; let isTaken = Inst{12}; } def L4_return_fnew_pt : HInst< -(outs), -(ins PredRegs:$Pv4), -"if (!$Pv4.new) dealloc_return:t", -tc_3993c58b, TypeLD>, Enc_b7fad3, PredNewRel { -let Inst{4-0} = 0b11110; +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32), +"if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw", +tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1110; let Inst{31-21} = 0b10010110000; -let Inst{20-16} = 0b11110; let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; -let cofMax1 = 1; let isPredicatedNew = 1; let mayLoad = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let Uses = [R30]; -let Defs = [PC, R29, R30, R31]; +let Uses = [FRAMEKEY]; +let Defs = [PC, R29]; let BaseOpcode = "L4_return"; let isTaken = Inst{12}; } -def L4_return_t : HInst< +def L4_return_map_to_raw_f : HInst< +(outs), +(ins PredRegs:$Pv4), +"if (!$Pv4) dealloc_return", +tc_513bef45, TypeMAPPING>, Requires<[HasV65T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_return_map_to_raw_fnew_pnt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if (!$Pv4.new) dealloc_return:nt", +tc_395dc00f, TypeMAPPING>, Requires<[HasV65T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_return_map_to_raw_fnew_pt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if (!$Pv4.new) dealloc_return:t", +tc_395dc00f, TypeMAPPING>, Requires<[HasV65T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_return_map_to_raw_t : HInst< (outs), (ins PredRegs:$Pv4), "if ($Pv4) dealloc_return", -tc_9ce7a5ab, TypeLD>, Enc_b7fad3, PredNewRel { -let Inst{4-0} = 0b11110; +tc_3bc2c5d3, TypeMAPPING>, Requires<[HasV65T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_return_map_to_raw_tnew_pnt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if ($Pv4.new) dealloc_return:nt", +tc_e7624c08, TypeMAPPING>, Requires<[HasV65T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_return_map_to_raw_tnew_pt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if ($Pv4.new) dealloc_return:t", +tc_e7624c08, TypeMAPPING>, Requires<[HasV65T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_return_t : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32), +"if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw", +tc_513bef45, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0100; let Inst{31-21} = 0b10010110000; -let Inst{20-16} = 0b11110; let isPredicated = 1; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; -let cofMax1 = 1; let mayLoad = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let Uses = [R30]; -let Defs = [PC, R29, R30, R31]; +let Uses = [FRAMEKEY]; +let Defs = [PC, R29]; let BaseOpcode = "L4_return"; let isTaken = Inst{12}; } def L4_return_tnew_pnt : HInst< -(outs), -(ins PredRegs:$Pv4), -"if ($Pv4.new) dealloc_return:nt", -tc_3993c58b, TypeLD>, Enc_b7fad3, PredNewRel { -let Inst{4-0} = 0b11110; +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32), +"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw", +tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0010; let Inst{31-21} = 0b10010110000; -let Inst{20-16} = 0b11110; let isPredicated = 1; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; -let cofMax1 = 1; let isPredicatedNew = 1; let mayLoad = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let Uses = [R30]; -let Defs = [PC, R29, R30, R31]; +let Uses = [FRAMEKEY]; +let Defs = [PC, R29]; let BaseOpcode = "L4_return"; let isTaken = Inst{12}; } def L4_return_tnew_pt : HInst< -(outs), -(ins PredRegs:$Pv4), -"if ($Pv4.new) dealloc_return:t", -tc_3993c58b, TypeLD>, Enc_b7fad3, PredNewRel { -let Inst{4-0} = 0b11110; +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32), +"if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw", +tc_395dc00f, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0110; let Inst{31-21} = 0b10010110000; -let Inst{20-16} = 0b11110; let isPredicated = 1; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; -let cofMax1 = 1; let isPredicatedNew = 1; let mayLoad = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let Uses = [R30]; -let Defs = [PC, R29, R30, R31]; +let Uses = [FRAMEKEY]; +let Defs = [PC, R29]; let BaseOpcode = "L4_return"; let isTaken = Inst{12}; } @@ -13066,13 +13447,14 @@ def L4_sub_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) -= $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_d44e31 { +tc_44126683, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -13084,7 +13466,7 @@ def L4_sub_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) -= $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13092,13 +13474,14 @@ def L4_sub_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) -= $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_163a3c { +tc_44126683, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -13110,7 +13493,7 @@ def L4_sub_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) -= $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13118,13 +13501,14 @@ def L4_sub_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) -= $Rt32", -tc_a9c993d9, TypeV4LDST>, Enc_226535 { +tc_44126683, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let isExtendable = 1; let opExtendable = 1; @@ -13136,7 +13520,23 @@ def L4_sub_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) -= $Rt32", -tc_a9c993d9, TypeMAPPING> { +tc_44126683, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L6_deallocframe_map_to_raw : HInst< +(outs), +(ins), +"deallocframe", +tc_d1090e34, TypeMAPPING>, Requires<[HasV65T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L6_return_map_to_raw : HInst< +(outs), +(ins), +"dealloc_return", +tc_3d04548d, TypeMAPPING>, Requires<[HasV65T]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13144,7 +13544,7 @@ def M2_acci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += add($Rs32,$Rt32)", -tc_c0cd91a8, TypeM>, Enc_2ae154, ImmRegRel { +tc_c74f796f, TypeM>, Enc_2ae154, ImmRegRel { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -13159,7 +13559,7 @@ def M2_accii : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 += add($Rs32,#$Ii)", -tc_c0cd91a8, TypeM>, Enc_c90aca, ImmRegRel { +tc_c74f796f, TypeM>, Enc_c90aca, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100010000; let hasNewValue = 1; @@ -13178,7 +13578,7 @@ def M2_cmaci_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpyi($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13189,7 +13589,7 @@ def M2_cmacr_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpyr($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13200,7 +13600,7 @@ def M2_cmacs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32):sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13212,7 +13612,7 @@ def M2_cmacs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -13224,7 +13624,7 @@ def M2_cmacsc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32*):sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111010; @@ -13236,7 +13636,7 @@ def M2_cmacsc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111110; @@ -13248,7 +13648,7 @@ def M2_cmpyi_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpyi($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13258,7 +13658,7 @@ def M2_cmpyr_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpyr($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13268,7 +13668,7 @@ def M2_cmpyrs_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32):rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101001; @@ -13281,7 +13681,7 @@ def M2_cmpyrs_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -13294,7 +13694,7 @@ def M2_cmpyrsc_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101011; @@ -13307,7 +13707,7 @@ def M2_cmpyrsc_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101111; @@ -13320,7 +13720,7 @@ def M2_cmpys_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32):sat", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13331,7 +13731,7 @@ def M2_cmpys_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -13342,7 +13742,7 @@ def M2_cmpysc_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32*):sat", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -13353,7 +13753,7 @@ def M2_cmpysc_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101110; @@ -13364,7 +13764,7 @@ def M2_cnacs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32):sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13376,7 +13776,7 @@ def M2_cnacs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -13388,7 +13788,7 @@ def M2_cnacsc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32*):sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111010; @@ -13400,7 +13800,7 @@ def M2_cnacsc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111110; @@ -13412,7 +13812,7 @@ def M2_dpmpyss_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13423,7 +13823,7 @@ def M2_dpmpyss_nac_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111001; @@ -13434,7 +13834,7 @@ def M2_dpmpyss_rnd_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32):rnd", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101001; @@ -13446,7 +13846,7 @@ def M2_dpmpyss_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13456,7 +13856,7 @@ def M2_dpmpyuu_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111010; @@ -13467,7 +13867,7 @@ def M2_dpmpyuu_nac_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111011; @@ -13478,7 +13878,7 @@ def M2_dpmpyuu_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -13488,7 +13888,7 @@ def M2_hmmpyh_rs1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -13501,7 +13901,7 @@ def M2_hmmpyh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -13514,7 +13914,7 @@ def M2_hmmpyl_rs1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101111; @@ -13527,7 +13927,7 @@ def M2_hmmpyl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -13540,7 +13940,7 @@ def M2_maci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyi($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_2ae154, ImmRegRel { +tc_e913dc32, TypeM>, Enc_2ae154, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -13555,7 +13955,7 @@ def M2_macsin : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), "$Rx32 -= mpyi($Rs32,#$Ii)", -tc_a12a5971, TypeM>, Enc_c90aca { +tc_16d0d8d5, TypeM>, Enc_c90aca { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100001100; let hasNewValue = 1; @@ -13573,7 +13973,7 @@ def M2_macsip : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), "$Rx32 += mpyi($Rs32,#$Ii)", -tc_a12a5971, TypeM>, Enc_c90aca, ImmRegRel { +tc_16d0d8d5, TypeM>, Enc_c90aca, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100001000; let hasNewValue = 1; @@ -13592,7 +13992,7 @@ def M2_mmachs_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -13604,7 +14004,7 @@ def M2_mmachs_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -13616,7 +14016,7 @@ def M2_mmachs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -13628,7 +14028,7 @@ def M2_mmachs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -13640,7 +14040,7 @@ def M2_mmacls_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -13652,7 +14052,7 @@ def M2_mmacls_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -13664,7 +14064,7 @@ def M2_mmacls_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -13676,7 +14076,7 @@ def M2_mmacls_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -13688,7 +14088,7 @@ def M2_mmacuhs_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -13700,7 +14100,7 @@ def M2_mmacuhs_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -13712,7 +14112,7 @@ def M2_mmacuhs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -13724,7 +14124,7 @@ def M2_mmacuhs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010110; @@ -13736,7 +14136,7 @@ def M2_mmaculs_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -13748,7 +14148,7 @@ def M2_mmaculs_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -13760,7 +14160,7 @@ def M2_mmaculs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -13772,7 +14172,7 @@ def M2_mmaculs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010110; @@ -13784,7 +14184,7 @@ def M2_mmpyh_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -13795,7 +14195,7 @@ def M2_mmpyh_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -13806,7 +14206,7 @@ def M2_mmpyh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -13817,7 +14217,7 @@ def M2_mmpyh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -13828,7 +14228,7 @@ def M2_mmpyl_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -13839,7 +14239,7 @@ def M2_mmpyl_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -13850,7 +14250,7 @@ def M2_mmpyl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -13861,7 +14261,7 @@ def M2_mmpyl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -13872,7 +14272,7 @@ def M2_mmpyuh_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -13883,7 +14283,7 @@ def M2_mmpyuh_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -13894,7 +14294,7 @@ def M2_mmpyuh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -13905,7 +14305,7 @@ def M2_mmpyuh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -13916,7 +14316,7 @@ def M2_mmpyul_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -13927,7 +14327,7 @@ def M2_mmpyul_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -13938,7 +14338,7 @@ def M2_mmpyul_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -13949,7 +14349,7 @@ def M2_mmpyul_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -13960,7 +14360,7 @@ def M2_mpy_acc_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -13973,7 +14373,7 @@ def M2_mpy_acc_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -13986,7 +14386,7 @@ def M2_mpy_acc_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -13999,7 +14399,7 @@ def M2_mpy_acc_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14012,7 +14412,7 @@ def M2_mpy_acc_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14025,7 +14425,7 @@ def M2_mpy_acc_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14038,7 +14438,7 @@ def M2_mpy_acc_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14051,7 +14451,7 @@ def M2_mpy_acc_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14064,7 +14464,7 @@ def M2_mpy_acc_sat_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h):sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14078,7 +14478,7 @@ def M2_mpy_acc_sat_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14092,7 +14492,7 @@ def M2_mpy_acc_sat_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l):sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14106,7 +14506,7 @@ def M2_mpy_acc_sat_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14120,7 +14520,7 @@ def M2_mpy_acc_sat_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h):sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14134,7 +14534,7 @@ def M2_mpy_acc_sat_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14148,7 +14548,7 @@ def M2_mpy_acc_sat_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l):sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14162,7 +14562,7 @@ def M2_mpy_acc_sat_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14176,7 +14576,7 @@ def M2_mpy_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h)", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14188,7 +14588,7 @@ def M2_mpy_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14200,7 +14600,7 @@ def M2_mpy_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l)", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14212,7 +14612,7 @@ def M2_mpy_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14224,7 +14624,7 @@ def M2_mpy_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h)", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14236,7 +14636,7 @@ def M2_mpy_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14248,7 +14648,7 @@ def M2_mpy_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l)", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14260,7 +14660,7 @@ def M2_mpy_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14272,7 +14672,7 @@ def M2_mpy_nac_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14285,7 +14685,7 @@ def M2_mpy_nac_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14298,7 +14698,7 @@ def M2_mpy_nac_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14311,7 +14711,7 @@ def M2_mpy_nac_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14324,7 +14724,7 @@ def M2_mpy_nac_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14337,7 +14737,7 @@ def M2_mpy_nac_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14350,7 +14750,7 @@ def M2_mpy_nac_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14363,7 +14763,7 @@ def M2_mpy_nac_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14376,7 +14776,7 @@ def M2_mpy_nac_sat_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h):sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14390,7 +14790,7 @@ def M2_mpy_nac_sat_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14404,7 +14804,7 @@ def M2_mpy_nac_sat_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l):sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14418,7 +14818,7 @@ def M2_mpy_nac_sat_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14432,7 +14832,7 @@ def M2_mpy_nac_sat_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h):sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14446,7 +14846,7 @@ def M2_mpy_nac_sat_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14460,7 +14860,7 @@ def M2_mpy_nac_sat_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l):sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14474,7 +14874,7 @@ def M2_mpy_nac_sat_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14488,7 +14888,7 @@ def M2_mpy_rnd_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -14500,7 +14900,7 @@ def M2_mpy_rnd_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -14512,7 +14912,7 @@ def M2_mpy_rnd_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -14524,7 +14924,7 @@ def M2_mpy_rnd_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -14536,7 +14936,7 @@ def M2_mpy_rnd_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -14548,7 +14948,7 @@ def M2_mpy_rnd_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -14560,7 +14960,7 @@ def M2_mpy_rnd_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -14572,7 +14972,7 @@ def M2_mpy_rnd_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -14584,7 +14984,7 @@ def M2_mpy_sat_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14597,7 +14997,7 @@ def M2_mpy_sat_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14610,7 +15010,7 @@ def M2_mpy_sat_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14623,7 +15023,7 @@ def M2_mpy_sat_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14636,7 +15036,7 @@ def M2_mpy_sat_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14649,7 +15049,7 @@ def M2_mpy_sat_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14662,7 +15062,7 @@ def M2_mpy_sat_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14675,7 +15075,7 @@ def M2_mpy_sat_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14688,7 +15088,7 @@ def M2_mpy_sat_rnd_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -14701,7 +15101,7 @@ def M2_mpy_sat_rnd_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -14714,7 +15114,7 @@ def M2_mpy_sat_rnd_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -14727,7 +15127,7 @@ def M2_mpy_sat_rnd_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -14740,7 +15140,7 @@ def M2_mpy_sat_rnd_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -14753,7 +15153,7 @@ def M2_mpy_sat_rnd_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -14766,7 +15166,7 @@ def M2_mpy_sat_rnd_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -14779,7 +15179,7 @@ def M2_mpy_sat_rnd_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -14792,7 +15192,7 @@ def M2_mpy_up : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101000; @@ -14804,7 +15204,7 @@ def M2_mpy_up_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32):<<1", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -14816,7 +15216,7 @@ def M2_mpy_up_s1_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101111; @@ -14829,7 +15229,7 @@ def M2_mpyd_acc_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -14840,7 +15240,7 @@ def M2_mpyd_acc_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -14851,7 +15251,7 @@ def M2_mpyd_acc_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -14862,7 +15262,7 @@ def M2_mpyd_acc_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -14873,7 +15273,7 @@ def M2_mpyd_acc_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -14884,7 +15284,7 @@ def M2_mpyd_acc_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -14895,7 +15295,7 @@ def M2_mpyd_acc_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -14906,7 +15306,7 @@ def M2_mpyd_acc_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -14917,7 +15317,7 @@ def M2_mpyd_hh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -14927,7 +15327,7 @@ def M2_mpyd_hh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -14937,7 +15337,7 @@ def M2_mpyd_hl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -14947,7 +15347,7 @@ def M2_mpyd_hl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -14957,7 +15357,7 @@ def M2_mpyd_lh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -14967,7 +15367,7 @@ def M2_mpyd_lh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -14977,7 +15377,7 @@ def M2_mpyd_ll_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -14987,7 +15387,7 @@ def M2_mpyd_ll_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -14997,7 +15397,7 @@ def M2_mpyd_nac_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15008,7 +15408,7 @@ def M2_mpyd_nac_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15019,7 +15419,7 @@ def M2_mpyd_nac_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15030,7 +15430,7 @@ def M2_mpyd_nac_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15041,7 +15441,7 @@ def M2_mpyd_nac_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15052,7 +15452,7 @@ def M2_mpyd_nac_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15063,7 +15463,7 @@ def M2_mpyd_nac_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15074,7 +15474,7 @@ def M2_mpyd_nac_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15085,7 +15485,7 @@ def M2_mpyd_rnd_hh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15095,7 +15495,7 @@ def M2_mpyd_rnd_hh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15105,7 +15505,7 @@ def M2_mpyd_rnd_hl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15115,7 +15515,7 @@ def M2_mpyd_rnd_hl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15125,7 +15525,7 @@ def M2_mpyd_rnd_lh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15135,7 +15535,7 @@ def M2_mpyd_rnd_lh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15145,7 +15545,7 @@ def M2_mpyd_rnd_ll_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15155,7 +15555,7 @@ def M2_mpyd_rnd_ll_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15165,7 +15565,7 @@ def M2_mpyi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyi($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_5ab2be, ImmRegRel { +tc_8fd5f294, TypeM>, Enc_5ab2be, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101000; @@ -15179,7 +15579,7 @@ def M2_mpysin : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u8_0Imm:$Ii), "$Rd32 = -mpyi($Rs32,#$Ii)", -tc_ae2c2dc2, TypeM>, Enc_b8c967 { +tc_1853ea6d, TypeM>, Enc_b8c967 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100000100; let hasNewValue = 1; @@ -15190,7 +15590,7 @@ def M2_mpysip : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Rd32 = +mpyi($Rs32,#$Ii)", -tc_ae2c2dc2, TypeM>, Enc_b8c967 { +tc_1853ea6d, TypeM>, Enc_b8c967 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100000000; let hasNewValue = 1; @@ -15206,7 +15606,7 @@ def M2_mpysmi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, m32_0Imm:$Ii), "$Rd32 = mpyi($Rs32,#$Ii)", -tc_ae2c2dc2, TypeM>, ImmRegRel { +tc_1853ea6d, TypeM>, ImmRegRel { let hasNewValue = 1; let opNewValue = 0; let CextOpcode = "M2_mpyi"; @@ -15222,7 +15622,7 @@ def M2_mpysu_up : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpysu($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101011; @@ -15234,7 +15634,7 @@ def M2_mpyu_acc_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15247,7 +15647,7 @@ def M2_mpyu_acc_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15260,7 +15660,7 @@ def M2_mpyu_acc_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15273,7 +15673,7 @@ def M2_mpyu_acc_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15286,7 +15686,7 @@ def M2_mpyu_acc_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15299,7 +15699,7 @@ def M2_mpyu_acc_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15312,7 +15712,7 @@ def M2_mpyu_acc_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15325,7 +15725,7 @@ def M2_mpyu_acc_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15338,7 +15738,7 @@ def M2_mpyu_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.h)", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15350,7 +15750,7 @@ def M2_mpyu_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15362,7 +15762,7 @@ def M2_mpyu_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.l)", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15374,7 +15774,7 @@ def M2_mpyu_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15386,7 +15786,7 @@ def M2_mpyu_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.h)", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15398,7 +15798,7 @@ def M2_mpyu_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15410,7 +15810,7 @@ def M2_mpyu_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.l)", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15422,7 +15822,7 @@ def M2_mpyu_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15434,7 +15834,7 @@ def M2_mpyu_nac_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -15447,7 +15847,7 @@ def M2_mpyu_nac_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -15460,7 +15860,7 @@ def M2_mpyu_nac_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -15473,7 +15873,7 @@ def M2_mpyu_nac_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -15486,7 +15886,7 @@ def M2_mpyu_nac_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -15499,7 +15899,7 @@ def M2_mpyu_nac_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -15512,7 +15912,7 @@ def M2_mpyu_nac_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -15525,7 +15925,7 @@ def M2_mpyu_nac_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -15538,7 +15938,7 @@ def M2_mpyu_up : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101010; @@ -15550,7 +15950,7 @@ def M2_mpyud_acc_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -15561,7 +15961,7 @@ def M2_mpyud_acc_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -15572,7 +15972,7 @@ def M2_mpyud_acc_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -15583,7 +15983,7 @@ def M2_mpyud_acc_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -15594,7 +15994,7 @@ def M2_mpyud_acc_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -15605,7 +16005,7 @@ def M2_mpyud_acc_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -15616,7 +16016,7 @@ def M2_mpyud_acc_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -15627,7 +16027,7 @@ def M2_mpyud_acc_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -15638,7 +16038,7 @@ def M2_mpyud_hh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.h)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -15648,7 +16048,7 @@ def M2_mpyud_hh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -15658,7 +16058,7 @@ def M2_mpyud_hl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.l)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -15668,7 +16068,7 @@ def M2_mpyud_hl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -15678,7 +16078,7 @@ def M2_mpyud_lh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.h)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -15688,7 +16088,7 @@ def M2_mpyud_lh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -15698,7 +16098,7 @@ def M2_mpyud_ll_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.l)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -15708,7 +16108,7 @@ def M2_mpyud_ll_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -15718,7 +16118,7 @@ def M2_mpyud_nac_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -15729,7 +16129,7 @@ def M2_mpyud_nac_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -15740,7 +16140,7 @@ def M2_mpyud_nac_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -15751,7 +16151,7 @@ def M2_mpyud_nac_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -15762,7 +16162,7 @@ def M2_mpyud_nac_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.h)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -15773,7 +16173,7 @@ def M2_mpyud_nac_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -15784,7 +16184,7 @@ def M2_mpyud_nac_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.l)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -15795,7 +16195,7 @@ def M2_mpyud_nac_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -15806,7 +16206,7 @@ def M2_mpyui : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyui($Rs32,$Rt32)", -tc_8c8041e6, TypeM> { +tc_8fd5f294, TypeM> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -15816,7 +16216,7 @@ def M2_nacci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= add($Rs32,$Rt32)", -tc_c0cd91a8, TypeM>, Enc_2ae154 { +tc_c74f796f, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111100; @@ -15830,7 +16230,7 @@ def M2_naccii : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 -= add($Rs32,#$Ii)", -tc_c0cd91a8, TypeM>, Enc_c90aca { +tc_c74f796f, TypeM>, Enc_c90aca { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100010100; let hasNewValue = 1; @@ -15848,7 +16248,7 @@ def M2_subacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32), "$Rx32 += sub($Rt32,$Rs32)", -tc_c0cd91a8, TypeM>, Enc_a568d4 { +tc_c74f796f, TypeM>, Enc_a568d4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -15862,7 +16262,7 @@ def M2_vabsdiffh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffh($Rtt32,$Rss32)", -tc_63cd9d2d, TypeM>, Enc_ea23e4 { +tc_2b6f77c6, TypeM>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -15872,7 +16272,7 @@ def M2_vabsdiffw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffw($Rtt32,$Rss32)", -tc_63cd9d2d, TypeM>, Enc_ea23e4 { +tc_2b6f77c6, TypeM>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -15882,7 +16282,7 @@ def M2_vcmac_s0_sat_i : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vcmpyi($Rss32,$Rtt32):sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -15894,7 +16294,7 @@ def M2_vcmac_s0_sat_r : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vcmpyr($Rss32,$Rtt32):sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -15906,7 +16306,7 @@ def M2_vcmpy_s0_sat_i : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyi($Rss32,$Rtt32):sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -15917,7 +16317,7 @@ def M2_vcmpy_s0_sat_r : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyr($Rss32,$Rtt32):sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -15928,7 +16328,7 @@ def M2_vcmpy_s1_sat_i : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -15939,7 +16339,7 @@ def M2_vcmpy_s1_sat_r : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -15950,7 +16350,7 @@ def M2_vdmacs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vdmpy($Rss32,$Rtt32):sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -15962,7 +16362,7 @@ def M2_vdmacs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -15974,7 +16374,7 @@ def M2_vdmpyrs_s0 : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat", -tc_8c8041e6, TypeM>, Enc_d2216a { +tc_8fd5f294, TypeM>, Enc_d2216a { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001000; @@ -15987,7 +16387,7 @@ def M2_vdmpyrs_s1 : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_d2216a { +tc_8fd5f294, TypeM>, Enc_d2216a { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001100; @@ -16000,7 +16400,7 @@ def M2_vdmpys_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vdmpy($Rss32,$Rtt32):sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16011,7 +16411,7 @@ def M2_vdmpys_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -16022,7 +16422,7 @@ def M2_vmac2 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyh($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111001; @@ -16033,7 +16433,7 @@ def M2_vmac2es : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyeh($Rss32,$Rtt32)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -16044,7 +16444,7 @@ def M2_vmac2es_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyeh($Rss32,$Rtt32):sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16056,7 +16456,7 @@ def M2_vmac2es_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -16068,7 +16468,7 @@ def M2_vmac2s_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyh($Rs32,$Rt32):sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -16080,7 +16480,7 @@ def M2_vmac2s_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -16092,7 +16492,7 @@ def M2_vmac2su_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyhsu($Rs32,$Rt32):sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111011; @@ -16104,7 +16504,7 @@ def M2_vmac2su_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111111; @@ -16116,7 +16516,7 @@ def M2_vmpy2es_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyeh($Rss32,$Rtt32):sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16127,7 +16527,7 @@ def M2_vmpy2es_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -16138,7 +16538,7 @@ def M2_vmpy2s_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyh($Rs32,$Rt32):sat", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -16149,7 +16549,7 @@ def M2_vmpy2s_s0pack : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101001; @@ -16162,7 +16562,7 @@ def M2_vmpy2s_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -16173,7 +16573,7 @@ def M2_vmpy2s_s1pack : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat", -tc_8c8041e6, TypeM>, Enc_5ab2be { +tc_8fd5f294, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -16186,7 +16586,7 @@ def M2_vmpy2su_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyhsu($Rs32,$Rt32):sat", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -16197,7 +16597,7 @@ def M2_vmpy2su_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -16208,7 +16608,7 @@ def M2_vraddh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vraddh($Rss32,$Rtt32)", -tc_8c8041e6, TypeM>, Enc_d2216a { +tc_8fd5f294, TypeM>, Enc_d2216a { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001001; @@ -16220,7 +16620,7 @@ def M2_vradduh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vradduh($Rss32,$Rtt32)", -tc_8c8041e6, TypeM>, Enc_d2216a { +tc_8fd5f294, TypeM>, Enc_d2216a { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001000; @@ -16232,7 +16632,7 @@ def M2_vrcmaci_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyi($Rss32,$Rtt32)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16243,7 +16643,7 @@ def M2_vrcmaci_s0c : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyi($Rss32,$Rtt32*)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -16254,7 +16654,7 @@ def M2_vrcmacr_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyr($Rss32,$Rtt32)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16265,7 +16665,7 @@ def M2_vrcmacr_s0c : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyr($Rss32,$Rtt32*)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -16276,7 +16676,7 @@ def M2_vrcmpyi_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyi($Rss32,$Rtt32)", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16286,7 +16686,7 @@ def M2_vrcmpyi_s0c : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyi($Rss32,$Rtt32*)", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -16296,7 +16696,7 @@ def M2_vrcmpyr_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyr($Rss32,$Rtt32)", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16306,7 +16706,7 @@ def M2_vrcmpyr_s0c : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyr($Rss32,$Rtt32*)", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -16316,7 +16716,7 @@ def M2_vrcmpys_acc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat", -tc_8cb685d9, TypeM> { +tc_e913dc32, TypeM> { let isPseudo = 1; let Constraints = "$Rxx32 = $Rxx32in"; } @@ -16324,7 +16724,7 @@ def M2_vrcmpys_acc_s1_h : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -16336,7 +16736,7 @@ def M2_vrcmpys_acc_s1_l : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -16348,14 +16748,14 @@ def M2_vrcmpys_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat", -tc_8c8041e6, TypeM> { +tc_8fd5f294, TypeM> { let isPseudo = 1; } def M2_vrcmpys_s1_h : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -16366,7 +16766,7 @@ def M2_vrcmpys_s1_l : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -16377,7 +16777,7 @@ def M2_vrcmpys_s1rp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat", -tc_8c8041e6, TypeM> { +tc_8fd5f294, TypeM> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -16386,7 +16786,7 @@ def M2_vrcmpys_s1rp_h : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi", -tc_8c8041e6, TypeM>, Enc_d2216a { +tc_8fd5f294, TypeM>, Enc_d2216a { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001101; @@ -16399,7 +16799,7 @@ def M2_vrcmpys_s1rp_l : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo", -tc_8c8041e6, TypeM>, Enc_d2216a { +tc_8fd5f294, TypeM>, Enc_d2216a { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001101; @@ -16412,7 +16812,7 @@ def M2_vrmac_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpyh($Rss32,$Rtt32)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16423,7 +16823,7 @@ def M2_vrmpy_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpyh($Rss32,$Rtt32)", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16433,7 +16833,7 @@ def M2_xor_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= xor($Rs32,$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111100; @@ -16447,7 +16847,7 @@ def M4_and_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= and($Rs32,$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -16461,7 +16861,7 @@ def M4_and_andn : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= and($Rs32,~$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111001; @@ -16475,7 +16875,7 @@ def M4_and_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= or($Rs32,$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -16489,7 +16889,7 @@ def M4_and_xor : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= xor($Rs32,$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -16503,7 +16903,7 @@ def M4_cmpyi_wh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat", -tc_8c8041e6, TypeS_3op>, Enc_3d5b28 { +tc_8fd5f294, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -16516,7 +16916,7 @@ def M4_cmpyi_whc : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat", -tc_8c8041e6, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> { +tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -16529,7 +16929,7 @@ def M4_cmpyr_wh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat", -tc_8c8041e6, TypeS_3op>, Enc_3d5b28 { +tc_8fd5f294, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -16542,7 +16942,7 @@ def M4_cmpyr_whc : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat", -tc_8c8041e6, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> { +tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5T]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -16555,7 +16955,7 @@ def M4_mac_up_s1_sat : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32,$Rt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111011; @@ -16570,7 +16970,7 @@ def M4_mpyri_addi : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II), "$Rd32 = add(#$Ii,mpyi($Rs32,#$II))", -tc_a12a5971, TypeALU64>, Enc_322e1b, ImmRegRel { +tc_16d0d8d5, TypeALU64>, Enc_322e1b, ImmRegRel { let Inst{31-24} = 0b11011000; let hasNewValue = 1; let opNewValue = 0; @@ -16586,7 +16986,7 @@ def M4_mpyri_addr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii), "$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))", -tc_a12a5971, TypeALU64>, Enc_420cf3, ImmRegRel { +tc_16d0d8d5, TypeALU64>, Enc_420cf3, ImmRegRel { let Inst{31-23} = 0b110111111; let hasNewValue = 1; let opNewValue = 0; @@ -16603,7 +17003,7 @@ def M4_mpyri_addr_u2 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32), "$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))", -tc_69bb508b, TypeALU64>, Enc_277737 { +tc_bcc96cee, TypeALU64>, Enc_277737 { let Inst{31-23} = 0b110111110; let hasNewValue = 1; let opNewValue = 0; @@ -16613,7 +17013,7 @@ def M4_mpyrr_addi : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))", -tc_8cb685d9, TypeALU64>, Enc_a7b8e8, ImmRegRel { +tc_e913dc32, TypeALU64>, Enc_a7b8e8, ImmRegRel { let Inst{31-23} = 0b110101110; let hasNewValue = 1; let opNewValue = 0; @@ -16630,7 +17030,7 @@ def M4_mpyrr_addr : HInst< (outs IntRegs:$Ry32), (ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32), "$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))", -tc_8cb685d9, TypeM>, Enc_7f1a05, ImmRegRel { +tc_e913dc32, TypeM>, Enc_7f1a05, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100011000; @@ -16645,7 +17045,7 @@ def M4_nac_up_s1_sat : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32,$Rt32):<<1:sat", -tc_8cb685d9, TypeM>, Enc_2ae154 { +tc_e913dc32, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111011; @@ -16660,7 +17060,7 @@ def M4_or_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= and($Rs32,$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -16674,7 +17074,7 @@ def M4_or_andn : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= and($Rs32,~$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111001; @@ -16688,7 +17088,7 @@ def M4_or_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= or($Rs32,$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -16702,7 +17102,7 @@ def M4_or_xor : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= xor($Rs32,$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -16716,7 +17116,7 @@ def M4_pmpyw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = pmpyw($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -16726,7 +17126,7 @@ def M4_pmpyw_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 ^= pmpyw($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111001; @@ -16737,7 +17137,7 @@ def M4_vpmpyh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vpmpyh($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101110; @@ -16747,7 +17147,7 @@ def M4_vpmpyh_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 ^= vpmpyh($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111101; @@ -16758,7 +17158,7 @@ def M4_vrmpyeh_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpyweh($Rss32,$Rtt32)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -16769,7 +17169,7 @@ def M4_vrmpyeh_acc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -16780,7 +17180,7 @@ def M4_vrmpyeh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpyweh($Rss32,$Rtt32)", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -16790,7 +17190,7 @@ def M4_vrmpyeh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -16800,7 +17200,7 @@ def M4_vrmpyoh_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpywoh($Rss32,$Rtt32)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -16811,7 +17211,7 @@ def M4_vrmpyoh_acc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -16822,7 +17222,7 @@ def M4_vrmpyoh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpywoh($Rss32,$Rtt32)", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -16832,7 +17232,7 @@ def M4_vrmpyoh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -16842,7 +17242,7 @@ def M4_xor_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= and($Rs32,$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -16856,7 +17256,7 @@ def M4_xor_andn : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= and($Rs32,~$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111001; @@ -16870,7 +17270,7 @@ def M4_xor_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= or($Rs32,$Rt32)", -tc_3c10f809, TypeM>, Enc_2ae154 { +tc_84df2cd3, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -16884,7 +17284,7 @@ def M4_xor_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 ^= xor($Rss32,$Rtt32)", -tc_3c10f809, TypeS_3op>, Enc_88c16c { +tc_84df2cd3, TypeS_3op>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001010100; @@ -16895,7 +17295,7 @@ def M5_vdmacbsu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat", -tc_8cb685d9, TypeM>, Enc_88c16c, Requires<[HasV5T]> { +tc_e913dc32, TypeM>, Enc_88c16c, Requires<[HasV5T]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -16907,7 +17307,7 @@ def M5_vdmpybsu : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat", -tc_8c8041e6, TypeM>, Enc_a56825, Requires<[HasV5T]> { +tc_8fd5f294, TypeM>, Enc_a56825, Requires<[HasV5T]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -16918,7 +17318,7 @@ def M5_vmacbsu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpybsu($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111110; @@ -16929,7 +17329,7 @@ def M5_vmacbuu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpybu($Rs32,$Rt32)", -tc_8cb685d9, TypeM>, Enc_61f0b0 { +tc_e913dc32, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -16940,7 +17340,7 @@ def M5_vmpybsu : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpybsu($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -16950,7 +17350,7 @@ def M5_vmpybuu : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpybu($Rs32,$Rt32)", -tc_8c8041e6, TypeM>, Enc_be32a5 { +tc_8fd5f294, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -16960,7 +17360,7 @@ def M5_vrmacbsu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpybsu($Rss32,$Rtt32)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010110; @@ -16971,7 +17371,7 @@ def M5_vrmacbuu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpybu($Rss32,$Rtt32)", -tc_8cb685d9, TypeM>, Enc_88c16c { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -16982,7 +17382,7 @@ def M5_vrmpybsu : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpybsu($Rss32,$Rtt32)", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -16992,7 +17392,7 @@ def M5_vrmpybuu : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpybu($Rss32,$Rtt32)", -tc_8c8041e6, TypeM>, Enc_a56825 { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -17002,7 +17402,7 @@ def M6_vabsdiffb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffb($Rtt32,$Rss32)", -tc_faab1248, TypeM>, Enc_ea23e4, Requires<[HasV62T]> { +tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62T]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -17012,7 +17412,7 @@ def M6_vabsdiffub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffub($Rtt32,$Rss32)", -tc_faab1248, TypeM>, Enc_ea23e4, Requires<[HasV62T]> { +tc_f49e76f4, TypeM>, Enc_ea23e4, Requires<[HasV62T]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -17022,7 +17422,7 @@ def PS_loadrbabs : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memb(#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17045,7 +17445,7 @@ def PS_loadrdabs : HInst< (outs DoubleRegs:$Rdd32), (ins u29_3Imm:$Ii), "$Rdd32 = memd(#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_509701, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_509701, AddrModeRel { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b01001; let addrMode = Absolute; @@ -17066,7 +17466,7 @@ def PS_loadrhabs : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memh(#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17089,7 +17489,7 @@ def PS_loadriabs : HInst< (outs IntRegs:$Rd32), (ins u30_2Imm:$Ii), "$Rd32 = memw(#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17112,7 +17512,7 @@ def PS_loadrubabs : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memub(#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1001; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17135,7 +17535,7 @@ def PS_loadruhabs : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memuh(#$Ii)", -tc_70cabf66, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_9c98e8af, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17158,7 +17558,7 @@ def PS_storerbabs : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Rt32), "memb(#$Ii) = $Rt32", -tc_c14739d5, TypeV2LDST>, Enc_1b64fb, AddrModeRel { +tc_a788683e, TypeV2LDST>, Enc_1b64fb, AddrModeRel { let Inst{24-21} = 0b0000; let Inst{31-27} = 0b01001; let addrMode = Absolute; @@ -17180,7 +17580,7 @@ def PS_storerbnewabs : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Nt8), "memb(#$Ii) = $Nt8.new", -tc_9e86015f, TypeV2LDST>, Enc_ad1831, AddrModeRel { +tc_ff9ee76e, TypeV2LDST>, Enc_ad1831, AddrModeRel { let Inst{12-11} = 0b00; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -17189,6 +17589,7 @@ let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; @@ -17205,7 +17606,7 @@ def PS_storerdabs : HInst< (outs), (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), "memd(#$Ii) = $Rtt32", -tc_c14739d5, TypeV2LDST>, Enc_5c124a, AddrModeRel { +tc_a788683e, TypeV2LDST>, Enc_5c124a, AddrModeRel { let Inst{24-21} = 0b0110; let Inst{31-27} = 0b01001; let addrMode = Absolute; @@ -17226,7 +17627,7 @@ def PS_storerfabs : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(#$Ii) = $Rt32.h", -tc_c14739d5, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0011; let Inst{31-27} = 0b01001; let addrMode = Absolute; @@ -17247,7 +17648,7 @@ def PS_storerhabs : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(#$Ii) = $Rt32", -tc_c14739d5, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0010; let Inst{31-27} = 0b01001; let addrMode = Absolute; @@ -17269,7 +17670,7 @@ def PS_storerhnewabs : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Nt8), "memh(#$Ii) = $Nt8.new", -tc_9e86015f, TypeV2LDST>, Enc_bc03e5, AddrModeRel { +tc_ff9ee76e, TypeV2LDST>, Enc_bc03e5, AddrModeRel { let Inst{12-11} = 0b01; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -17278,6 +17679,7 @@ let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; @@ -17294,7 +17696,7 @@ def PS_storeriabs : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Rt32), "memw(#$Ii) = $Rt32", -tc_c14739d5, TypeV2LDST>, Enc_541f26, AddrModeRel { +tc_a788683e, TypeV2LDST>, Enc_541f26, AddrModeRel { let Inst{24-21} = 0b0100; let Inst{31-27} = 0b01001; let addrMode = Absolute; @@ -17316,7 +17718,7 @@ def PS_storerinewabs : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Nt8), "memw(#$Ii) = $Nt8.new", -tc_9e86015f, TypeV2LDST>, Enc_78cbf0, AddrModeRel { +tc_ff9ee76e, TypeV2LDST>, Enc_78cbf0, AddrModeRel { let Inst{12-11} = 0b10; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -17325,6 +17727,7 @@ let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; @@ -17341,7 +17744,7 @@ def S2_addasl_rrri : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii), "$Rd32 = addasl($Rt32,$Rs32,#$Ii)", -tc_090485bb, TypeS_3op>, Enc_47ef61 { +tc_c74f796f, TypeS_3op>, Enc_47ef61 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000100000; let hasNewValue = 1; @@ -17349,24 +17752,26 @@ let opNewValue = 0; let prefersSlot3 = 1; } def S2_allocframe : HInst< -(outs), -(ins u11_3Imm:$Ii), -"allocframe(#$Ii)", -tc_0cb867f2, TypeST>, Enc_22c845 { +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, u11_3Imm:$Ii), +"allocframe($Rx32,#$Ii):raw", +tc_e216a5db, TypeST>, Enc_22c845 { let Inst{13-11} = 0b000; let Inst{31-21} = 0b10100000100; -let Inst{20-16} = 0b11101; +let hasNewValue = 1; +let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayStore = 1; -let Uses = [R29, R30, R31]; -let Defs = [R29, R30]; +let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31]; +let Defs = [R30]; +let Constraints = "$Rx32 = $Rx32in"; } def S2_asl_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asl($Rss32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_5eac98 { +tc_540fdfbc, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000000000; } @@ -17374,7 +17779,7 @@ def S2_asl_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += asl($Rss32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_70fb07 { +tc_c74f796f, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b110; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -17384,7 +17789,7 @@ def S2_asl_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= asl($Rss32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_70fb07 { +tc_84df2cd3, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -17394,7 +17799,7 @@ def S2_asl_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= asl($Rss32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_70fb07 { +tc_c74f796f, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -17404,7 +17809,7 @@ def S2_asl_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= asl($Rss32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_70fb07 { +tc_84df2cd3, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b110; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -17414,7 +17819,7 @@ def S2_asl_i_p_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 ^= asl($Rss32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_70fb07 { +tc_84df2cd3, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000010100; let prefersSlot3 = 1; @@ -17424,7 +17829,7 @@ def S2_asl_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asl($Rs32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_a05677 { +tc_540fdfbc, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -17435,7 +17840,7 @@ def S2_asl_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += asl($Rs32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_28a2dc { +tc_c74f796f, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -17448,7 +17853,7 @@ def S2_asl_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= asl($Rs32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_28a2dc { +tc_84df2cd3, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -17461,7 +17866,7 @@ def S2_asl_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= asl($Rs32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_28a2dc { +tc_c74f796f, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -17474,7 +17879,7 @@ def S2_asl_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= asl($Rs32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_28a2dc { +tc_84df2cd3, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -17487,7 +17892,7 @@ def S2_asl_i_r_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asl($Rs32,#$Ii):sat", -tc_47ab9233, TypeS_2op>, Enc_a05677 { +tc_b44c6e2a, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100010; @@ -17500,7 +17905,7 @@ def S2_asl_i_r_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 ^= asl($Rs32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_28a2dc { +tc_84df2cd3, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110100; @@ -17513,7 +17918,7 @@ def S2_asl_i_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vaslh($Rss32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_12b6e9 { +tc_540fdfbc, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b010; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000100; @@ -17522,7 +17927,7 @@ def S2_asl_i_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rdd32 = vaslw($Rss32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_7e5a82 { +tc_540fdfbc, TypeS_2op>, Enc_7e5a82 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000000010; @@ -17531,7 +17936,7 @@ def S2_asl_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = asl($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -17540,7 +17945,7 @@ def S2_asl_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += asl($Rss32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_1aa186 { +tc_c74f796f, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -17551,7 +17956,7 @@ def S2_asl_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= asl($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -17562,7 +17967,7 @@ def S2_asl_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= asl($Rss32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_1aa186 { +tc_c74f796f, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -17573,7 +17978,7 @@ def S2_asl_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= asl($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -17584,7 +17989,7 @@ def S2_asl_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= asl($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -17595,7 +18000,7 @@ def S2_asl_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asl($Rs32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_5ab2be { +tc_540fdfbc, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -17606,7 +18011,7 @@ def S2_asl_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += asl($Rs32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_2ae154 { +tc_c74f796f, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -17619,7 +18024,7 @@ def S2_asl_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= asl($Rs32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_2ae154 { +tc_84df2cd3, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -17632,7 +18037,7 @@ def S2_asl_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= asl($Rs32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_2ae154 { +tc_c74f796f, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -17645,7 +18050,7 @@ def S2_asl_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= asl($Rs32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_2ae154 { +tc_84df2cd3, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -17658,7 +18063,7 @@ def S2_asl_r_r_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asl($Rs32,$Rt32):sat", -tc_47ab9233, TypeS_3op>, Enc_5ab2be { +tc_b44c6e2a, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110000; @@ -17671,7 +18076,7 @@ def S2_asl_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vaslh($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -17680,7 +18085,7 @@ def S2_asl_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vaslw($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -17689,7 +18094,7 @@ def S2_asr_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asr($Rss32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_5eac98 { +tc_540fdfbc, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10000000000; } @@ -17697,7 +18102,7 @@ def S2_asr_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += asr($Rss32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_70fb07 { +tc_c74f796f, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b100; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -17707,7 +18112,7 @@ def S2_asr_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= asr($Rss32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_70fb07 { +tc_84df2cd3, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -17717,7 +18122,7 @@ def S2_asr_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= asr($Rss32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_70fb07 { +tc_c74f796f, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -17727,7 +18132,7 @@ def S2_asr_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= asr($Rss32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_70fb07 { +tc_84df2cd3, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b100; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -17737,7 +18142,7 @@ def S2_asr_i_p_rnd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asr($Rss32,#$Ii):rnd", -tc_63cd9d2d, TypeS_2op>, Enc_5eac98, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Enc_5eac98, Requires<[HasV5T]> { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -17746,14 +18151,14 @@ def S2_asr_i_p_rnd_goodsyntax : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asrrnd($Rss32,#$Ii)", -tc_63cd9d2d, TypeS_2op>, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> { let isPseudo = 1; } def S2_asr_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asr($Rs32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_a05677 { +tc_540fdfbc, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -17764,7 +18169,7 @@ def S2_asr_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += asr($Rs32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_28a2dc { +tc_c74f796f, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -17777,7 +18182,7 @@ def S2_asr_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= asr($Rs32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_28a2dc { +tc_84df2cd3, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -17790,7 +18195,7 @@ def S2_asr_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= asr($Rs32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_28a2dc { +tc_c74f796f, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -17803,7 +18208,7 @@ def S2_asr_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= asr($Rs32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_28a2dc { +tc_84df2cd3, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -17816,7 +18221,7 @@ def S2_asr_i_r_rnd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asr($Rs32,#$Ii):rnd", -tc_63cd9d2d, TypeS_2op>, Enc_a05677 { +tc_2b6f77c6, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100010; @@ -17828,7 +18233,7 @@ def S2_asr_i_r_rnd_goodsyntax : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asrrnd($Rs32,#$Ii)", -tc_63cd9d2d, TypeS_2op> { +tc_2b6f77c6, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -17837,7 +18242,7 @@ def S2_asr_i_svw_trun : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rd32 = vasrw($Rss32,#$Ii)", -tc_7ca2ea10, TypeS_2op>, Enc_8dec2e { +tc_1b9c9ee5, TypeS_2op>, Enc_8dec2e { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001000110; @@ -17849,7 +18254,7 @@ def S2_asr_i_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_12b6e9 { +tc_540fdfbc, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000100; @@ -17858,7 +18263,7 @@ def S2_asr_i_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rdd32 = vasrw($Rss32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_7e5a82 { +tc_540fdfbc, TypeS_2op>, Enc_7e5a82 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000000010; @@ -17867,7 +18272,7 @@ def S2_asr_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = asr($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -17876,7 +18281,7 @@ def S2_asr_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += asr($Rss32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_1aa186 { +tc_c74f796f, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -17887,7 +18292,7 @@ def S2_asr_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= asr($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -17898,7 +18303,7 @@ def S2_asr_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= asr($Rss32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_1aa186 { +tc_c74f796f, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -17909,7 +18314,7 @@ def S2_asr_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= asr($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -17920,7 +18325,7 @@ def S2_asr_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= asr($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -17931,7 +18336,7 @@ def S2_asr_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asr($Rs32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_5ab2be { +tc_540fdfbc, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -17942,7 +18347,7 @@ def S2_asr_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += asr($Rs32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_2ae154 { +tc_c74f796f, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -17955,7 +18360,7 @@ def S2_asr_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= asr($Rs32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_2ae154 { +tc_84df2cd3, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -17968,7 +18373,7 @@ def S2_asr_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= asr($Rs32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_2ae154 { +tc_c74f796f, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -17981,7 +18386,7 @@ def S2_asr_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= asr($Rs32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_2ae154 { +tc_84df2cd3, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -17994,7 +18399,7 @@ def S2_asr_r_r_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asr($Rs32,$Rt32):sat", -tc_47ab9233, TypeS_3op>, Enc_5ab2be { +tc_b44c6e2a, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110000; @@ -18007,7 +18412,7 @@ def S2_asr_r_svw_trun : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = vasrw($Rss32,$Rt32)", -tc_7ca2ea10, TypeS_3op>, Enc_3d5b28 { +tc_1b9c9ee5, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -18019,7 +18424,7 @@ def S2_asr_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vasrh($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -18028,7 +18433,7 @@ def S2_asr_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vasrw($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -18037,7 +18442,7 @@ def S2_brev : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = brev($Rs32)", -tc_ab1b5e74, TypeS_2op>, Enc_5e2823 { +tc_d088982c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -18048,7 +18453,7 @@ def S2_brevp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = brev($Rss32)", -tc_ab1b5e74, TypeS_2op>, Enc_b9c5fb { +tc_d088982c, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18057,7 +18462,7 @@ def S2_cabacdecbin : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = decbin($Rss32,$Rtt32)", -tc_5d806107, TypeS_3op>, Enc_a56825 { +tc_c6ebf8dd, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -18069,7 +18474,7 @@ def S2_cl0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = cl0($Rs32)", -tc_ab1b5e74, TypeS_2op>, Enc_5e2823 { +tc_d088982c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18080,7 +18485,7 @@ def S2_cl0p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = cl0($Rss32)", -tc_ab1b5e74, TypeS_2op>, Enc_90cd8b { +tc_d088982c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -18091,7 +18496,7 @@ def S2_cl1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = cl1($Rs32)", -tc_ab1b5e74, TypeS_2op>, Enc_5e2823 { +tc_d088982c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18102,7 +18507,7 @@ def S2_cl1p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = cl1($Rss32)", -tc_ab1b5e74, TypeS_2op>, Enc_90cd8b { +tc_d088982c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -18113,7 +18518,7 @@ def S2_clb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = clb($Rs32)", -tc_ab1b5e74, TypeS_2op>, Enc_5e2823 { +tc_d088982c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18124,7 +18529,7 @@ def S2_clbnorm : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = normamt($Rs32)", -tc_ab1b5e74, TypeS_2op>, Enc_5e2823 { +tc_d088982c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18135,7 +18540,7 @@ def S2_clbp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = clb($Rss32)", -tc_ab1b5e74, TypeS_2op>, Enc_90cd8b { +tc_d088982c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -18146,7 +18551,7 @@ def S2_clrbit_i : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = clrbit($Rs32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_a05677 { +tc_540fdfbc, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100110; @@ -18157,7 +18562,7 @@ def S2_clrbit_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = clrbit($Rs32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_5ab2be { +tc_540fdfbc, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -18168,7 +18573,7 @@ def S2_ct0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = ct0($Rs32)", -tc_ab1b5e74, TypeS_2op>, Enc_5e2823 { +tc_d088982c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -18179,7 +18584,7 @@ def S2_ct0p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = ct0($Rss32)", -tc_ab1b5e74, TypeS_2op>, Enc_90cd8b { +tc_d088982c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000111; let hasNewValue = 1; @@ -18190,7 +18595,7 @@ def S2_ct1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = ct1($Rs32)", -tc_ab1b5e74, TypeS_2op>, Enc_5e2823 { +tc_d088982c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -18201,7 +18606,7 @@ def S2_ct1p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = ct1($Rss32)", -tc_ab1b5e74, TypeS_2op>, Enc_90cd8b { +tc_d088982c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000111; let hasNewValue = 1; @@ -18212,7 +18617,7 @@ def S2_deinterleave : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = deinterleave($Rss32)", -tc_ab1b5e74, TypeS_2op>, Enc_b9c5fb { +tc_d088982c, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18221,7 +18626,7 @@ def S2_extractu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), "$Rd32 = extractu($Rs32,#$Ii,#$II)", -tc_c0cd91a8, TypeS_2op>, Enc_b388cf { +tc_c74f796f, TypeS_2op>, Enc_b388cf { let Inst{13-13} = 0b0; let Inst{31-23} = 0b100011010; let hasNewValue = 1; @@ -18232,7 +18637,7 @@ def S2_extractu_rp : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rd32 = extractu($Rs32,$Rtt32)", -tc_87601822, TypeS_3op>, Enc_e07374 { +tc_2b6f77c6, TypeS_3op>, Enc_e07374 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001001000; @@ -18244,7 +18649,7 @@ def S2_extractup : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), "$Rdd32 = extractu($Rss32,#$Ii,#$II)", -tc_c0cd91a8, TypeS_2op>, Enc_b84c4c { +tc_c74f796f, TypeS_2op>, Enc_b84c4c { let Inst{31-24} = 0b10000001; let prefersSlot3 = 1; } @@ -18252,7 +18657,7 @@ def S2_extractup_rp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = extractu($Rss32,$Rtt32)", -tc_87601822, TypeS_3op>, Enc_a56825 { +tc_2b6f77c6, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -18262,7 +18667,7 @@ def S2_insert : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = insert($Rs32,#$Ii,#$II)", -tc_d95f4e98, TypeS_2op>, Enc_a1e29d { +tc_87735c3b, TypeS_2op>, Enc_a1e29d { let Inst{13-13} = 0b0; let Inst{31-23} = 0b100011110; let hasNewValue = 1; @@ -18274,7 +18679,7 @@ def S2_insert_rp : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rx32 = insert($Rs32,$Rtt32)", -tc_3c10f809, TypeS_3op>, Enc_179b35 { +tc_84df2cd3, TypeS_3op>, Enc_179b35 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001000000; @@ -18287,7 +18692,7 @@ def S2_insertp : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), "$Rxx32 = insert($Rss32,#$Ii,#$II)", -tc_d95f4e98, TypeS_2op>, Enc_143a3c { +tc_87735c3b, TypeS_2op>, Enc_143a3c { let Inst{31-24} = 0b10000011; let prefersSlot3 = 1; let Constraints = "$Rxx32 = $Rxx32in"; @@ -18296,7 +18701,7 @@ def S2_insertp_rp : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 = insert($Rss32,$Rtt32)", -tc_3c10f809, TypeS_3op>, Enc_88c16c { +tc_84df2cd3, TypeS_3op>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001010000; @@ -18307,7 +18712,7 @@ def S2_interleave : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = interleave($Rss32)", -tc_ab1b5e74, TypeS_2op>, Enc_b9c5fb { +tc_d088982c, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18316,7 +18721,7 @@ def S2_lfsp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = lfs($Rss32,$Rtt32)", -tc_87601822, TypeS_3op>, Enc_a56825 { +tc_2b6f77c6, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -18326,7 +18731,7 @@ def S2_lsl_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = lsl($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -18335,7 +18740,7 @@ def S2_lsl_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += lsl($Rss32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_1aa186 { +tc_c74f796f, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -18346,7 +18751,7 @@ def S2_lsl_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= lsl($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -18357,7 +18762,7 @@ def S2_lsl_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= lsl($Rss32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_1aa186 { +tc_c74f796f, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -18368,7 +18773,7 @@ def S2_lsl_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= lsl($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -18379,7 +18784,7 @@ def S2_lsl_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= lsl($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -18390,7 +18795,7 @@ def S2_lsl_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = lsl($Rs32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_5ab2be { +tc_540fdfbc, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -18401,7 +18806,7 @@ def S2_lsl_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += lsl($Rs32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_2ae154 { +tc_c74f796f, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -18414,7 +18819,7 @@ def S2_lsl_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= lsl($Rs32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_2ae154 { +tc_84df2cd3, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -18427,7 +18832,7 @@ def S2_lsl_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= lsl($Rs32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_2ae154 { +tc_c74f796f, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -18440,7 +18845,7 @@ def S2_lsl_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= lsl($Rs32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_2ae154 { +tc_84df2cd3, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -18453,7 +18858,7 @@ def S2_lsl_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlslh($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -18462,7 +18867,7 @@ def S2_lsl_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlslw($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -18471,7 +18876,7 @@ def S2_lsr_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = lsr($Rss32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_5eac98 { +tc_540fdfbc, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000000000; } @@ -18479,7 +18884,7 @@ def S2_lsr_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += lsr($Rss32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_70fb07 { +tc_c74f796f, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b101; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -18489,7 +18894,7 @@ def S2_lsr_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= lsr($Rss32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_70fb07 { +tc_84df2cd3, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -18499,7 +18904,7 @@ def S2_lsr_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= lsr($Rss32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_70fb07 { +tc_c74f796f, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -18509,7 +18914,7 @@ def S2_lsr_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= lsr($Rss32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_70fb07 { +tc_84df2cd3, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b101; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -18519,7 +18924,7 @@ def S2_lsr_i_p_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 ^= lsr($Rss32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_70fb07 { +tc_84df2cd3, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000010100; let prefersSlot3 = 1; @@ -18529,7 +18934,7 @@ def S2_lsr_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = lsr($Rs32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_a05677 { +tc_540fdfbc, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -18540,7 +18945,7 @@ def S2_lsr_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += lsr($Rs32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_28a2dc { +tc_c74f796f, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -18553,7 +18958,7 @@ def S2_lsr_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= lsr($Rs32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_28a2dc { +tc_84df2cd3, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -18566,7 +18971,7 @@ def S2_lsr_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= lsr($Rs32,#$Ii)", -tc_c0cd91a8, TypeS_2op>, Enc_28a2dc { +tc_c74f796f, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -18579,7 +18984,7 @@ def S2_lsr_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= lsr($Rs32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_28a2dc { +tc_84df2cd3, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -18592,7 +18997,7 @@ def S2_lsr_i_r_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 ^= lsr($Rs32,#$Ii)", -tc_3c10f809, TypeS_2op>, Enc_28a2dc { +tc_84df2cd3, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110100; @@ -18605,7 +19010,7 @@ def S2_lsr_i_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vlsrh($Rss32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_12b6e9 { +tc_540fdfbc, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b001; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000100; @@ -18614,7 +19019,7 @@ def S2_lsr_i_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rdd32 = vlsrw($Rss32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_7e5a82 { +tc_540fdfbc, TypeS_2op>, Enc_7e5a82 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000000010; @@ -18623,7 +19028,7 @@ def S2_lsr_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = lsr($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -18632,7 +19037,7 @@ def S2_lsr_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += lsr($Rss32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_1aa186 { +tc_c74f796f, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -18643,7 +19048,7 @@ def S2_lsr_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= lsr($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -18654,7 +19059,7 @@ def S2_lsr_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= lsr($Rss32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_1aa186 { +tc_c74f796f, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -18665,7 +19070,7 @@ def S2_lsr_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= lsr($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -18676,7 +19081,7 @@ def S2_lsr_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= lsr($Rss32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_1aa186 { +tc_84df2cd3, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -18687,7 +19092,7 @@ def S2_lsr_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = lsr($Rs32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_5ab2be { +tc_540fdfbc, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -18698,7 +19103,7 @@ def S2_lsr_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += lsr($Rs32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_2ae154 { +tc_c74f796f, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -18711,7 +19116,7 @@ def S2_lsr_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= lsr($Rs32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_2ae154 { +tc_84df2cd3, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -18724,7 +19129,7 @@ def S2_lsr_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= lsr($Rs32,$Rt32)", -tc_c0cd91a8, TypeS_3op>, Enc_2ae154 { +tc_c74f796f, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -18737,7 +19142,7 @@ def S2_lsr_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= lsr($Rs32,$Rt32)", -tc_3c10f809, TypeS_3op>, Enc_2ae154 { +tc_84df2cd3, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -18750,7 +19155,7 @@ def S2_lsr_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlsrh($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -18759,7 +19164,7 @@ def S2_lsr_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlsrw($Rss32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_927852 { +tc_540fdfbc, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -18768,7 +19173,7 @@ def S2_packhl : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = packhl($Rs32,$Rt32)", -tc_548f402d, TypeALU32_3op>, Enc_be32a5 { +tc_b9488031, TypeALU32_3op>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110101100; @@ -18778,7 +19183,7 @@ def S2_parityp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = parity($Rss32,$Rtt32)", -tc_87601822, TypeALU64>, Enc_d2216a { +tc_2b6f77c6, TypeALU64>, Enc_d2216a { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010000000; @@ -18790,7 +19195,7 @@ def S2_pstorerbf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb($Rs32+#$Ii) = $Rt32", -tc_3d905451, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_8b15472a, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100000; let isPredicated = 1; @@ -18812,7 +19217,7 @@ def S2_pstorerbf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb($Rx32++#$Ii) = $Rt32", -tc_9b73d261, TypeST>, Enc_cc449f, AddrModeRel { +tc_cd7374a0, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -18830,7 +19235,7 @@ def S2_pstorerbf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memb($Rs32) = $Rt32", -tc_3d905451, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -18838,7 +19243,7 @@ def S2_pstorerbfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32", -tc_7675c0e9, TypeST>, Enc_cc449f, AddrModeRel { +tc_74e47fd9, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -18857,7 +19262,7 @@ def S2_pstorerbnewf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new", -tc_9da3628f, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_594ab548, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000100101; @@ -18867,6 +19272,7 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let InputType = "imm"; @@ -18882,7 +19288,7 @@ def S2_pstorerbnewf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new", -tc_e2480a7f, TypeST>, Enc_52a5dd, AddrModeRel { +tc_d9f95eef, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-11} = 0b100; @@ -18893,6 +19299,7 @@ let addrMode = PostInc; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; @@ -18903,7 +19310,7 @@ def S2_pstorerbnewf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4) memb($Rs32) = $Nt8.new", -tc_9da3628f, TypeMAPPING> { +tc_594ab548, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -18912,7 +19319,7 @@ def S2_pstorerbnewfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", -tc_8fab9ac3, TypeST>, Enc_52a5dd, AddrModeRel { +tc_d24b2d85, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -18924,6 +19331,7 @@ let accessSize = ByteAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; @@ -18934,7 +19342,7 @@ def S2_pstorerbnewt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new", -tc_9da3628f, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_594ab548, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000000101; @@ -18943,6 +19351,7 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let InputType = "imm"; @@ -18958,7 +19367,7 @@ def S2_pstorerbnewt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new", -tc_e2480a7f, TypeST>, Enc_52a5dd, AddrModeRel { +tc_d9f95eef, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-11} = 0b100; @@ -18968,6 +19377,7 @@ let addrMode = PostInc; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; @@ -18978,7 +19388,7 @@ def S2_pstorerbnewt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4) memb($Rs32) = $Nt8.new", -tc_9da3628f, TypeMAPPING> { +tc_594ab548, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -18987,7 +19397,7 @@ def S2_pstorerbnewtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", -tc_8fab9ac3, TypeST>, Enc_52a5dd, AddrModeRel { +tc_d24b2d85, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -18998,6 +19408,7 @@ let accessSize = ByteAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; @@ -19008,7 +19419,7 @@ def S2_pstorerbt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb($Rs32+#$Ii) = $Rt32", -tc_3d905451, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_8b15472a, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000000; let isPredicated = 1; @@ -19029,7 +19440,7 @@ def S2_pstorerbt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb($Rx32++#$Ii) = $Rt32", -tc_9b73d261, TypeST>, Enc_cc449f, AddrModeRel { +tc_cd7374a0, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19046,7 +19457,7 @@ def S2_pstorerbt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memb($Rs32) = $Rt32", -tc_3d905451, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19054,7 +19465,7 @@ def S2_pstorerbtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32", -tc_7675c0e9, TypeST>, Enc_cc449f, AddrModeRel { +tc_74e47fd9, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19072,7 +19483,7 @@ def S2_pstorerdf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32", -tc_3d905451, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_8b15472a, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100110; let isPredicated = 1; @@ -19093,7 +19504,7 @@ def S2_pstorerdf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32", -tc_9b73d261, TypeST>, Enc_9a33d5, AddrModeRel { +tc_cd7374a0, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19111,7 +19522,7 @@ def S2_pstorerdf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rs32) = $Rtt32", -tc_3d905451, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19119,7 +19530,7 @@ def S2_pstorerdfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32", -tc_7675c0e9, TypeST>, Enc_9a33d5, AddrModeRel { +tc_74e47fd9, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19138,7 +19549,7 @@ def S2_pstorerdt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rs32+#$Ii) = $Rtt32", -tc_3d905451, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_8b15472a, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000110; let isPredicated = 1; @@ -19158,7 +19569,7 @@ def S2_pstorerdt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rx32++#$Ii) = $Rtt32", -tc_9b73d261, TypeST>, Enc_9a33d5, AddrModeRel { +tc_cd7374a0, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19175,7 +19586,7 @@ def S2_pstorerdt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rs32) = $Rtt32", -tc_3d905451, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19183,7 +19594,7 @@ def S2_pstorerdtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32", -tc_7675c0e9, TypeST>, Enc_9a33d5, AddrModeRel { +tc_74e47fd9, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19201,7 +19612,7 @@ def S2_pstorerff_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h", -tc_3d905451, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100011; let isPredicated = 1; @@ -19222,7 +19633,7 @@ def S2_pstorerff_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h", -tc_9b73d261, TypeST>, Enc_b886fd, AddrModeRel { +tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19240,7 +19651,7 @@ def S2_pstorerff_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32) = $Rt32.h", -tc_3d905451, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19248,7 +19659,7 @@ def S2_pstorerffnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", -tc_7675c0e9, TypeST>, Enc_b886fd, AddrModeRel { +tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19267,7 +19678,7 @@ def S2_pstorerft_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h", -tc_3d905451, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000011; let isPredicated = 1; @@ -19287,7 +19698,7 @@ def S2_pstorerft_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h", -tc_9b73d261, TypeST>, Enc_b886fd, AddrModeRel { +tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19304,7 +19715,7 @@ def S2_pstorerft_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memh($Rs32) = $Rt32.h", -tc_3d905451, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19312,7 +19723,7 @@ def S2_pstorerftnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", -tc_7675c0e9, TypeST>, Enc_b886fd, AddrModeRel { +tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19330,7 +19741,7 @@ def S2_pstorerhf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32", -tc_3d905451, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100010; let isPredicated = 1; @@ -19352,7 +19763,7 @@ def S2_pstorerhf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32", -tc_9b73d261, TypeST>, Enc_b886fd, AddrModeRel { +tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19370,7 +19781,7 @@ def S2_pstorerhf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32) = $Rt32", -tc_3d905451, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19378,7 +19789,7 @@ def S2_pstorerhfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32", -tc_7675c0e9, TypeST>, Enc_b886fd, AddrModeRel { +tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19397,7 +19808,7 @@ def S2_pstorerhnewf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new", -tc_9da3628f, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_594ab548, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000100101; @@ -19407,6 +19818,7 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let InputType = "imm"; @@ -19422,7 +19834,7 @@ def S2_pstorerhnewf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new", -tc_e2480a7f, TypeST>, Enc_31aa6a, AddrModeRel { +tc_d9f95eef, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-11} = 0b101; @@ -19433,6 +19845,7 @@ let addrMode = PostInc; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; @@ -19443,7 +19856,7 @@ def S2_pstorerhnewf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4) memh($Rs32) = $Nt8.new", -tc_9da3628f, TypeMAPPING> { +tc_594ab548, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -19452,7 +19865,7 @@ def S2_pstorerhnewfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", -tc_8fab9ac3, TypeST>, Enc_31aa6a, AddrModeRel { +tc_d24b2d85, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -19464,6 +19877,7 @@ let accessSize = HalfWordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; @@ -19474,7 +19888,7 @@ def S2_pstorerhnewt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new", -tc_9da3628f, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_594ab548, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000000101; @@ -19483,6 +19897,7 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let InputType = "imm"; @@ -19498,7 +19913,7 @@ def S2_pstorerhnewt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new", -tc_e2480a7f, TypeST>, Enc_31aa6a, AddrModeRel { +tc_d9f95eef, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-11} = 0b101; @@ -19508,6 +19923,7 @@ let addrMode = PostInc; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; @@ -19518,7 +19934,7 @@ def S2_pstorerhnewt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4) memh($Rs32) = $Nt8.new", -tc_9da3628f, TypeMAPPING> { +tc_594ab548, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -19527,7 +19943,7 @@ def S2_pstorerhnewtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", -tc_8fab9ac3, TypeST>, Enc_31aa6a, AddrModeRel { +tc_d24b2d85, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -19538,6 +19954,7 @@ let accessSize = HalfWordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; @@ -19548,7 +19965,7 @@ def S2_pstorerht_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+#$Ii) = $Rt32", -tc_3d905451, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8b15472a, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000010; let isPredicated = 1; @@ -19569,7 +19986,7 @@ def S2_pstorerht_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rx32++#$Ii) = $Rt32", -tc_9b73d261, TypeST>, Enc_b886fd, AddrModeRel { +tc_cd7374a0, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19586,7 +20003,7 @@ def S2_pstorerht_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memh($Rs32) = $Rt32", -tc_3d905451, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19594,7 +20011,7 @@ def S2_pstorerhtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32", -tc_7675c0e9, TypeST>, Enc_b886fd, AddrModeRel { +tc_74e47fd9, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19612,7 +20029,7 @@ def S2_pstorerif_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw($Rs32+#$Ii) = $Rt32", -tc_3d905451, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_8b15472a, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100100; let isPredicated = 1; @@ -19634,7 +20051,7 @@ def S2_pstorerif_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw($Rx32++#$Ii) = $Rt32", -tc_9b73d261, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_cd7374a0, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19652,7 +20069,7 @@ def S2_pstorerif_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memw($Rs32) = $Rt32", -tc_3d905451, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19660,7 +20077,7 @@ def S2_pstorerifnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32", -tc_7675c0e9, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_74e47fd9, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19680,7 +20097,7 @@ def S2_pstorerinewf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new", -tc_9da3628f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_594ab548, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000100101; @@ -19690,6 +20107,7 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let InputType = "imm"; @@ -19705,7 +20123,7 @@ def S2_pstorerinewf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new", -tc_e2480a7f, TypeST>, Enc_65f095, AddrModeRel { +tc_d9f95eef, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-11} = 0b110; @@ -19716,6 +20134,7 @@ let addrMode = PostInc; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; @@ -19726,7 +20145,7 @@ def S2_pstorerinewf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4) memw($Rs32) = $Nt8.new", -tc_9da3628f, TypeMAPPING> { +tc_594ab548, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -19735,7 +20154,7 @@ def S2_pstorerinewfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", -tc_8fab9ac3, TypeST>, Enc_65f095, AddrModeRel { +tc_d24b2d85, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -19747,6 +20166,7 @@ let accessSize = WordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; @@ -19757,7 +20177,7 @@ def S2_pstorerinewt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new", -tc_9da3628f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_594ab548, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000000101; @@ -19766,6 +20186,7 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let InputType = "imm"; @@ -19781,7 +20202,7 @@ def S2_pstorerinewt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new", -tc_e2480a7f, TypeST>, Enc_65f095, AddrModeRel { +tc_d9f95eef, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-11} = 0b110; @@ -19791,6 +20212,7 @@ let addrMode = PostInc; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; @@ -19801,7 +20223,7 @@ def S2_pstorerinewt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4) memw($Rs32) = $Nt8.new", -tc_9da3628f, TypeMAPPING> { +tc_594ab548, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -19810,7 +20232,7 @@ def S2_pstorerinewtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", -tc_8fab9ac3, TypeST>, Enc_65f095, AddrModeRel { +tc_d24b2d85, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -19821,6 +20243,7 @@ let accessSize = WordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; @@ -19831,7 +20254,7 @@ def S2_pstorerit_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw($Rs32+#$Ii) = $Rt32", -tc_3d905451, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_8b15472a, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000100; let isPredicated = 1; @@ -19852,7 +20275,7 @@ def S2_pstorerit_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw($Rx32++#$Ii) = $Rt32", -tc_9b73d261, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_cd7374a0, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19869,7 +20292,7 @@ def S2_pstorerit_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memw($Rs32) = $Rt32", -tc_3d905451, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19877,7 +20300,7 @@ def S2_pstoreritnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32", -tc_7675c0e9, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_74e47fd9, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19895,7 +20318,7 @@ def S2_setbit_i : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = setbit($Rs32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_a05677 { +tc_540fdfbc, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100110; @@ -19906,7 +20329,7 @@ def S2_setbit_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = setbit($Rs32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_5ab2be { +tc_540fdfbc, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -19917,7 +20340,7 @@ def S2_shuffeb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = shuffeb($Rss32,$Rtt32)", -tc_9c18c9a5, TypeS_3op>, Enc_a56825 { +tc_540fdfbc, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -19926,7 +20349,7 @@ def S2_shuffeh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = shuffeh($Rss32,$Rtt32)", -tc_9c18c9a5, TypeS_3op>, Enc_a56825 { +tc_540fdfbc, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -19935,7 +20358,7 @@ def S2_shuffob : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = shuffob($Rtt32,$Rss32)", -tc_9c18c9a5, TypeS_3op>, Enc_ea23e4 { +tc_540fdfbc, TypeS_3op>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -19944,7 +20367,7 @@ def S2_shuffoh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = shuffoh($Rtt32,$Rss32)", -tc_9c18c9a5, TypeS_3op>, Enc_ea23e4 { +tc_540fdfbc, TypeS_3op>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -19953,7 +20376,7 @@ def S2_storerb_io : HInst< (outs), (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) = $Rt32", -tc_53ee6546, TypeST>, Enc_448f7f, AddrModeRel { +tc_05b6c987, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; @@ -19974,7 +20397,7 @@ def S2_storerb_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++$Mu2:brev) = $Rt32", -tc_20a8e109, TypeST>, Enc_d5c73f, AddrModeRel { +tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111000; let accessSize = ByteAccess; @@ -19987,7 +20410,7 @@ def S2_storerb_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++#$Ii:circ($Mu2)) = $Rt32", -tc_251c87b2, TypeST>, Enc_b15941 { +tc_9fdb5406, TypeST>, Enc_b15941, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001000; @@ -19995,6 +20418,7 @@ let addrMode = PostInc; let accessSize = ByteAccess; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storerb_pci"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20002,13 +20426,14 @@ def S2_storerb_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++I:circ($Mu2)) = $Rt32", -tc_20a8e109, TypeST>, Enc_d5c73f { +tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001000; let addrMode = PostInc; let accessSize = ByteAccess; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storerb_pcr"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20016,7 +20441,7 @@ def S2_storerb_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "memb($Rx32++#$Ii) = $Rt32", -tc_20a8e109, TypeST>, Enc_10bc21, AddrModeRel { +tc_f86c328a, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -20024,6 +20449,7 @@ let Inst{31-21} = 0b10101011000; let addrMode = PostInc; let accessSize = ByteAccess; let mayStore = 1; +let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; let isPredicable = 1; let isNVStorable = 1; @@ -20033,7 +20459,7 @@ def S2_storerb_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++$Mu2) = $Rt32", -tc_20a8e109, TypeST>, Enc_d5c73f { +tc_f86c328a, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101000; let addrMode = PostInc; @@ -20046,7 +20472,7 @@ def S2_storerb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) = $Rt32", -tc_53ee6546, TypeMAPPING> { +tc_05b6c987, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20054,7 +20480,7 @@ def S2_storerbgp : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Rt32), "memb(gp+#$Ii) = $Rt32", -tc_c14739d5, TypeV2LDST>, Enc_1b64fb, AddrModeRel { +tc_a788683e, TypeV2LDST>, Enc_1b64fb, AddrModeRel { let Inst{24-21} = 0b0000; let Inst{31-27} = 0b01001; let accessSize = ByteAccess; @@ -20072,7 +20498,7 @@ def S2_storerbnew_io : HInst< (outs), (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8), "memb($Rs32+#$Ii) = $Nt8.new", -tc_6c576d46, TypeST>, Enc_4df4e9, AddrModeRel { +tc_f7dd9c9f, TypeST>, Enc_4df4e9, AddrModeRel { let Inst{12-11} = 0b00; let Inst{24-21} = 0b1101; let Inst{31-27} = 0b10100; @@ -20080,6 +20506,7 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let InputType = "imm"; @@ -20096,13 +20523,14 @@ def S2_storerbnew_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++$Mu2:brev) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_8dbe85, AddrModeRel { +tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101111101; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let BaseOpcode = "S2_storerb_pbr"; let opNewValue = 3; @@ -20112,7 +20540,7 @@ def S2_storerbnew_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", -tc_9c68db63, TypeST>, Enc_96ce4f { +tc_9d5941c7, TypeST>, Enc_96ce4f, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{12-11} = 0b00; @@ -20121,8 +20549,10 @@ let addrMode = PostInc; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storerb_pci"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20130,7 +20560,7 @@ def S2_storerbnew_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++I:circ($Mu2)) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_8dbe85 { +tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101001101; @@ -20138,8 +20568,10 @@ let addrMode = PostInc; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storerb_pcr"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } @@ -20147,7 +20579,7 @@ def S2_storerbnew_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "memb($Rx32++#$Ii) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_c7cd90, AddrModeRel { +tc_e7d02c66, TypeST>, Enc_c7cd90, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-11} = 0b000; @@ -20156,6 +20588,7 @@ let addrMode = PostInc; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let BaseOpcode = "S2_storerb_pi"; let isPredicable = 1; @@ -20167,7 +20600,7 @@ def S2_storerbnew_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++$Mu2) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_8dbe85 { +tc_e7d02c66, TypeST>, Enc_8dbe85 { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101101101; @@ -20175,6 +20608,7 @@ let addrMode = PostInc; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; @@ -20183,7 +20617,7 @@ def S2_storerbnew_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Nt8), "memb($Rs32) = $Nt8.new", -tc_6c576d46, TypeMAPPING> { +tc_f7dd9c9f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 1; @@ -20192,13 +20626,14 @@ def S2_storerbnewgp : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Nt8), "memb(gp+#$Ii) = $Nt8.new", -tc_9e86015f, TypeV2LDST>, Enc_ad1831, AddrModeRel { +tc_ff9ee76e, TypeV2LDST>, Enc_ad1831, AddrModeRel { let Inst{12-11} = 0b00; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let Uses = [GP]; let BaseOpcode = "S2_storerbabs"; @@ -20213,7 +20648,7 @@ def S2_storerd_io : HInst< (outs), (ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32), "memd($Rs32+#$Ii) = $Rtt32", -tc_53ee6546, TypeST>, Enc_ce6828, AddrModeRel { +tc_05b6c987, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; @@ -20233,7 +20668,7 @@ def S2_storerd_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++$Mu2:brev) = $Rtt32", -tc_20a8e109, TypeST>, Enc_928ca1 { +tc_f86c328a, TypeST>, Enc_928ca1 { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111110; let accessSize = DoubleWordAccess; @@ -20244,7 +20679,7 @@ def S2_storerd_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32", -tc_251c87b2, TypeST>, Enc_395cc4 { +tc_9fdb5406, TypeST>, Enc_395cc4 { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001110; @@ -20258,7 +20693,7 @@ def S2_storerd_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++I:circ($Mu2)) = $Rtt32", -tc_20a8e109, TypeST>, Enc_928ca1 { +tc_f86c328a, TypeST>, Enc_928ca1 { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001110; let addrMode = PostInc; @@ -20271,7 +20706,7 @@ def S2_storerd_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "memd($Rx32++#$Ii) = $Rtt32", -tc_20a8e109, TypeST>, Enc_85bf58, AddrModeRel { +tc_f86c328a, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -20288,7 +20723,7 @@ def S2_storerd_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++$Mu2) = $Rtt32", -tc_20a8e109, TypeST>, Enc_928ca1 { +tc_f86c328a, TypeST>, Enc_928ca1 { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101110; let addrMode = PostInc; @@ -20300,7 +20735,7 @@ def S2_storerd_zomap : HInst< (outs), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "memd($Rs32) = $Rtt32", -tc_53ee6546, TypeMAPPING> { +tc_05b6c987, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20308,7 +20743,7 @@ def S2_storerdgp : HInst< (outs), (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), "memd(gp+#$Ii) = $Rtt32", -tc_c14739d5, TypeV2LDST>, Enc_5c124a, AddrModeRel { +tc_a788683e, TypeV2LDST>, Enc_5c124a, AddrModeRel { let Inst{24-21} = 0b0110; let Inst{31-27} = 0b01001; let accessSize = DoubleWordAccess; @@ -20325,7 +20760,7 @@ def S2_storerf_io : HInst< (outs), (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) = $Rt32.h", -tc_53ee6546, TypeST>, Enc_e957fb, AddrModeRel { +tc_05b6c987, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; @@ -20345,7 +20780,7 @@ def S2_storerf_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2:brev) = $Rt32.h", -tc_20a8e109, TypeST>, Enc_d5c73f { +tc_f86c328a, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111011; let accessSize = HalfWordAccess; @@ -20356,7 +20791,7 @@ def S2_storerf_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h", -tc_251c87b2, TypeST>, Enc_935d9b { +tc_9fdb5406, TypeST>, Enc_935d9b { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001011; @@ -20370,7 +20805,7 @@ def S2_storerf_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++I:circ($Mu2)) = $Rt32.h", -tc_20a8e109, TypeST>, Enc_d5c73f { +tc_f86c328a, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001011; let addrMode = PostInc; @@ -20383,7 +20818,7 @@ def S2_storerf_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "memh($Rx32++#$Ii) = $Rt32.h", -tc_20a8e109, TypeST>, Enc_052c7d, AddrModeRel { +tc_f86c328a, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -20400,7 +20835,7 @@ def S2_storerf_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2) = $Rt32.h", -tc_20a8e109, TypeST>, Enc_d5c73f { +tc_f86c328a, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101011; let addrMode = PostInc; @@ -20412,7 +20847,7 @@ def S2_storerf_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) = $Rt32.h", -tc_53ee6546, TypeMAPPING> { +tc_05b6c987, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20420,7 +20855,7 @@ def S2_storerfgp : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(gp+#$Ii) = $Rt32.h", -tc_c14739d5, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0011; let Inst{31-27} = 0b01001; let accessSize = HalfWordAccess; @@ -20437,7 +20872,7 @@ def S2_storerh_io : HInst< (outs), (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) = $Rt32", -tc_53ee6546, TypeST>, Enc_e957fb, AddrModeRel { +tc_05b6c987, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; @@ -20458,7 +20893,7 @@ def S2_storerh_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2:brev) = $Rt32", -tc_20a8e109, TypeST>, Enc_d5c73f, AddrModeRel { +tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111010; let accessSize = HalfWordAccess; @@ -20471,7 +20906,7 @@ def S2_storerh_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32", -tc_251c87b2, TypeST>, Enc_935d9b { +tc_9fdb5406, TypeST>, Enc_935d9b, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001010; @@ -20479,6 +20914,7 @@ let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storerh_pci"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20486,13 +20922,14 @@ def S2_storerh_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++I:circ($Mu2)) = $Rt32", -tc_20a8e109, TypeST>, Enc_d5c73f { +tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001010; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storerh_pcr"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20500,7 +20937,7 @@ def S2_storerh_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "memh($Rx32++#$Ii) = $Rt32", -tc_20a8e109, TypeST>, Enc_052c7d, AddrModeRel { +tc_f86c328a, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -20508,6 +20945,7 @@ let Inst{31-21} = 0b10101011010; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; +let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; let isPredicable = 1; let isNVStorable = 1; @@ -20517,7 +20955,7 @@ def S2_storerh_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2) = $Rt32", -tc_20a8e109, TypeST>, Enc_d5c73f { +tc_f86c328a, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101010; let addrMode = PostInc; @@ -20530,7 +20968,7 @@ def S2_storerh_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) = $Rt32", -tc_53ee6546, TypeMAPPING> { +tc_05b6c987, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20538,7 +20976,7 @@ def S2_storerhgp : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(gp+#$Ii) = $Rt32", -tc_c14739d5, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_a788683e, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0010; let Inst{31-27} = 0b01001; let accessSize = HalfWordAccess; @@ -20556,7 +20994,7 @@ def S2_storerhnew_io : HInst< (outs), (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8), "memh($Rs32+#$Ii) = $Nt8.new", -tc_6c576d46, TypeST>, Enc_0d8870, AddrModeRel { +tc_f7dd9c9f, TypeST>, Enc_0d8870, AddrModeRel { let Inst{12-11} = 0b01; let Inst{24-21} = 0b1101; let Inst{31-27} = 0b10100; @@ -20564,6 +21002,7 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let InputType = "imm"; @@ -20580,13 +21019,14 @@ def S2_storerhnew_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++$Mu2:brev) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_8dbe85, AddrModeRel { +tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101111101; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let BaseOpcode = "S2_storerh_pbr"; let opNewValue = 3; @@ -20596,7 +21036,7 @@ def S2_storerhnew_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", -tc_9c68db63, TypeST>, Enc_91b9fe { +tc_9d5941c7, TypeST>, Enc_91b9fe, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{12-11} = 0b01; @@ -20605,8 +21045,10 @@ let addrMode = PostInc; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storerh_pci"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20614,7 +21056,7 @@ def S2_storerhnew_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++I:circ($Mu2)) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_8dbe85 { +tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101001101; @@ -20622,8 +21064,10 @@ let addrMode = PostInc; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storerh_pcr"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } @@ -20631,7 +21075,7 @@ def S2_storerhnew_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "memh($Rx32++#$Ii) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_e26546, AddrModeRel { +tc_e7d02c66, TypeST>, Enc_e26546, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-11} = 0b001; @@ -20640,6 +21084,7 @@ let addrMode = PostInc; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let BaseOpcode = "S2_storerh_pi"; let isNVStorable = 1; @@ -20651,7 +21096,7 @@ def S2_storerhnew_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++$Mu2) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_8dbe85 { +tc_e7d02c66, TypeST>, Enc_8dbe85 { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101101101; @@ -20659,6 +21104,7 @@ let addrMode = PostInc; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; @@ -20667,7 +21113,7 @@ def S2_storerhnew_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Nt8), "memh($Rs32) = $Nt8.new", -tc_6c576d46, TypeMAPPING> { +tc_f7dd9c9f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 1; @@ -20676,13 +21122,14 @@ def S2_storerhnewgp : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Nt8), "memh(gp+#$Ii) = $Nt8.new", -tc_9e86015f, TypeV2LDST>, Enc_bc03e5, AddrModeRel { +tc_ff9ee76e, TypeV2LDST>, Enc_bc03e5, AddrModeRel { let Inst{12-11} = 0b01; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let Uses = [GP]; let BaseOpcode = "S2_storerhabs"; @@ -20697,7 +21144,7 @@ def S2_storeri_io : HInst< (outs), (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) = $Rt32", -tc_53ee6546, TypeST>, Enc_143445, AddrModeRel { +tc_05b6c987, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; @@ -20718,7 +21165,7 @@ def S2_storeri_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++$Mu2:brev) = $Rt32", -tc_20a8e109, TypeST>, Enc_d5c73f, AddrModeRel { +tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111100; let accessSize = WordAccess; @@ -20731,7 +21178,7 @@ def S2_storeri_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++#$Ii:circ($Mu2)) = $Rt32", -tc_251c87b2, TypeST>, Enc_79b8c8 { +tc_9fdb5406, TypeST>, Enc_79b8c8, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001100; @@ -20739,6 +21186,7 @@ let addrMode = PostInc; let accessSize = WordAccess; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storeri_pci"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20746,13 +21194,14 @@ def S2_storeri_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++I:circ($Mu2)) = $Rt32", -tc_20a8e109, TypeST>, Enc_d5c73f { +tc_f86c328a, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001100; let addrMode = PostInc; let accessSize = WordAccess; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storeri_pcr"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20760,7 +21209,7 @@ def S2_storeri_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "memw($Rx32++#$Ii) = $Rt32", -tc_20a8e109, TypeST>, Enc_db40cd, AddrModeRel { +tc_f86c328a, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -20768,6 +21217,7 @@ let Inst{31-21} = 0b10101011100; let addrMode = PostInc; let accessSize = WordAccess; let mayStore = 1; +let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; let isPredicable = 1; let isNVStorable = 1; @@ -20777,7 +21227,7 @@ def S2_storeri_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++$Mu2) = $Rt32", -tc_20a8e109, TypeST>, Enc_d5c73f { +tc_f86c328a, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101100; let addrMode = PostInc; @@ -20790,7 +21240,7 @@ def S2_storeri_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) = $Rt32", -tc_53ee6546, TypeMAPPING> { +tc_05b6c987, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20798,7 +21248,7 @@ def S2_storerigp : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Rt32), "memw(gp+#$Ii) = $Rt32", -tc_c14739d5, TypeV2LDST>, Enc_541f26, AddrModeRel { +tc_a788683e, TypeV2LDST>, Enc_541f26, AddrModeRel { let Inst{24-21} = 0b0100; let Inst{31-27} = 0b01001; let accessSize = WordAccess; @@ -20816,7 +21266,7 @@ def S2_storerinew_io : HInst< (outs), (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8), "memw($Rs32+#$Ii) = $Nt8.new", -tc_6c576d46, TypeST>, Enc_690862, AddrModeRel { +tc_f7dd9c9f, TypeST>, Enc_690862, AddrModeRel { let Inst{12-11} = 0b10; let Inst{24-21} = 0b1101; let Inst{31-27} = 0b10100; @@ -20824,6 +21274,7 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let InputType = "imm"; @@ -20840,13 +21291,14 @@ def S2_storerinew_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++$Mu2:brev) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_8dbe85, AddrModeRel { +tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101111101; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let BaseOpcode = "S2_storeri_pbr"; let opNewValue = 3; @@ -20856,7 +21308,7 @@ def S2_storerinew_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", -tc_9c68db63, TypeST>, Enc_3f97c8 { +tc_9d5941c7, TypeST>, Enc_3f97c8, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{12-11} = 0b10; @@ -20865,8 +21317,10 @@ let addrMode = PostInc; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storeri_pci"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20874,7 +21328,7 @@ def S2_storerinew_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++I:circ($Mu2)) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_8dbe85 { +tc_e7d02c66, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101001101; @@ -20882,8 +21336,10 @@ let addrMode = PostInc; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let Uses = [CS]; +let BaseOpcode = "S2_storeri_pcr"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } @@ -20891,7 +21347,7 @@ def S2_storerinew_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "memw($Rx32++#$Ii) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_223005, AddrModeRel { +tc_e7d02c66, TypeST>, Enc_223005, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-11} = 0b010; @@ -20900,6 +21356,7 @@ let addrMode = PostInc; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let BaseOpcode = "S2_storeri_pi"; let isPredicable = 1; @@ -20910,7 +21367,7 @@ def S2_storerinew_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++$Mu2) = $Nt8.new", -tc_c8f9a6f6, TypeST>, Enc_8dbe85 { +tc_e7d02c66, TypeST>, Enc_8dbe85 { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101101101; @@ -20918,6 +21375,7 @@ let addrMode = PostInc; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; @@ -20926,7 +21384,7 @@ def S2_storerinew_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Nt8), "memw($Rs32) = $Nt8.new", -tc_6c576d46, TypeMAPPING> { +tc_f7dd9c9f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 1; @@ -20935,13 +21393,14 @@ def S2_storerinewgp : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Nt8), "memw(gp+#$Ii) = $Nt8.new", -tc_9e86015f, TypeV2LDST>, Enc_78cbf0, AddrModeRel { +tc_ff9ee76e, TypeV2LDST>, Enc_78cbf0, AddrModeRel { let Inst{12-11} = 0b10; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let Uses = [GP]; let BaseOpcode = "S2_storeriabs"; @@ -20956,7 +21415,7 @@ def S2_storew_locked : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw_locked($Rs32,$Pd4) = $Rt32", -tc_7d01cbdc, TypeST>, Enc_c2b48e { +tc_1372bca1, TypeST>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100000101; @@ -20969,7 +21428,7 @@ def S2_svsathb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = vsathb($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_5e2823 { +tc_cde8b071, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -20980,7 +21439,7 @@ def S2_svsathub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = vsathub($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_5e2823 { +tc_cde8b071, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -20991,7 +21450,7 @@ def S2_tableidxb : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw", -tc_d95f4e98, TypeS_2op>, Enc_cd82bc { +tc_87735c3b, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011100; let hasNewValue = 1; let opNewValue = 0; @@ -21002,7 +21461,7 @@ def S2_tableidxb_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxb($Rs32,#$Ii,#$II)", -tc_d95f4e98, TypeS_2op> { +tc_87735c3b, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21013,7 +21472,7 @@ def S2_tableidxd : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw", -tc_d95f4e98, TypeS_2op>, Enc_cd82bc { +tc_87735c3b, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011111; let hasNewValue = 1; let opNewValue = 0; @@ -21024,7 +21483,7 @@ def S2_tableidxd_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxd($Rs32,#$Ii,#$II)", -tc_d95f4e98, TypeS_2op> { +tc_87735c3b, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21034,7 +21493,7 @@ def S2_tableidxh : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw", -tc_d95f4e98, TypeS_2op>, Enc_cd82bc { +tc_87735c3b, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011101; let hasNewValue = 1; let opNewValue = 0; @@ -21045,7 +21504,7 @@ def S2_tableidxh_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxh($Rs32,#$Ii,#$II)", -tc_d95f4e98, TypeS_2op> { +tc_87735c3b, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21055,7 +21514,7 @@ def S2_tableidxw : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw", -tc_d95f4e98, TypeS_2op>, Enc_cd82bc { +tc_87735c3b, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011110; let hasNewValue = 1; let opNewValue = 0; @@ -21066,7 +21525,7 @@ def S2_tableidxw_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxw($Rs32,#$Ii,#$II)", -tc_d95f4e98, TypeS_2op> { +tc_87735c3b, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21076,7 +21535,7 @@ def S2_togglebit_i : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = togglebit($Rs32,#$Ii)", -tc_9c18c9a5, TypeS_2op>, Enc_a05677 { +tc_540fdfbc, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100110; @@ -21087,7 +21546,7 @@ def S2_togglebit_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = togglebit($Rs32,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_5ab2be { +tc_540fdfbc, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -21098,7 +21557,7 @@ def S2_tstbit_i : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Pd4 = tstbit($Rs32,#$Ii)", -tc_5fa2857c, TypeS_2op>, Enc_83ee64 { +tc_7a830544, TypeS_2op>, Enc_83ee64 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000101000; @@ -21107,7 +21566,7 @@ def S2_tstbit_r : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = tstbit($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e { +tc_1e856f58, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111000; @@ -21116,7 +21575,7 @@ def S2_valignib : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii), "$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)", -tc_d1b5a4b6, TypeS_3op>, Enc_729ff7 { +tc_f8eeed7a, TypeS_3op>, Enc_729ff7 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000000000; } @@ -21124,7 +21583,7 @@ def S2_valignrb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4), "$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)", -tc_d1b5a4b6, TypeS_3op>, Enc_8c6530 { +tc_f8eeed7a, TypeS_3op>, Enc_8c6530 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010000; @@ -21133,7 +21592,7 @@ def S2_vcnegh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vcnegh($Rss32,$Rt32)", -tc_47ab9233, TypeS_3op>, Enc_927852 { +tc_b44c6e2a, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011110; @@ -21144,7 +21603,7 @@ def S2_vcrotate : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vcrotate($Rss32,$Rt32)", -tc_63cd9d2d, TypeS_3op>, Enc_927852 { +tc_2b6f77c6, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011110; @@ -21155,7 +21614,7 @@ def S2_vrcnegh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += vrcnegh($Rss32,$Rt32)", -tc_8cb685d9, TypeS_3op>, Enc_1aa186 { +tc_e913dc32, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -21166,7 +21625,7 @@ def S2_vrndpackwh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vrndwh($Rss32)", -tc_88fa2da6, TypeS_2op>, Enc_90cd8b { +tc_d088982c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21177,7 +21636,7 @@ def S2_vrndpackwhs : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vrndwh($Rss32):sat", -tc_94e6ffd9, TypeS_2op>, Enc_90cd8b { +tc_c2f7d806, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21189,7 +21648,7 @@ def S2_vsathb : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsathb($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_90cd8b { +tc_cde8b071, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21200,7 +21659,7 @@ def S2_vsathb_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsathb($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb { +tc_cde8b071, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21209,7 +21668,7 @@ def S2_vsathub : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsathub($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_90cd8b { +tc_cde8b071, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21220,7 +21679,7 @@ def S2_vsathub_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsathub($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb { +tc_cde8b071, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21229,7 +21688,7 @@ def S2_vsatwh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsatwh($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_90cd8b { +tc_cde8b071, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21240,7 +21699,7 @@ def S2_vsatwh_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsatwh($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb { +tc_cde8b071, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21249,7 +21708,7 @@ def S2_vsatwuh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsatwuh($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_90cd8b { +tc_cde8b071, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21260,7 +21719,7 @@ def S2_vsatwuh_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsatwuh($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_b9c5fb { +tc_cde8b071, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21269,7 +21728,7 @@ def S2_vsplatrb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = vsplatb($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_5e2823 { +tc_cde8b071, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -21281,7 +21740,7 @@ def S2_vsplatrh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsplath($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 { +tc_cde8b071, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100010; let isReMaterializable = 1; @@ -21291,7 +21750,7 @@ def S2_vspliceib : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii), "$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)", -tc_d1b5a4b6, TypeS_3op>, Enc_d50cd3 { +tc_f8eeed7a, TypeS_3op>, Enc_d50cd3 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000000100; } @@ -21299,7 +21758,7 @@ def S2_vsplicerb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4), "$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)", -tc_d1b5a4b6, TypeS_3op>, Enc_dbd70c { +tc_f8eeed7a, TypeS_3op>, Enc_dbd70c { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010100; @@ -21308,7 +21767,7 @@ def S2_vsxtbh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsxtbh($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 { +tc_cde8b071, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -21318,7 +21777,7 @@ def S2_vsxthw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsxthw($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 { +tc_cde8b071, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -21328,7 +21787,7 @@ def S2_vtrunehb : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vtrunehb($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_90cd8b { +tc_cde8b071, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21338,7 +21797,7 @@ def S2_vtrunewh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunewh($Rss32,$Rtt32)", -tc_9c18c9a5, TypeS_3op>, Enc_a56825 { +tc_540fdfbc, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -21347,7 +21806,7 @@ def S2_vtrunohb : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vtrunohb($Rss32)", -tc_b86c7e8b, TypeS_2op>, Enc_90cd8b { +tc_cde8b071, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21357,7 +21816,7 @@ def S2_vtrunowh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunowh($Rss32,$Rtt32)", -tc_9c18c9a5, TypeS_3op>, Enc_a56825 { +tc_540fdfbc, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -21366,7 +21825,7 @@ def S2_vzxtbh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vzxtbh($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 { +tc_cde8b071, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -21376,7 +21835,7 @@ def S2_vzxthw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vzxthw($Rs32)", -tc_b86c7e8b, TypeS_2op>, Enc_3a3d62 { +tc_cde8b071, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -21386,7 +21845,7 @@ def S4_addaddi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii), "$Rd32 = add($Rs32,add($Ru32,#$Ii))", -tc_090485bb, TypeALU64>, Enc_8b8d61 { +tc_c74f796f, TypeALU64>, Enc_8b8d61 { let Inst{31-23} = 0b110110110; let hasNewValue = 1; let opNewValue = 0; @@ -21401,7 +21860,7 @@ def S4_addi_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = add(#$Ii,asl($Rx32in,#$II))", -tc_c0cd91a8, TypeALU64>, Enc_c31910 { +tc_c74f796f, TypeALU64>, Enc_c31910 { let Inst{2-0} = 0b100; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -21419,7 +21878,7 @@ def S4_addi_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = add(#$Ii,lsr($Rx32in,#$II))", -tc_c0cd91a8, TypeALU64>, Enc_c31910 { +tc_c74f796f, TypeALU64>, Enc_c31910 { let Inst{2-0} = 0b100; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -21437,7 +21896,7 @@ def S4_andi_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = and(#$Ii,asl($Rx32in,#$II))", -tc_3c10f809, TypeALU64>, Enc_c31910 { +tc_84df2cd3, TypeALU64>, Enc_c31910 { let Inst{2-0} = 0b000; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -21455,7 +21914,7 @@ def S4_andi_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = and(#$Ii,lsr($Rx32in,#$II))", -tc_3c10f809, TypeALU64>, Enc_c31910 { +tc_84df2cd3, TypeALU64>, Enc_c31910 { let Inst{2-0} = 0b000; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -21473,7 +21932,7 @@ def S4_clbaddi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s6_0Imm:$Ii), "$Rd32 = add(clb($Rs32),#$Ii)", -tc_87601822, TypeS_2op>, Enc_9fae8a { +tc_2b6f77c6, TypeS_2op>, Enc_9fae8a { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10001100001; let hasNewValue = 1; @@ -21484,7 +21943,7 @@ def S4_clbpaddi : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, s6_0Imm:$Ii), "$Rd32 = add(clb($Rss32),#$Ii)", -tc_87601822, TypeS_2op>, Enc_a1640c { +tc_2b6f77c6, TypeS_2op>, Enc_a1640c { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -21495,7 +21954,7 @@ def S4_clbpnorm : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = normamt($Rss32)", -tc_ab1b5e74, TypeS_2op>, Enc_90cd8b { +tc_d088982c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -21506,7 +21965,7 @@ def S4_extract : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), "$Rd32 = extract($Rs32,#$Ii,#$II)", -tc_c0cd91a8, TypeS_2op>, Enc_b388cf { +tc_c74f796f, TypeS_2op>, Enc_b388cf { let Inst{13-13} = 0b0; let Inst{31-23} = 0b100011011; let hasNewValue = 1; @@ -21517,7 +21976,7 @@ def S4_extract_rp : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rd32 = extract($Rs32,$Rtt32)", -tc_87601822, TypeS_3op>, Enc_e07374 { +tc_2b6f77c6, TypeS_3op>, Enc_e07374 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001001000; @@ -21529,7 +21988,7 @@ def S4_extractp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), "$Rdd32 = extract($Rss32,#$Ii,#$II)", -tc_c0cd91a8, TypeS_2op>, Enc_b84c4c { +tc_c74f796f, TypeS_2op>, Enc_b84c4c { let Inst{31-24} = 0b10001010; let prefersSlot3 = 1; } @@ -21537,7 +21996,7 @@ def S4_extractp_rp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = extract($Rss32,$Rtt32)", -tc_87601822, TypeS_3op>, Enc_a56825 { +tc_2b6f77c6, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -21547,7 +22006,7 @@ def S4_lsli : HInst< (outs IntRegs:$Rd32), (ins s6_0Imm:$Ii, IntRegs:$Rt32), "$Rd32 = lsl(#$Ii,$Rt32)", -tc_9c18c9a5, TypeS_3op>, Enc_fef969 { +tc_540fdfbc, TypeS_3op>, Enc_fef969 { let Inst{7-6} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -21558,7 +22017,7 @@ def S4_ntstbit_i : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Pd4 = !tstbit($Rs32,#$Ii)", -tc_5fa2857c, TypeS_2op>, Enc_83ee64 { +tc_7a830544, TypeS_2op>, Enc_83ee64 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000101001; @@ -21567,7 +22026,7 @@ def S4_ntstbit_r : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !tstbit($Rs32,$Rt32)", -tc_c58f771a, TypeS_3op>, Enc_c2b48e { +tc_1e856f58, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111001; @@ -21576,7 +22035,7 @@ def S4_or_andi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 |= and($Rs32,#$Ii)", -tc_3c10f809, TypeALU64>, Enc_b0e9d8 { +tc_84df2cd3, TypeALU64>, Enc_b0e9d8 { let Inst{31-22} = 0b1101101000; let hasNewValue = 1; let opNewValue = 0; @@ -21593,7 +22052,7 @@ def S4_or_andix : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii), "$Rx32 = or($Ru32,and($Rx32in,#$Ii))", -tc_3c10f809, TypeALU64>, Enc_b4e6cf { +tc_84df2cd3, TypeALU64>, Enc_b4e6cf { let Inst{31-22} = 0b1101101001; let hasNewValue = 1; let opNewValue = 0; @@ -21609,7 +22068,7 @@ def S4_or_ori : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 |= or($Rs32,#$Ii)", -tc_3c10f809, TypeALU64>, Enc_b0e9d8 { +tc_84df2cd3, TypeALU64>, Enc_b0e9d8 { let Inst{31-22} = 0b1101101010; let hasNewValue = 1; let opNewValue = 0; @@ -21626,7 +22085,7 @@ def S4_ori_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = or(#$Ii,asl($Rx32in,#$II))", -tc_3c10f809, TypeALU64>, Enc_c31910 { +tc_84df2cd3, TypeALU64>, Enc_c31910 { let Inst{2-0} = 0b010; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -21644,7 +22103,7 @@ def S4_ori_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = or(#$Ii,lsr($Rx32in,#$II))", -tc_3c10f809, TypeALU64>, Enc_c31910 { +tc_84df2cd3, TypeALU64>, Enc_c31910 { let Inst{2-0} = 0b010; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -21662,7 +22121,7 @@ def S4_parity : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = parity($Rs32,$Rt32)", -tc_87601822, TypeALU64>, Enc_5ab2be { +tc_2b6f77c6, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101111; @@ -21674,7 +22133,7 @@ def S4_pstorerbf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb(#$Ii) = $Rt32", -tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -21699,7 +22158,7 @@ def S4_pstorerbf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel { +tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101000; let isPredicated = 1; let isPredicatedFalse = 1; @@ -21715,7 +22174,7 @@ def S4_pstorerbfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb(#$Ii) = $Rt32", -tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -21741,7 +22200,7 @@ def S4_pstorerbfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32", -tc_20a8e109, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_f86c328a, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110000; let isPredicated = 1; @@ -21764,7 +22223,7 @@ def S4_pstorerbfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel { +tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111000; let isPredicated = 1; let isPredicatedFalse = 1; @@ -21781,7 +22240,7 @@ def S4_pstorerbfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rs32) = $Rt32", -tc_20a8e109, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -21789,7 +22248,7 @@ def S4_pstorerbnewf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb(#$Ii) = $Nt8.new", -tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel { +tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b000; @@ -21801,6 +22260,7 @@ let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; @@ -21816,7 +22276,7 @@ def S4_pstorerbnewf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel { +tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110101101; let isPredicated = 1; @@ -21825,6 +22285,7 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let InputType = "reg"; @@ -21835,7 +22296,7 @@ def S4_pstorerbnewfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb(#$Ii) = $Nt8.new", -tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel { +tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -21848,6 +22309,7 @@ let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; @@ -21863,7 +22325,7 @@ def S4_pstorerbnewfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", -tc_c8f9a6f6, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_e7d02c66, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000110101; @@ -21874,6 +22336,7 @@ let accessSize = ByteAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let InputType = "imm"; @@ -21889,7 +22352,7 @@ def S4_pstorerbnewfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel { +tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110111101; let isPredicated = 1; @@ -21899,6 +22362,7 @@ let accessSize = ByteAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let InputType = "reg"; @@ -21909,7 +22373,7 @@ def S4_pstorerbnewfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rs32) = $Nt8.new", -tc_c8f9a6f6, TypeMAPPING> { +tc_e7d02c66, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -21918,7 +22382,7 @@ def S4_pstorerbnewt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb(#$Ii) = $Nt8.new", -tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel { +tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b000; @@ -21929,6 +22393,7 @@ let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; @@ -21944,7 +22409,7 @@ def S4_pstorerbnewt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel { +tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110100101; let isPredicated = 1; @@ -21952,6 +22417,7 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let InputType = "reg"; @@ -21962,7 +22428,7 @@ def S4_pstorerbnewtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb(#$Ii) = $Nt8.new", -tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel { +tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -21974,6 +22440,7 @@ let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; @@ -21989,7 +22456,7 @@ def S4_pstorerbnewtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", -tc_c8f9a6f6, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_e7d02c66, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000010101; @@ -21999,6 +22466,7 @@ let accessSize = ByteAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let InputType = "imm"; @@ -22014,7 +22482,7 @@ def S4_pstorerbnewtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel { +tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110110101; let isPredicated = 1; @@ -22023,6 +22491,7 @@ let accessSize = ByteAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let InputType = "reg"; @@ -22033,7 +22502,7 @@ def S4_pstorerbnewtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4.new) memb($Rs32) = $Nt8.new", -tc_c8f9a6f6, TypeMAPPING> { +tc_e7d02c66, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -22042,7 +22511,7 @@ def S4_pstorerbt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb(#$Ii) = $Rt32", -tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22066,7 +22535,7 @@ def S4_pstorerbt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel { +tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100000; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -22081,7 +22550,7 @@ def S4_pstorerbtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb(#$Ii) = $Rt32", -tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22106,7 +22575,7 @@ def S4_pstorerbtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32", -tc_20a8e109, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_f86c328a, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010000; let isPredicated = 1; @@ -22128,7 +22597,7 @@ def S4_pstorerbtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel { +tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110000; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -22144,7 +22613,7 @@ def S4_pstorerbtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memb($Rs32) = $Rt32", -tc_20a8e109, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22152,7 +22621,7 @@ def S4_pstorerdf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd(#$Ii) = $Rtt32", -tc_c85212ca, TypeST>, Enc_50b5ac, AddrModeRel { +tc_238d91d2, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22176,7 +22645,7 @@ def S4_pstorerdf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_7bc567a7, TypeST>, Enc_1a9974, AddrModeRel { +tc_5274e61a, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110101110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -22191,7 +22660,7 @@ def S4_pstorerdfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd(#$Ii) = $Rtt32", -tc_336e698c, TypeST>, Enc_50b5ac, AddrModeRel { +tc_66888ded, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22216,7 +22685,7 @@ def S4_pstorerdfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32", -tc_20a8e109, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_f86c328a, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110110; let isPredicated = 1; @@ -22238,7 +22707,7 @@ def S4_pstorerdfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_7639d4b0, TypeST>, Enc_1a9974, AddrModeRel { +tc_3e07fb90, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110111110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -22254,7 +22723,7 @@ def S4_pstorerdfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rs32) = $Rtt32", -tc_20a8e109, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22262,7 +22731,7 @@ def S4_pstorerdt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd(#$Ii) = $Rtt32", -tc_c85212ca, TypeST>, Enc_50b5ac, AddrModeRel { +tc_238d91d2, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22285,7 +22754,7 @@ def S4_pstorerdt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_7bc567a7, TypeST>, Enc_1a9974, AddrModeRel { +tc_5274e61a, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110100110; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -22299,7 +22768,7 @@ def S4_pstorerdtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd(#$Ii) = $Rtt32", -tc_336e698c, TypeST>, Enc_50b5ac, AddrModeRel { +tc_66888ded, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22323,7 +22792,7 @@ def S4_pstorerdtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32", -tc_20a8e109, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_f86c328a, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010110; let isPredicated = 1; @@ -22344,7 +22813,7 @@ def S4_pstorerdtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_7639d4b0, TypeST>, Enc_1a9974, AddrModeRel { +tc_3e07fb90, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110110110; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -22359,7 +22828,7 @@ def S4_pstorerdtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rs32) = $Rtt32", -tc_20a8e109, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22367,7 +22836,7 @@ def S4_pstorerff_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh(#$Ii) = $Rt32.h", -tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22391,7 +22860,7 @@ def S4_pstorerff_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel { +tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101011; let isPredicated = 1; let isPredicatedFalse = 1; @@ -22406,7 +22875,7 @@ def S4_pstorerffnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh(#$Ii) = $Rt32.h", -tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22431,7 +22900,7 @@ def S4_pstorerffnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", -tc_20a8e109, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110011; let isPredicated = 1; @@ -22453,7 +22922,7 @@ def S4_pstorerffnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel { +tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111011; let isPredicated = 1; let isPredicatedFalse = 1; @@ -22469,7 +22938,7 @@ def S4_pstorerffnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32) = $Rt32.h", -tc_20a8e109, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22477,7 +22946,7 @@ def S4_pstorerft_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh(#$Ii) = $Rt32.h", -tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22500,7 +22969,7 @@ def S4_pstorerft_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel { +tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100011; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -22514,7 +22983,7 @@ def S4_pstorerftnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh(#$Ii) = $Rt32.h", -tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22538,7 +23007,7 @@ def S4_pstorerftnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", -tc_20a8e109, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010011; let isPredicated = 1; @@ -22559,7 +23028,7 @@ def S4_pstorerftnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel { +tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110011; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -22574,7 +23043,7 @@ def S4_pstorerftnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32) = $Rt32.h", -tc_20a8e109, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22582,7 +23051,7 @@ def S4_pstorerhf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh(#$Ii) = $Rt32", -tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22607,7 +23076,7 @@ def S4_pstorerhf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel { +tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101010; let isPredicated = 1; let isPredicatedFalse = 1; @@ -22623,7 +23092,7 @@ def S4_pstorerhfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh(#$Ii) = $Rt32", -tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22649,7 +23118,7 @@ def S4_pstorerhfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32", -tc_20a8e109, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110010; let isPredicated = 1; @@ -22672,7 +23141,7 @@ def S4_pstorerhfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel { +tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111010; let isPredicated = 1; let isPredicatedFalse = 1; @@ -22689,7 +23158,7 @@ def S4_pstorerhfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32) = $Rt32", -tc_20a8e109, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22697,7 +23166,7 @@ def S4_pstorerhnewf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh(#$Ii) = $Nt8.new", -tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel { +tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b001; @@ -22709,6 +23178,7 @@ let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; @@ -22724,7 +23194,7 @@ def S4_pstorerhnewf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel { +tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110101101; let isPredicated = 1; @@ -22733,6 +23203,7 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let InputType = "reg"; @@ -22743,7 +23214,7 @@ def S4_pstorerhnewfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh(#$Ii) = $Nt8.new", -tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel { +tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -22756,6 +23227,7 @@ let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; @@ -22771,7 +23243,7 @@ def S4_pstorerhnewfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", -tc_c8f9a6f6, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_e7d02c66, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000110101; @@ -22782,6 +23254,7 @@ let accessSize = HalfWordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let InputType = "imm"; @@ -22797,7 +23270,7 @@ def S4_pstorerhnewfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel { +tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110111101; let isPredicated = 1; @@ -22807,6 +23280,7 @@ let accessSize = HalfWordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let InputType = "reg"; @@ -22817,7 +23291,7 @@ def S4_pstorerhnewfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rs32) = $Nt8.new", -tc_c8f9a6f6, TypeMAPPING> { +tc_e7d02c66, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -22826,7 +23300,7 @@ def S4_pstorerhnewt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh(#$Ii) = $Nt8.new", -tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel { +tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b001; @@ -22837,6 +23311,7 @@ let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; @@ -22852,7 +23327,7 @@ def S4_pstorerhnewt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel { +tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110100101; let isPredicated = 1; @@ -22860,6 +23335,7 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let InputType = "reg"; @@ -22870,7 +23346,7 @@ def S4_pstorerhnewtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh(#$Ii) = $Nt8.new", -tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel { +tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -22882,6 +23358,7 @@ let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; @@ -22897,7 +23374,7 @@ def S4_pstorerhnewtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", -tc_c8f9a6f6, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_e7d02c66, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000010101; @@ -22907,6 +23384,7 @@ let accessSize = HalfWordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let InputType = "imm"; @@ -22922,7 +23400,7 @@ def S4_pstorerhnewtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel { +tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110110101; let isPredicated = 1; @@ -22931,6 +23409,7 @@ let accessSize = HalfWordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let InputType = "reg"; @@ -22941,7 +23420,7 @@ def S4_pstorerhnewtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4.new) memh($Rs32) = $Nt8.new", -tc_c8f9a6f6, TypeMAPPING> { +tc_e7d02c66, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -22950,7 +23429,7 @@ def S4_pstorerht_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh(#$Ii) = $Rt32", -tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22974,7 +23453,7 @@ def S4_pstorerht_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel { +tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100010; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -22989,7 +23468,7 @@ def S4_pstorerhtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh(#$Ii) = $Rt32", -tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23014,7 +23493,7 @@ def S4_pstorerhtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32", -tc_20a8e109, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_f86c328a, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010010; let isPredicated = 1; @@ -23036,7 +23515,7 @@ def S4_pstorerhtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel { +tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110010; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -23052,7 +23531,7 @@ def S4_pstorerhtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32) = $Rt32", -tc_20a8e109, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23060,7 +23539,7 @@ def S4_pstorerif_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw(#$Ii) = $Rt32", -tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23085,7 +23564,7 @@ def S4_pstorerif_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel { +tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23101,7 +23580,7 @@ def S4_pstorerifnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw(#$Ii) = $Rt32", -tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23127,7 +23606,7 @@ def S4_pstorerifnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32", -tc_20a8e109, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_f86c328a, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110100; let isPredicated = 1; @@ -23150,7 +23629,7 @@ def S4_pstorerifnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel { +tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23167,7 +23646,7 @@ def S4_pstorerifnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rs32) = $Rt32", -tc_20a8e109, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23175,7 +23654,7 @@ def S4_pstorerinewf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw(#$Ii) = $Nt8.new", -tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel { +tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b010; @@ -23187,6 +23666,7 @@ let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; @@ -23202,7 +23682,7 @@ def S4_pstorerinewf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel { +tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110101101; let isPredicated = 1; @@ -23211,6 +23691,7 @@ let addrMode = BaseRegOffset; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let InputType = "reg"; @@ -23221,7 +23702,7 @@ def S4_pstorerinewfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw(#$Ii) = $Nt8.new", -tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel { +tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -23234,6 +23715,7 @@ let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; @@ -23249,7 +23731,7 @@ def S4_pstorerinewfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", -tc_c8f9a6f6, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_e7d02c66, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000110101; @@ -23260,6 +23742,7 @@ let accessSize = WordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let InputType = "imm"; @@ -23275,7 +23758,7 @@ def S4_pstorerinewfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel { +tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110111101; let isPredicated = 1; @@ -23285,6 +23768,7 @@ let accessSize = WordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let InputType = "reg"; @@ -23295,7 +23779,7 @@ def S4_pstorerinewfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rs32) = $Nt8.new", -tc_c8f9a6f6, TypeMAPPING> { +tc_e7d02c66, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -23304,7 +23788,7 @@ def S4_pstorerinewt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw(#$Ii) = $Nt8.new", -tc_2c8fe5ae, TypeST>, Enc_44215c, AddrModeRel { +tc_6ac37025, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b010; @@ -23315,6 +23799,7 @@ let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; @@ -23330,7 +23815,7 @@ def S4_pstorerinewt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_77781686, TypeST>, Enc_47ee5e, AddrModeRel { +tc_adb14c66, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110100101; let isPredicated = 1; @@ -23338,6 +23823,7 @@ let addrMode = BaseRegOffset; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let InputType = "reg"; @@ -23348,7 +23834,7 @@ def S4_pstorerinewtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw(#$Ii) = $Nt8.new", -tc_7986ba30, TypeST>, Enc_44215c, AddrModeRel { +tc_53bdb2f6, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -23360,6 +23846,7 @@ let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; @@ -23375,7 +23862,7 @@ def S4_pstorerinewtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", -tc_c8f9a6f6, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_e7d02c66, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000010101; @@ -23385,6 +23872,7 @@ let accessSize = WordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let InputType = "imm"; @@ -23400,7 +23888,7 @@ def S4_pstorerinewtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_8def9c57, TypeST>, Enc_47ee5e, AddrModeRel { +tc_e421e012, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110110101; let isPredicated = 1; @@ -23409,6 +23897,7 @@ let accessSize = WordAccess; let isNVStore = 1; let isPredicatedNew = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let InputType = "reg"; @@ -23419,7 +23908,7 @@ def S4_pstorerinewtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4.new) memw($Rs32) = $Nt8.new", -tc_c8f9a6f6, TypeMAPPING> { +tc_e7d02c66, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -23428,7 +23917,7 @@ def S4_pstorerit_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw(#$Ii) = $Rt32", -tc_c85212ca, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_238d91d2, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23452,7 +23941,7 @@ def S4_pstorerit_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7bc567a7, TypeST>, Enc_6339d5, AddrModeRel { +tc_5274e61a, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100100; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -23467,7 +23956,7 @@ def S4_pstoreritnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw(#$Ii) = $Rt32", -tc_336e698c, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_66888ded, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23492,7 +23981,7 @@ def S4_pstoreritnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32", -tc_20a8e109, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_f86c328a, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010100; let isPredicated = 1; @@ -23514,7 +24003,7 @@ def S4_pstoreritnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_7639d4b0, TypeST>, Enc_6339d5, AddrModeRel { +tc_3e07fb90, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110100; let isPredicated = 1; let addrMode = BaseRegOffset; @@ -23530,7 +24019,7 @@ def S4_pstoreritnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memw($Rs32) = $Rt32", -tc_20a8e109, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23538,7 +24027,7 @@ def S4_stored_locked : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "memd_locked($Rs32,$Pd4) = $Rtt32", -tc_7d01cbdc, TypeST>, Enc_d7dc10 { +tc_1372bca1, TypeST>, Enc_d7dc10 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100000111; @@ -23551,7 +24040,7 @@ def S4_storeirb_io : HInst< (outs), (ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "memb($Rs32+#$Ii) = #$II", -tc_fcee8723, TypeST>, Enc_8203bb, PredNewRel { +tc_05b6c987, TypeST>, Enc_8203bb, PredNewRel { let Inst{31-21} = 0b00111100000; let addrMode = BaseImmOffset; let accessSize = ByteAccess; @@ -23570,7 +24059,7 @@ def S4_storeirb_zomap : HInst< (outs), (ins IntRegs:$Rs32, s8_0Imm:$II), "memb($Rs32) = #$II", -tc_fcee8723, TypeMAPPING> { +tc_05b6c987, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23578,7 +24067,7 @@ def S4_storeirbf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if (!$Pv4) memb($Rs32+#$Ii) = #$II", -tc_1e69aa99, TypeST>, Enc_d7a65e, PredNewRel { +tc_8b15472a, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111000100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23598,7 +24087,7 @@ def S4_storeirbf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4) memb($Rs32) = #$II", -tc_1e69aa99, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23606,7 +24095,7 @@ def S4_storeirbfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if (!$Pv4.new) memb($Rs32+#$Ii) = #$II", -tc_8f0a6bad, TypeST>, Enc_d7a65e, PredNewRel { +tc_f86c328a, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111001100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23627,7 +24116,7 @@ def S4_storeirbfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4.new) memb($Rs32) = #$II", -tc_8f0a6bad, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23635,7 +24124,7 @@ def S4_storeirbt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if ($Pv4) memb($Rs32+#$Ii) = #$II", -tc_1e69aa99, TypeST>, Enc_d7a65e, PredNewRel { +tc_8b15472a, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111000000; let isPredicated = 1; let addrMode = BaseImmOffset; @@ -23654,7 +24143,7 @@ def S4_storeirbt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4) memb($Rs32) = #$II", -tc_1e69aa99, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23662,7 +24151,7 @@ def S4_storeirbtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if ($Pv4.new) memb($Rs32+#$Ii) = #$II", -tc_8f0a6bad, TypeST>, Enc_d7a65e, PredNewRel { +tc_f86c328a, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111001000; let isPredicated = 1; let addrMode = BaseImmOffset; @@ -23682,7 +24171,7 @@ def S4_storeirbtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4.new) memb($Rs32) = #$II", -tc_8f0a6bad, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23690,7 +24179,7 @@ def S4_storeirh_io : HInst< (outs), (ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "memh($Rs32+#$Ii) = #$II", -tc_fcee8723, TypeST>, Enc_a803e0, PredNewRel { +tc_05b6c987, TypeST>, Enc_a803e0, PredNewRel { let Inst{31-21} = 0b00111100001; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; @@ -23709,7 +24198,7 @@ def S4_storeirh_zomap : HInst< (outs), (ins IntRegs:$Rs32, s8_0Imm:$II), "memh($Rs32) = #$II", -tc_fcee8723, TypeMAPPING> { +tc_05b6c987, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23717,7 +24206,7 @@ def S4_storeirhf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if (!$Pv4) memh($Rs32+#$Ii) = #$II", -tc_1e69aa99, TypeST>, Enc_f20719, PredNewRel { +tc_8b15472a, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111000101; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23737,7 +24226,7 @@ def S4_storeirhf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4) memh($Rs32) = #$II", -tc_1e69aa99, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23745,7 +24234,7 @@ def S4_storeirhfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if (!$Pv4.new) memh($Rs32+#$Ii) = #$II", -tc_8f0a6bad, TypeST>, Enc_f20719, PredNewRel { +tc_f86c328a, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111001101; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23766,7 +24255,7 @@ def S4_storeirhfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4.new) memh($Rs32) = #$II", -tc_8f0a6bad, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23774,7 +24263,7 @@ def S4_storeirht_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if ($Pv4) memh($Rs32+#$Ii) = #$II", -tc_1e69aa99, TypeST>, Enc_f20719, PredNewRel { +tc_8b15472a, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111000001; let isPredicated = 1; let addrMode = BaseImmOffset; @@ -23793,7 +24282,7 @@ def S4_storeirht_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4) memh($Rs32) = #$II", -tc_1e69aa99, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23801,7 +24290,7 @@ def S4_storeirhtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if ($Pv4.new) memh($Rs32+#$Ii) = #$II", -tc_8f0a6bad, TypeST>, Enc_f20719, PredNewRel { +tc_f86c328a, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111001001; let isPredicated = 1; let addrMode = BaseImmOffset; @@ -23821,7 +24310,7 @@ def S4_storeirhtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4.new) memh($Rs32) = #$II", -tc_8f0a6bad, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23829,7 +24318,7 @@ def S4_storeiri_io : HInst< (outs), (ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "memw($Rs32+#$Ii) = #$II", -tc_fcee8723, TypeST>, Enc_f37377, PredNewRel { +tc_05b6c987, TypeST>, Enc_f37377, PredNewRel { let Inst{31-21} = 0b00111100010; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -23848,7 +24337,7 @@ def S4_storeiri_zomap : HInst< (outs), (ins IntRegs:$Rs32, s8_0Imm:$II), "memw($Rs32) = #$II", -tc_fcee8723, TypeMAPPING> { +tc_05b6c987, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23856,7 +24345,7 @@ def S4_storeirif_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if (!$Pv4) memw($Rs32+#$Ii) = #$II", -tc_1e69aa99, TypeST>, Enc_5ccba9, PredNewRel { +tc_8b15472a, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111000110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23876,7 +24365,7 @@ def S4_storeirif_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4) memw($Rs32) = #$II", -tc_1e69aa99, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23884,7 +24373,7 @@ def S4_storeirifnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if (!$Pv4.new) memw($Rs32+#$Ii) = #$II", -tc_8f0a6bad, TypeST>, Enc_5ccba9, PredNewRel { +tc_f86c328a, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111001110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23905,7 +24394,7 @@ def S4_storeirifnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4.new) memw($Rs32) = #$II", -tc_8f0a6bad, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23913,7 +24402,7 @@ def S4_storeirit_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if ($Pv4) memw($Rs32+#$Ii) = #$II", -tc_1e69aa99, TypeST>, Enc_5ccba9, PredNewRel { +tc_8b15472a, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111000010; let isPredicated = 1; let addrMode = BaseImmOffset; @@ -23932,7 +24421,7 @@ def S4_storeirit_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4) memw($Rs32) = #$II", -tc_1e69aa99, TypeMAPPING> { +tc_8b15472a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23940,7 +24429,7 @@ def S4_storeiritnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if ($Pv4.new) memw($Rs32+#$Ii) = #$II", -tc_8f0a6bad, TypeST>, Enc_5ccba9, PredNewRel { +tc_f86c328a, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111001010; let isPredicated = 1; let addrMode = BaseImmOffset; @@ -23960,7 +24449,7 @@ def S4_storeiritnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4.new) memw($Rs32) = #$II", -tc_8f0a6bad, TypeMAPPING> { +tc_f86c328a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23968,12 +24457,10 @@ def S4_storerb_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memb($Re32=#$II) = $Rt32", -tc_336e698c, TypeST>, Enc_8bcba4, AddrModeRel { +tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011000; -let hasNewValue = 1; -let opNewValue = 0; let addrMode = AbsoluteSet; let accessSize = ByteAccess; let isExtended = 1; @@ -23991,7 +24478,7 @@ def S4_storerb_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_45631a8d, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011000; let addrMode = BaseRegOffset; @@ -24007,7 +24494,7 @@ def S4_storerb_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memb($Ru32<<#$Ii+#$II) = $Rt32", -tc_a4567c39, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101000; let addrMode = BaseLongOffset; @@ -24029,17 +24516,16 @@ def S4_storerbnew_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Nt8), "memb($Re32=#$II) = $Nt8.new", -tc_7986ba30, TypeST>, Enc_724154, AddrModeRel { +tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-11} = 0b000; let Inst{31-21} = 0b10101011101; -let hasNewValue = 1; -let opNewValue = 0; let addrMode = AbsoluteSet; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let BaseOpcode = "S2_storerb_ap"; let DecoderNamespace = "MustExtend"; @@ -24054,13 +24540,14 @@ def S4_storerbnew_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_be995eaf, TypeST>, Enc_c6220b, AddrModeRel { +tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel { let Inst{6-3} = 0b0000; let Inst{31-21} = 0b00111011101; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let InputType = "reg"; @@ -24072,7 +24559,7 @@ def S4_storerbnew_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), "memb($Ru32<<#$Ii+#$II) = $Nt8.new", -tc_210b2456, TypeST>, Enc_7eb485, AddrModeRel { +tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel { let Inst{7-7} = 0b1; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101101101; @@ -24081,6 +24568,7 @@ let accessSize = ByteAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerb"; let BaseOpcode = "S4_storerb_ur"; @@ -24096,12 +24584,10 @@ def S4_storerd_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, DoubleRegs:$Rtt32), "memd($Re32=#$II) = $Rtt32", -tc_336e698c, TypeST>, Enc_c7a204 { +tc_66888ded, TypeST>, Enc_c7a204 { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011110; -let hasNewValue = 1; -let opNewValue = 0; let addrMode = AbsoluteSet; let accessSize = DoubleWordAccess; let isExtended = 1; @@ -24118,7 +24604,7 @@ def S4_storerd_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_45631a8d, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl { +tc_d9709180, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011110; let addrMode = BaseRegOffset; @@ -24133,7 +24619,7 @@ def S4_storerd_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32), "memd($Ru32<<#$Ii+#$II) = $Rtt32", -tc_a4567c39, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl { +tc_0dc560de, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101110; let addrMode = BaseLongOffset; @@ -24154,12 +24640,10 @@ def S4_storerf_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memh($Re32=#$II) = $Rt32.h", -tc_336e698c, TypeST>, Enc_8bcba4 { +tc_66888ded, TypeST>, Enc_8bcba4 { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011011; -let hasNewValue = 1; -let opNewValue = 0; let addrMode = AbsoluteSet; let accessSize = HalfWordAccess; let isExtended = 1; @@ -24176,7 +24660,7 @@ def S4_storerf_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_45631a8d, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011011; let addrMode = BaseRegOffset; @@ -24191,7 +24675,7 @@ def S4_storerf_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memh($Ru32<<#$Ii+#$II) = $Rt32.h", -tc_a4567c39, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101011; let addrMode = BaseLongOffset; @@ -24212,12 +24696,10 @@ def S4_storerh_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memh($Re32=#$II) = $Rt32", -tc_336e698c, TypeST>, Enc_8bcba4, AddrModeRel { +tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011010; -let hasNewValue = 1; -let opNewValue = 0; let addrMode = AbsoluteSet; let accessSize = HalfWordAccess; let isExtended = 1; @@ -24235,7 +24717,7 @@ def S4_storerh_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_45631a8d, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011010; let addrMode = BaseRegOffset; @@ -24251,7 +24733,7 @@ def S4_storerh_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memh($Ru32<<#$Ii+#$II) = $Rt32", -tc_a4567c39, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101010; let addrMode = BaseLongOffset; @@ -24273,17 +24755,16 @@ def S4_storerhnew_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Nt8), "memh($Re32=#$II) = $Nt8.new", -tc_7986ba30, TypeST>, Enc_724154, AddrModeRel { +tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-11} = 0b001; let Inst{31-21} = 0b10101011101; -let hasNewValue = 1; -let opNewValue = 0; let addrMode = AbsoluteSet; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let BaseOpcode = "S2_storerh_ap"; let DecoderNamespace = "MustExtend"; @@ -24298,13 +24779,14 @@ def S4_storerhnew_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_be995eaf, TypeST>, Enc_c6220b, AddrModeRel { +tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel { let Inst{6-3} = 0b0001; let Inst{31-21} = 0b00111011101; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let InputType = "reg"; @@ -24316,7 +24798,7 @@ def S4_storerhnew_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), "memh($Ru32<<#$Ii+#$II) = $Nt8.new", -tc_210b2456, TypeST>, Enc_7eb485, AddrModeRel { +tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel { let Inst{7-7} = 0b1; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101101101; @@ -24325,6 +24807,7 @@ let accessSize = HalfWordAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_ur"; @@ -24340,12 +24823,10 @@ def S4_storeri_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memw($Re32=#$II) = $Rt32", -tc_336e698c, TypeST>, Enc_8bcba4, AddrModeRel { +tc_66888ded, TypeST>, Enc_8bcba4, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011100; -let hasNewValue = 1; -let opNewValue = 0; let addrMode = AbsoluteSet; let accessSize = WordAccess; let isExtended = 1; @@ -24363,7 +24844,7 @@ def S4_storeri_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_45631a8d, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_d9709180, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011100; let addrMode = BaseRegOffset; @@ -24379,7 +24860,7 @@ def S4_storeri_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memw($Ru32<<#$Ii+#$II) = $Rt32", -tc_a4567c39, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_0dc560de, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101100; let addrMode = BaseLongOffset; @@ -24401,17 +24882,16 @@ def S4_storerinew_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Nt8), "memw($Re32=#$II) = $Nt8.new", -tc_7986ba30, TypeST>, Enc_724154, AddrModeRel { +tc_53bdb2f6, TypeST>, Enc_724154, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-11} = 0b010; let Inst{31-21} = 0b10101011101; -let hasNewValue = 1; -let opNewValue = 0; let addrMode = AbsoluteSet; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let BaseOpcode = "S2_storeri_ap"; let DecoderNamespace = "MustExtend"; @@ -24426,13 +24906,14 @@ def S4_storerinew_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_be995eaf, TypeST>, Enc_c6220b, AddrModeRel { +tc_b166348b, TypeST>, Enc_c6220b, AddrModeRel { let Inst{6-3} = 0b0010; let Inst{31-21} = 0b00111011101; let addrMode = BaseRegOffset; let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let InputType = "reg"; @@ -24444,7 +24925,7 @@ def S4_storerinew_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), "memw($Ru32<<#$Ii+#$II) = $Nt8.new", -tc_210b2456, TypeST>, Enc_7eb485, AddrModeRel { +tc_a8acdac0, TypeST>, Enc_7eb485, AddrModeRel { let Inst{7-7} = 0b1; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101101101; @@ -24453,6 +24934,7 @@ let accessSize = WordAccess; let isNVStore = 1; let isNewValue = 1; let isExtended = 1; +let isRestrictNoSlot1Store = 1; let mayStore = 1; let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_ur"; @@ -24468,7 +24950,7 @@ def S4_subaddi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32), "$Rd32 = add($Rs32,sub(#$Ii,$Ru32))", -tc_090485bb, TypeALU64>, Enc_8b8d61 { +tc_c74f796f, TypeALU64>, Enc_8b8d61 { let Inst{31-23} = 0b110110111; let hasNewValue = 1; let opNewValue = 0; @@ -24483,7 +24965,7 @@ def S4_subi_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = sub(#$Ii,asl($Rx32in,#$II))", -tc_c0cd91a8, TypeALU64>, Enc_c31910 { +tc_c74f796f, TypeALU64>, Enc_c31910 { let Inst{2-0} = 0b110; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -24501,7 +24983,7 @@ def S4_subi_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))", -tc_c0cd91a8, TypeALU64>, Enc_c31910 { +tc_c74f796f, TypeALU64>, Enc_c31910 { let Inst{2-0} = 0b110; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -24519,7 +25001,7 @@ def S4_vrcrotate : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)", -tc_6264c5e0, TypeS_3op>, Enc_645d54 { +tc_b9c0b731, TypeS_3op>, Enc_645d54 { let Inst{7-6} = 0b11; let Inst{31-21} = 0b11000011110; let prefersSlot3 = 1; @@ -24528,7 +25010,7 @@ def S4_vrcrotate_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)", -tc_bc5561d8, TypeS_3op>, Enc_b72622 { +tc_60571023, TypeS_3op>, Enc_b72622 { let Inst{7-6} = 0b00; let Inst{31-21} = 0b11001011101; let prefersSlot3 = 1; @@ -24538,7 +25020,7 @@ def S4_vxaddsubh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat", -tc_47ab9233, TypeS_3op>, Enc_a56825 { +tc_b44c6e2a, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -24549,7 +25031,7 @@ def S4_vxaddsubhr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat", -tc_63cd9d2d, TypeS_3op>, Enc_a56825 { +tc_2b6f77c6, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -24560,7 +25042,7 @@ def S4_vxaddsubw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat", -tc_47ab9233, TypeS_3op>, Enc_a56825 { +tc_b44c6e2a, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -24571,7 +25053,7 @@ def S4_vxsubaddh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat", -tc_47ab9233, TypeS_3op>, Enc_a56825 { +tc_b44c6e2a, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -24582,7 +25064,7 @@ def S4_vxsubaddhr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat", -tc_63cd9d2d, TypeS_3op>, Enc_a56825 { +tc_2b6f77c6, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -24593,7 +25075,7 @@ def S4_vxsubaddw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat", -tc_47ab9233, TypeS_3op>, Enc_a56825 { +tc_b44c6e2a, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -24604,7 +25086,7 @@ def S5_asrhub_rnd_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):raw", -tc_63cd9d2d, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> { let Inst{7-5} = 0b100; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10001000011; @@ -24617,7 +25099,7 @@ def S5_asrhub_rnd_sat_goodsyntax : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat", -tc_63cd9d2d, TypeS_2op>, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -24626,7 +25108,7 @@ def S5_asrhub_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):sat", -tc_63cd9d2d, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5T]> { let Inst{7-5} = 0b101; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10001000011; @@ -24639,7 +25121,7 @@ def S5_popcountp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = popcount($Rss32)", -tc_ca280e8b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { +tc_00afc57e, TypeS_2op>, Enc_90cd8b, Requires<[HasV5T]> { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -24650,7 +25132,7 @@ def S5_vasrhrnd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii):raw", -tc_63cd9d2d, TypeS_2op>, Enc_12b6e9, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Enc_12b6e9, Requires<[HasV5T]> { let Inst{7-5} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000001; @@ -24660,14 +25142,22 @@ def S5_vasrhrnd_goodsyntax : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii):rnd", -tc_63cd9d2d, TypeS_2op>, Requires<[HasV5T]> { +tc_2b6f77c6, TypeS_2op>, Requires<[HasV5T]> { let isPseudo = 1; } +def S6_allocframe_to_raw : HInst< +(outs), +(ins u11_3Imm:$Ii), +"allocframe(#$Ii)", +tc_e216a5db, TypeMAPPING>, Requires<[HasV65T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} def S6_rol_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = rol($Rss32,#$Ii)", -tc_9f518242, TypeS_2op>, Enc_5eac98, Requires<[HasV60T]> { +tc_55050d58, TypeS_2op>, Enc_5eac98, Requires<[HasV60T]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000000000; } @@ -24675,7 +25165,7 @@ def S6_rol_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += rol($Rss32,#$Ii)", -tc_e17ce9ad, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -24685,7 +25175,7 @@ def S6_rol_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= rol($Rss32,#$Ii)", -tc_e17ce9ad, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -24695,7 +25185,7 @@ def S6_rol_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= rol($Rss32,#$Ii)", -tc_e17ce9ad, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -24705,7 +25195,7 @@ def S6_rol_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= rol($Rss32,#$Ii)", -tc_e17ce9ad, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -24715,7 +25205,7 @@ def S6_rol_i_p_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 ^= rol($Rss32,#$Ii)", -tc_e17ce9ad, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_70fb07, Requires<[HasV60T]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010100; let prefersSlot3 = 1; @@ -24725,7 +25215,7 @@ def S6_rol_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = rol($Rs32,#$Ii)", -tc_9f518242, TypeS_2op>, Enc_a05677, Requires<[HasV60T]> { +tc_55050d58, TypeS_2op>, Enc_a05677, Requires<[HasV60T]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -24736,7 +25226,7 @@ def S6_rol_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += rol($Rs32,#$Ii)", -tc_e17ce9ad, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -24749,7 +25239,7 @@ def S6_rol_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= rol($Rs32,#$Ii)", -tc_e17ce9ad, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -24762,7 +25252,7 @@ def S6_rol_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= rol($Rs32,#$Ii)", -tc_e17ce9ad, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -24775,7 +25265,7 @@ def S6_rol_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= rol($Rs32,#$Ii)", -tc_e17ce9ad, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -24788,7 +25278,7 @@ def S6_rol_i_r_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 ^= rol($Rs32,#$Ii)", -tc_e17ce9ad, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { +tc_41d5298e, TypeS_2op>, Enc_28a2dc, Requires<[HasV60T]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110100; @@ -24801,7 +25291,7 @@ def S6_vsplatrbp : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsplatb($Rs32)", -tc_78b3c689, TypeS_2op>, Enc_3a3d62, Requires<[HasV62T]> { +tc_be706f30, TypeS_2op>, Enc_3a3d62, Requires<[HasV62T]> { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100010; } @@ -24809,7 +25299,7 @@ def S6_vtrunehb_ppp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunehb($Rss32,$Rtt32)", -tc_9f518242, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> { +tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -24818,7 +25308,7 @@ def S6_vtrunohb_ppp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunohb($Rss32,$Rtt32)", -tc_9f518242, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> { +tc_55050d58, TypeS_3op>, Enc_a56825, Requires<[HasV62T]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -24827,7 +25317,7 @@ def SA1_addi : HInst< (outs GeneralSubRegs:$Rx16), (ins IntRegs:$Rx16in, s32_0Imm:$Ii), "$Rx16 = add($Rx16in,#$Ii)", -tc_821c4233, TypeSUBINSN>, Enc_93af4c { +tc_609d2efe, TypeSUBINSN>, Enc_93af4c { let Inst{12-11} = 0b00; let hasNewValue = 1; let opNewValue = 0; @@ -24844,7 +25334,7 @@ def SA1_addrx : HInst< (outs GeneralSubRegs:$Rx16), (ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16), "$Rx16 = add($Rx16in,$Rs16)", -tc_821c4233, TypeSUBINSN>, Enc_0527db { +tc_609d2efe, TypeSUBINSN>, Enc_0527db { let Inst{12-8} = 0b11000; let hasNewValue = 1; let opNewValue = 0; @@ -24856,7 +25346,7 @@ def SA1_addsp : HInst< (outs GeneralSubRegs:$Rd16), (ins u6_2Imm:$Ii), "$Rd16 = add(r29,#$Ii)", -tc_d2609065, TypeSUBINSN>, Enc_2df31d { +tc_a904d137, TypeSUBINSN>, Enc_2df31d { let Inst{12-10} = 0b011; let hasNewValue = 1; let opNewValue = 0; @@ -24868,7 +25358,7 @@ def SA1_and1 : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = and($Rs16,#1)", -tc_d2609065, TypeSUBINSN>, Enc_97d666 { +tc_a904d137, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10010; let hasNewValue = 1; let opNewValue = 0; @@ -24879,7 +25369,7 @@ def SA1_clrf : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (!p0) $Rd16 = #0", -tc_7c2dcd4d, TypeSUBINSN>, Enc_1f5ba6 { +tc_1b82a277, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100111; let isPredicated = 1; let isPredicatedFalse = 1; @@ -24893,7 +25383,7 @@ def SA1_clrfnew : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (!p0.new) $Rd16 = #0", -tc_f26aa619, TypeSUBINSN>, Enc_1f5ba6 { +tc_e9c822f7, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100101; let isPredicated = 1; let isPredicatedFalse = 1; @@ -24908,7 +25398,7 @@ def SA1_clrt : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (p0) $Rd16 = #0", -tc_7c2dcd4d, TypeSUBINSN>, Enc_1f5ba6 { +tc_1b82a277, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100110; let isPredicated = 1; let hasNewValue = 1; @@ -24921,7 +25411,7 @@ def SA1_clrtnew : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (p0.new) $Rd16 = #0", -tc_f26aa619, TypeSUBINSN>, Enc_1f5ba6 { +tc_e9c822f7, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100100; let isPredicated = 1; let hasNewValue = 1; @@ -24935,7 +25425,7 @@ def SA1_cmpeqi : HInst< (outs), (ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii), "p0 = cmp.eq($Rs16,#$Ii)", -tc_e8c7a357, TypeSUBINSN>, Enc_63eaeb { +tc_90f3e30c, TypeSUBINSN>, Enc_63eaeb { let Inst{3-2} = 0b00; let Inst{12-8} = 0b11001; let AsmVariantName = "NonParsable"; @@ -24946,7 +25436,7 @@ def SA1_combine0i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#0,#$Ii)", -tc_d2609065, TypeSUBINSN>, Enc_ed48be { +tc_a904d137, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b00; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -24958,7 +25448,7 @@ def SA1_combine1i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#1,#$Ii)", -tc_d2609065, TypeSUBINSN>, Enc_ed48be { +tc_a904d137, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b01; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -24970,7 +25460,7 @@ def SA1_combine2i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#2,#$Ii)", -tc_d2609065, TypeSUBINSN>, Enc_ed48be { +tc_a904d137, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b10; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -24982,7 +25472,7 @@ def SA1_combine3i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#3,#$Ii)", -tc_d2609065, TypeSUBINSN>, Enc_ed48be { +tc_a904d137, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b11; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -24994,7 +25484,7 @@ def SA1_combinerz : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins GeneralSubRegs:$Rs16), "$Rdd8 = combine($Rs16,#0)", -tc_d2609065, TypeSUBINSN>, Enc_399e12 { +tc_a904d137, TypeSUBINSN>, Enc_399e12 { let Inst{3-3} = 0b1; let Inst{12-8} = 0b11101; let hasNewValue = 1; @@ -25006,7 +25496,7 @@ def SA1_combinezr : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins GeneralSubRegs:$Rs16), "$Rdd8 = combine(#0,$Rs16)", -tc_d2609065, TypeSUBINSN>, Enc_399e12 { +tc_a904d137, TypeSUBINSN>, Enc_399e12 { let Inst{3-3} = 0b0; let Inst{12-8} = 0b11101; let hasNewValue = 1; @@ -25018,7 +25508,7 @@ def SA1_dec : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, n1Const:$n1), "$Rd16 = add($Rs16,#$n1)", -tc_821c4233, TypeSUBINSN>, Enc_ee5ed0 { +tc_609d2efe, TypeSUBINSN>, Enc_ee5ed0 { let Inst{12-8} = 0b10011; let hasNewValue = 1; let opNewValue = 0; @@ -25029,7 +25519,7 @@ def SA1_inc : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = add($Rs16,#1)", -tc_d2609065, TypeSUBINSN>, Enc_97d666 { +tc_a904d137, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10001; let hasNewValue = 1; let opNewValue = 0; @@ -25040,7 +25530,7 @@ def SA1_seti : HInst< (outs GeneralSubRegs:$Rd16), (ins u32_0Imm:$Ii), "$Rd16 = #$Ii", -tc_d2609065, TypeSUBINSN>, Enc_e39bb2 { +tc_a904d137, TypeSUBINSN>, Enc_e39bb2 { let Inst{12-10} = 0b010; let hasNewValue = 1; let opNewValue = 0; @@ -25056,7 +25546,7 @@ def SA1_setin1 : HInst< (outs GeneralSubRegs:$Rd16), (ins n1Const:$n1), "$Rd16 = #$n1", -tc_d2609065, TypeSUBINSN>, Enc_7a0ea6 { +tc_a904d137, TypeSUBINSN>, Enc_7a0ea6 { let Inst{12-4} = 0b110100000; let hasNewValue = 1; let opNewValue = 0; @@ -25067,7 +25557,7 @@ def SA1_sxtb : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = sxtb($Rs16)", -tc_d2609065, TypeSUBINSN>, Enc_97d666 { +tc_a904d137, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10101; let hasNewValue = 1; let opNewValue = 0; @@ -25078,7 +25568,7 @@ def SA1_sxth : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = sxth($Rs16)", -tc_d2609065, TypeSUBINSN>, Enc_97d666 { +tc_a904d137, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10100; let hasNewValue = 1; let opNewValue = 0; @@ -25089,7 +25579,7 @@ def SA1_tfr : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = $Rs16", -tc_d2609065, TypeSUBINSN>, Enc_97d666 { +tc_a904d137, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10000; let hasNewValue = 1; let opNewValue = 0; @@ -25100,7 +25590,7 @@ def SA1_zxtb : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = and($Rs16,#255)", -tc_d2609065, TypeSUBINSN>, Enc_97d666 { +tc_a904d137, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10111; let hasNewValue = 1; let opNewValue = 0; @@ -25111,7 +25601,7 @@ def SA1_zxth : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = zxth($Rs16)", -tc_d2609065, TypeSUBINSN>, Enc_97d666 { +tc_a904d137, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10110; let hasNewValue = 1; let opNewValue = 0; @@ -25122,7 +25612,7 @@ def SL1_loadri_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), "$Rd16 = memw($Rs16+#$Ii)", -tc_bf6fa601, TypeSUBINSN>, Enc_53dca9 { +tc_7f881c76, TypeSUBINSN>, Enc_53dca9 { let Inst{12-12} = 0b0; let hasNewValue = 1; let opNewValue = 0; @@ -25136,7 +25626,7 @@ def SL1_loadrub_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), "$Rd16 = memub($Rs16+#$Ii)", -tc_bf6fa601, TypeSUBINSN>, Enc_c175d0 { +tc_7f881c76, TypeSUBINSN>, Enc_c175d0 { let Inst{12-12} = 0b1; let hasNewValue = 1; let opNewValue = 0; @@ -25150,12 +25640,12 @@ def SL2_deallocframe : HInst< (outs), (ins), "deallocframe", -tc_86442910, TypeSUBINSN>, Enc_e3b0c4 { +tc_36c68ad1, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111100000000; let accessSize = DoubleWordAccess; let AsmVariantName = "NonParsable"; let mayLoad = 1; -let Uses = [R30]; +let Uses = [FRAMEKEY, R30]; let Defs = [R30, R29, R31]; let DecoderNamespace = "SUBINSN_L2"; } @@ -25163,12 +25653,12 @@ def SL2_jumpr31 : HInst< (outs), (ins), "jumpr r31", -tc_35fb9d13, TypeSUBINSN>, Enc_e3b0c4 { +tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000000; let isTerminator = 1; let isIndirectBranch = 1; -let cofMax1 = 1; let AsmVariantName = "NonParsable"; +let cofMax1 = 1; let isReturn = 1; let Uses = [R31]; let Defs = [PC]; @@ -25178,14 +25668,14 @@ def SL2_jumpr31_f : HInst< (outs), (ins), "if (!p0) jumpr r31", -tc_35fb9d13, TypeSUBINSN>, Enc_e3b0c4 { +tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000101; let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isIndirectBranch = 1; -let cofMax1 = 1; let AsmVariantName = "NonParsable"; +let cofMax1 = 1; let isReturn = 1; let Uses = [P0, R31]; let Defs = [PC]; @@ -25196,15 +25686,15 @@ def SL2_jumpr31_fnew : HInst< (outs), (ins), "if (!p0.new) jumpr:nt r31", -tc_35fb9d13, TypeSUBINSN>, Enc_e3b0c4 { +tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000111; let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isIndirectBranch = 1; -let cofMax1 = 1; let AsmVariantName = "NonParsable"; let isPredicatedNew = 1; +let cofMax1 = 1; let isReturn = 1; let Uses = [P0, R31]; let Defs = [PC]; @@ -25215,13 +25705,13 @@ def SL2_jumpr31_t : HInst< (outs), (ins), "if (p0) jumpr r31", -tc_35fb9d13, TypeSUBINSN>, Enc_e3b0c4 { +tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000100; let isPredicated = 1; let isTerminator = 1; let isIndirectBranch = 1; -let cofMax1 = 1; let AsmVariantName = "NonParsable"; +let cofMax1 = 1; let isReturn = 1; let Uses = [P0, R31]; let Defs = [PC]; @@ -25232,14 +25722,14 @@ def SL2_jumpr31_tnew : HInst< (outs), (ins), "if (p0.new) jumpr:nt r31", -tc_35fb9d13, TypeSUBINSN>, Enc_e3b0c4 { +tc_2a160009, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000110; let isPredicated = 1; let isTerminator = 1; let isIndirectBranch = 1; -let cofMax1 = 1; let AsmVariantName = "NonParsable"; let isPredicatedNew = 1; +let cofMax1 = 1; let isReturn = 1; let Uses = [P0, R31]; let Defs = [PC]; @@ -25250,7 +25740,7 @@ def SL2_loadrb_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii), "$Rd16 = memb($Rs16+#$Ii)", -tc_bf6fa601, TypeSUBINSN>, Enc_2fbf3c { +tc_7f881c76, TypeSUBINSN>, Enc_2fbf3c { let Inst{12-11} = 0b10; let hasNewValue = 1; let opNewValue = 0; @@ -25264,7 +25754,7 @@ def SL2_loadrd_sp : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u5_3Imm:$Ii), "$Rdd8 = memd(r29+#$Ii)", -tc_70cabf66, TypeSUBINSN>, Enc_86a14b { +tc_9c98e8af, TypeSUBINSN>, Enc_86a14b { let Inst{12-8} = 0b11110; let hasNewValue = 1; let opNewValue = 0; @@ -25279,7 +25769,7 @@ def SL2_loadrh_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), "$Rd16 = memh($Rs16+#$Ii)", -tc_bf6fa601, TypeSUBINSN>, Enc_2bae10 { +tc_7f881c76, TypeSUBINSN>, Enc_2bae10 { let Inst{12-11} = 0b00; let hasNewValue = 1; let opNewValue = 0; @@ -25293,7 +25783,7 @@ def SL2_loadri_sp : HInst< (outs GeneralSubRegs:$Rd16), (ins u5_2Imm:$Ii), "$Rd16 = memw(r29+#$Ii)", -tc_70cabf66, TypeSUBINSN>, Enc_51635c { +tc_9c98e8af, TypeSUBINSN>, Enc_51635c { let Inst{12-9} = 0b1110; let hasNewValue = 1; let opNewValue = 0; @@ -25308,7 +25798,7 @@ def SL2_loadruh_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), "$Rd16 = memuh($Rs16+#$Ii)", -tc_bf6fa601, TypeSUBINSN>, Enc_2bae10 { +tc_7f881c76, TypeSUBINSN>, Enc_2bae10 { let Inst{12-11} = 0b01; let hasNewValue = 1; let opNewValue = 0; @@ -25322,16 +25812,17 @@ def SL2_return : HInst< (outs), (ins), "dealloc_return", -tc_95c54f8b, TypeSUBINSN>, Enc_e3b0c4 { +tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000000; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; -let cofMax1 = 1; let AsmVariantName = "NonParsable"; let mayLoad = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let Uses = [R30]; +let Uses = [FRAMEKEY, R30]; let Defs = [PC, R30, R29, R31]; let DecoderNamespace = "SUBINSN_L2"; } @@ -25339,18 +25830,19 @@ def SL2_return_f : HInst< (outs), (ins), "if (!p0) dealloc_return", -tc_95c54f8b, TypeSUBINSN>, Enc_e3b0c4 { +tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000101; let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; -let cofMax1 = 1; let AsmVariantName = "NonParsable"; let mayLoad = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let Uses = [P0, R30]; +let Uses = [FRAMEKEY, P0, R30]; let Defs = [PC, R30, R29, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; @@ -25359,19 +25851,20 @@ def SL2_return_fnew : HInst< (outs), (ins), "if (!p0.new) dealloc_return:nt", -tc_95c54f8b, TypeSUBINSN>, Enc_e3b0c4 { +tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000111; let isPredicated = 1; let isPredicatedFalse = 1; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; -let cofMax1 = 1; let AsmVariantName = "NonParsable"; let isPredicatedNew = 1; let mayLoad = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let Uses = [P0, R30]; +let Uses = [FRAMEKEY, P0, R30]; let Defs = [PC, R30, R29, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; @@ -25380,17 +25873,18 @@ def SL2_return_t : HInst< (outs), (ins), "if (p0) dealloc_return", -tc_95c54f8b, TypeSUBINSN>, Enc_e3b0c4 { +tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000100; let isPredicated = 1; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; -let cofMax1 = 1; let AsmVariantName = "NonParsable"; let mayLoad = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let Uses = [P0, R30]; +let Uses = [FRAMEKEY, P0, R30]; let Defs = [PC, R30, R29, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; @@ -25399,18 +25893,19 @@ def SL2_return_tnew : HInst< (outs), (ins), "if (p0.new) dealloc_return:nt", -tc_95c54f8b, TypeSUBINSN>, Enc_e3b0c4 { +tc_fcab4871, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000110; let isPredicated = 1; let isTerminator = 1; let isIndirectBranch = 1; let accessSize = DoubleWordAccess; -let cofMax1 = 1; let AsmVariantName = "NonParsable"; let isPredicatedNew = 1; let mayLoad = 1; +let cofMax1 = 1; +let isRestrictNoSlot1Store = 1; let isReturn = 1; -let Uses = [P0, R30]; +let Uses = [FRAMEKEY, P0, R30]; let Defs = [PC, R30, R29, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; @@ -25419,7 +25914,7 @@ def SS1_storeb_io : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16), "memb($Rs16+#$Ii) = $Rt16", -tc_53ee6546, TypeSUBINSN>, Enc_b38ffc { +tc_05b6c987, TypeSUBINSN>, Enc_b38ffc { let Inst{12-12} = 0b1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; @@ -25431,7 +25926,7 @@ def SS1_storew_io : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16), "memw($Rs16+#$Ii) = $Rt16", -tc_53ee6546, TypeSUBINSN>, Enc_f55a0c { +tc_05b6c987, TypeSUBINSN>, Enc_f55a0c { let Inst{12-12} = 0b0; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -25443,14 +25938,14 @@ def SS2_allocframe : HInst< (outs), (ins u5_3Imm:$Ii), "allocframe(#$Ii)", -tc_f027ebe9, TypeSUBINSN>, Enc_6f70ca { +tc_0fc1ae07, TypeSUBINSN>, Enc_6f70ca { let Inst{3-0} = 0b0000; let Inst{12-9} = 0b1110; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let AsmVariantName = "NonParsable"; let mayStore = 1; -let Uses = [R30, R29, R31]; +let Uses = [FRAMEKEY, FRAMELIMIT, R30, R29, R31]; let Defs = [R30, R29]; let DecoderNamespace = "SUBINSN_S2"; } @@ -25458,7 +25953,7 @@ def SS2_storebi0 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), "memb($Rs16+#$Ii) = #0", -tc_6c52d277, TypeSUBINSN>, Enc_84d359 { +tc_57288781, TypeSUBINSN>, Enc_84d359 { let Inst{12-8} = 0b10010; let addrMode = BaseImmOffset; let accessSize = ByteAccess; @@ -25470,7 +25965,7 @@ def SS2_storebi1 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), "memb($Rs16+#$Ii) = #1", -tc_6c52d277, TypeSUBINSN>, Enc_84d359 { +tc_57288781, TypeSUBINSN>, Enc_84d359 { let Inst{12-8} = 0b10011; let addrMode = BaseImmOffset; let accessSize = ByteAccess; @@ -25482,7 +25977,7 @@ def SS2_stored_sp : HInst< (outs), (ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8), "memd(r29+#$Ii) = $Rtt8", -tc_c14739d5, TypeSUBINSN>, Enc_b8309d { +tc_a788683e, TypeSUBINSN>, Enc_b8309d { let Inst{12-9} = 0b0101; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; @@ -25495,7 +25990,7 @@ def SS2_storeh_io : HInst< (outs), (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16), "memh($Rs16+#$Ii) = $Rt16", -tc_53ee6546, TypeSUBINSN>, Enc_625deb { +tc_05b6c987, TypeSUBINSN>, Enc_625deb { let Inst{12-11} = 0b00; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; @@ -25507,7 +26002,7 @@ def SS2_storew_sp : HInst< (outs), (ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16), "memw(r29+#$Ii) = $Rt16", -tc_c14739d5, TypeSUBINSN>, Enc_87c142 { +tc_a788683e, TypeSUBINSN>, Enc_87c142 { let Inst{12-9} = 0b0100; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -25520,7 +26015,7 @@ def SS2_storewi0 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), "memw($Rs16+#$Ii) = #0", -tc_6c52d277, TypeSUBINSN>, Enc_a6ce9c { +tc_57288781, TypeSUBINSN>, Enc_a6ce9c { let Inst{12-8} = 0b10000; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -25532,7 +26027,7 @@ def SS2_storewi1 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), "memw($Rs16+#$Ii) = #1", -tc_6c52d277, TypeSUBINSN>, Enc_a6ce9c { +tc_57288781, TypeSUBINSN>, Enc_a6ce9c { let Inst{12-8} = 0b10001; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -25544,7 +26039,7 @@ def V6_MAP_equb : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25555,9 +26050,7 @@ def V6_MAP_equb_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -25567,9 +26060,7 @@ def V6_MAP_equb_ior : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -25580,9 +26071,7 @@ def V6_MAP_equb_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -25592,7 +26081,7 @@ def V6_MAP_equh : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25603,9 +26092,7 @@ def V6_MAP_equh_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -25615,9 +26102,7 @@ def V6_MAP_equh_ior : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -25628,9 +26113,7 @@ def V6_MAP_equh_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -25640,7 +26123,7 @@ def V6_MAP_equw : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25651,9 +26134,7 @@ def V6_MAP_equw_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -25663,9 +26144,7 @@ def V6_MAP_equw_ior : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -25676,9 +26155,7 @@ def V6_MAP_equw_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -25688,7 +26165,7 @@ def V6_extractw : HInst< (outs IntRegs:$Rd32), (ins HvxVR:$Vu32, IntRegs:$Rs32), "$Rd32 = vextract($Vu32,$Rs32)", -tc_9777e6bf, TypeLD>, Enc_50e578, Requires<[HasV60T,UseHVX]> { +tc_9777e6bf, TypeLD>, Enc_50e578, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10010010000; @@ -25702,7 +26179,7 @@ def V6_extractw_alt : HInst< (outs IntRegs:$Rd32), (ins HvxVR:$Vu32, IntRegs:$Rs32), "$Rd32.w = vextract($Vu32,$Rs32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25713,7 +26190,7 @@ def V6_hi : HInst< (outs HvxVR:$Vd32), (ins HvxWR:$Vss32), "$Vd32 = hi($Vss32)", -CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25723,7 +26200,7 @@ def V6_ld0 : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vmem($Rt32)", -PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25734,7 +26211,7 @@ def V6_ldcnp0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32.cur = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25745,7 +26222,7 @@ def V6_ldcnpnt0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32.cur = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25756,7 +26233,7 @@ def V6_ldcp0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32.cur = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25767,7 +26244,7 @@ def V6_ldcpnt0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32.cur = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25778,7 +26255,7 @@ def V6_ldnp0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32 = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25789,7 +26266,7 @@ def V6_ldnpnt0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32 = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25800,7 +26277,18 @@ def V6_ldnt0 : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vmem($Rt32):nt", -PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_ldntnt0 : HInst< +(outs HvxVR:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmem($Rt32):nt", +PSEUDO, TypeMAPPING>, Requires<[HasV62T]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25811,7 +26299,7 @@ def V6_ldp0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32 = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25822,7 +26310,7 @@ def V6_ldpnt0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32 = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25833,7 +26321,7 @@ def V6_ldtnp0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32.tmp = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25844,7 +26332,7 @@ def V6_ldtnpnt0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25855,7 +26343,7 @@ def V6_ldtp0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32.tmp = vmem($Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25866,7 +26354,7 @@ def V6_ldtpnt0 : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) $Vd32.tmp = vmem($Rt32):nt", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25877,7 +26365,7 @@ def V6_ldu0 : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vmemu($Rt32)", -PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25888,7 +26376,7 @@ def V6_lo : HInst< (outs HvxVR:$Vd32), (ins HvxWR:$Vss32), "$Vd32 = lo($Vss32)", -CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25898,7 +26386,7 @@ def V6_lvsplatb : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32.b = vsplat($Rt32)", -tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[HasV62T,UseHVX]> { +tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; @@ -25909,7 +26397,7 @@ def V6_lvsplath : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32.h = vsplat($Rt32)", -tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[HasV62T,UseHVX]> { +tc_6b78cf13, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; @@ -25920,7 +26408,7 @@ def V6_lvsplatw : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32 = vsplat($Rt32)", -tc_6b78cf13, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[HasV60T,UseHVX]> { +tc_6b78cf13, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV60]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; @@ -25931,7 +26419,7 @@ def V6_pred_and : HInst< (outs HvxQR:$Qd4), (ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = and($Qs4,$Qt4)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{21-16} = 0b000011; @@ -25944,7 +26432,7 @@ def V6_pred_and_n : HInst< (outs HvxQR:$Qd4), (ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = and($Qs4,!$Qt4)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000101; let Inst{13-10} = 0b0000; let Inst{21-16} = 0b000011; @@ -25957,7 +26445,7 @@ def V6_pred_not : HInst< (outs HvxQR:$Qd4), (ins HvxQR:$Qs4), "$Qd4 = not($Qs4)", -tc_71337255, TypeCVI_VA>, Enc_bfbf03, Requires<[HasV60T,UseHVX]> { +tc_71337255, TypeCVI_VA>, Enc_bfbf03, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000010; let Inst{13-10} = 0b0000; let Inst{31-16} = 0b0001111000000011; @@ -25969,7 +26457,7 @@ def V6_pred_or : HInst< (outs HvxQR:$Qd4), (ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = or($Qs4,$Qt4)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000001; let Inst{13-10} = 0b0000; let Inst{21-16} = 0b000011; @@ -25982,7 +26470,7 @@ def V6_pred_or_n : HInst< (outs HvxQR:$Qd4), (ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = or($Qs4,!$Qt4)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000100; let Inst{13-10} = 0b0000; let Inst{21-16} = 0b000011; @@ -25995,7 +26483,7 @@ def V6_pred_scalar2 : HInst< (outs HvxQR:$Qd4), (ins IntRegs:$Rt32), "$Qd4 = vsetq($Rt32)", -tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[HasV60T,UseHVX]> { +tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV60]> { let Inst{13-2} = 0b000000010001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; @@ -26006,7 +26494,7 @@ def V6_pred_scalar2v2 : HInst< (outs HvxQR:$Qd4), (ins IntRegs:$Rt32), "$Qd4 = vsetq2($Rt32)", -tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[HasV62T,UseHVX]> { +tc_4105d6b5, TypeCVI_VP>, Enc_7222b7, Requires<[UseHVXV62]> { let Inst{13-2} = 0b000000010011; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; @@ -26017,7 +26505,7 @@ def V6_pred_xor : HInst< (outs HvxQR:$Qd4), (ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4 = xor($Qs4,$Qt4)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000011; let Inst{13-10} = 0b0000; let Inst{21-16} = 0b000011; @@ -26030,7 +26518,7 @@ def V6_shuffeqh : HInst< (outs HvxQR:$Qd4), (ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4.b = vshuffe($Qs4.h,$Qt4.h)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV62T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> { let Inst{7-2} = 0b000110; let Inst{13-10} = 0b0000; let Inst{21-16} = 0b000011; @@ -26043,7 +26531,7 @@ def V6_shuffeqw : HInst< (outs HvxQR:$Qd4), (ins HvxQR:$Qs4, HvxQR:$Qt4), "$Qd4.h = vshuffe($Qs4.w,$Qt4.w)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[HasV62T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_134437, Requires<[UseHVXV62]> { let Inst{7-2} = 0b000111; let Inst{13-10} = 0b0000; let Inst{21-16} = 0b000011; @@ -26056,7 +26544,7 @@ def V6_st0 : HInst< (outs), (ins IntRegs:$Rt32, HvxVR:$Vs32), "vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26065,7 +26553,7 @@ def V6_stn0 : HInst< (outs), (ins IntRegs:$Rt32, HvxVR:$Os8), "vmem($Rt32) = $Os8.new", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26075,7 +26563,7 @@ def V6_stnnt0 : HInst< (outs), (ins IntRegs:$Rt32, HvxVR:$Os8), "vmem($Rt32):nt = $Os8.new", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26085,7 +26573,7 @@ def V6_stnp0 : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26094,7 +26582,7 @@ def V6_stnpnt0 : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26103,7 +26591,7 @@ def V6_stnq0 : HInst< (outs), (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26112,7 +26600,7 @@ def V6_stnqnt0 : HInst< (outs), (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26121,7 +26609,7 @@ def V6_stnt0 : HInst< (outs), (ins IntRegs:$Rt32, HvxVR:$Vs32), "vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26130,7 +26618,7 @@ def V6_stp0 : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26139,7 +26627,7 @@ def V6_stpnt0 : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26148,7 +26636,7 @@ def V6_stq0 : HInst< (outs), (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26157,7 +26645,7 @@ def V6_stqnt0 : HInst< (outs), (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32):nt = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26166,7 +26654,7 @@ def V6_stu0 : HInst< (outs), (ins IntRegs:$Rt32, HvxVR:$Vs32), "vmemu($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26175,7 +26663,7 @@ def V6_stunp0 : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26184,7 +26672,7 @@ def V6_stup0 : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmemu($Rt32) = $Vs32", -PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26193,7 +26681,7 @@ def V6_vL32Ub_ai : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32 = vmemu($Rt32+#$Ii)", -tc_35e92f8e, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[HasV60T,UseHVX]> { +tc_35e92f8e, TypeCVI_VM_VP_LDU>, Enc_f3f408, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000000; @@ -26203,13 +26691,14 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vL32Ub_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32 = vmemu($Rx32++#$Ii)", -tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[HasV60T,UseHVX]> { +tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_a255dc, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001000; @@ -26219,6 +26708,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26227,7 +26717,7 @@ def V6_vL32Ub_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32 = vmemu($Rx32++$Mu2)", -tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]> { +tc_4fd8566e, TypeCVI_VM_VP_LDU>, Enc_2ebe3b, Requires<[UseHVXV60]> { let Inst{12-5} = 0b00000111; let Inst{31-21} = 0b00101011000; let hasNewValue = 1; @@ -26236,6 +26726,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -26243,7 +26734,7 @@ def V6_vL32b_ai : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32 = vmem($Rt32+#$Ii)", -tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]>, PredRel { +tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000000; @@ -26253,16 +26744,17 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; +let BaseOpcode = "V6_vL32b_ai"; let isCVLoadable = 1; let isPredicable = 1; -let BaseOpcode = "V6_vL32b_ai"; let DecoderNamespace = "EXT_mmvec"; } def V6_vL32b_cur_ai : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.cur = vmem($Rt32+#$Ii)", -tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]>, PredRel { +tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b001; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000000; @@ -26273,15 +26765,16 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_cur_ai"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vL32b_cur_npred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b101; let Inst{31-21} = 0b00101000100; let isPredicated = 1; @@ -26293,6 +26786,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_cur_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -26300,7 +26794,7 @@ def V6_vL32b_cur_npred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; @@ -26313,6 +26807,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_cur_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26321,7 +26816,7 @@ def V6_vL32b_cur_npred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000101; let Inst{31-21} = 0b00101011100; let isPredicated = 1; @@ -26333,6 +26828,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_cur_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26341,7 +26837,7 @@ def V6_vL32b_cur_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32.cur = vmem($Rx32++#$Ii)", -tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]>, PredRel { +tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b001; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001000; @@ -26352,8 +26848,9 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_cur_pi"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -26361,7 +26858,7 @@ def V6_vL32b_cur_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.cur = vmem($Rx32++$Mu2)", -tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]>, PredRel { +tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { let Inst{12-5} = 0b00000001; let Inst{31-21} = 0b00101011000; let hasNewValue = 1; @@ -26371,8 +26868,9 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_cur_ppu"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -26380,7 +26878,7 @@ def V6_vL32b_cur_pred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b100; let Inst{31-21} = 0b00101000100; let isPredicated = 1; @@ -26391,6 +26889,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_cur_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -26398,7 +26897,7 @@ def V6_vL32b_cur_pred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; @@ -26410,6 +26909,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_cur_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26418,7 +26918,7 @@ def V6_vL32b_cur_pred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000100; let Inst{31-21} = 0b00101011100; let isPredicated = 1; @@ -26429,6 +26929,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_cur_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26437,7 +26938,7 @@ def V6_vL32b_npred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b011; let Inst{31-21} = 0b00101000100; let isPredicated = 1; @@ -26448,6 +26949,7 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -26455,7 +26957,7 @@ def V6_vL32b_npred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; @@ -26467,6 +26969,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26475,7 +26978,7 @@ def V6_vL32b_npred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000011; let Inst{31-21} = 0b00101011100; let isPredicated = 1; @@ -26486,6 +26989,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26494,7 +26998,7 @@ def V6_vL32b_nt_ai : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32 = vmem($Rt32+#$Ii):nt", -tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]>, PredRel { +tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000010; @@ -26505,16 +27009,17 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; +let BaseOpcode = "V6_vL32b_nt_ai"; let isCVLoadable = 1; let isPredicable = 1; -let BaseOpcode = "V6_vL32b_nt_ai"; let DecoderNamespace = "EXT_mmvec"; } def V6_vL32b_nt_cur_ai : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.cur = vmem($Rt32+#$Ii):nt", -tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]>, PredRel { +tc_b712833a, TypeCVI_VM_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b001; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000010; @@ -26526,15 +27031,16 @@ let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_cur_ai"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vL32b_nt_cur_npred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b101; let Inst{31-21} = 0b00101000110; let isPredicated = 1; @@ -26547,6 +27053,7 @@ let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_cur_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -26554,7 +27061,7 @@ def V6_vL32b_nt_cur_npred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; @@ -26568,6 +27075,7 @@ let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_cur_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26576,7 +27084,7 @@ def V6_vL32b_nt_cur_npred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000101; let Inst{31-21} = 0b00101011110; let isPredicated = 1; @@ -26589,6 +27097,7 @@ let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_cur_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26597,7 +27106,7 @@ def V6_vL32b_nt_cur_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32.cur = vmem($Rx32++#$Ii):nt", -tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]>, PredRel { +tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b001; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001010; @@ -26609,8 +27118,9 @@ let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_cur_pi"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -26618,7 +27128,7 @@ def V6_vL32b_nt_cur_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.cur = vmem($Rx32++$Mu2):nt", -tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]>, PredRel { +tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { let Inst{12-5} = 0b00000001; let Inst{31-21} = 0b00101011010; let hasNewValue = 1; @@ -26629,8 +27139,9 @@ let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_cur_ppu"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -26638,7 +27149,7 @@ def V6_vL32b_nt_cur_pred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b100; let Inst{31-21} = 0b00101000110; let isPredicated = 1; @@ -26650,6 +27161,7 @@ let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_cur_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -26657,7 +27169,7 @@ def V6_vL32b_nt_cur_pred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; @@ -26670,6 +27182,7 @@ let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_cur_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26678,7 +27191,7 @@ def V6_vL32b_nt_cur_pred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000100; let Inst{31-21} = 0b00101011110; let isPredicated = 1; @@ -26690,6 +27203,7 @@ let isCVLoad = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_cur_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26698,7 +27212,7 @@ def V6_vL32b_nt_npred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b011; let Inst{31-21} = 0b00101000110; let isPredicated = 1; @@ -26710,6 +27224,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -26717,7 +27232,7 @@ def V6_vL32b_nt_npred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; @@ -26730,6 +27245,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26738,7 +27254,7 @@ def V6_vL32b_nt_npred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000011; let Inst{31-21} = 0b00101011110; let isPredicated = 1; @@ -26750,6 +27266,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26758,7 +27275,7 @@ def V6_vL32b_nt_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32 = vmem($Rx32++#$Ii):nt", -tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]>, PredRel { +tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b000; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001010; @@ -26769,9 +27286,10 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; +let BaseOpcode = "V6_vL32b_nt_pi"; let isCVLoadable = 1; let isPredicable = 1; -let BaseOpcode = "V6_vL32b_nt_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -26779,7 +27297,7 @@ def V6_vL32b_nt_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32 = vmem($Rx32++$Mu2):nt", -tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]>, PredRel { +tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b00101011010; let hasNewValue = 1; @@ -26789,9 +27307,10 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; +let BaseOpcode = "V6_vL32b_nt_ppu"; let isCVLoadable = 1; let isPredicable = 1; -let BaseOpcode = "V6_vL32b_nt_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -26799,7 +27318,7 @@ def V6_vL32b_nt_pred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b010; let Inst{31-21} = 0b00101000110; let isPredicated = 1; @@ -26810,6 +27329,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -26817,7 +27337,7 @@ def V6_vL32b_nt_pred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; @@ -26829,6 +27349,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26837,7 +27358,7 @@ def V6_vL32b_nt_pred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000010; let Inst{31-21} = 0b00101011110; let isPredicated = 1; @@ -26848,6 +27369,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26856,7 +27378,7 @@ def V6_vL32b_nt_tmp_ai : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.tmp = vmem($Rt32+#$Ii):nt", -tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]>, PredRel { +tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b010; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000010; @@ -26867,15 +27389,16 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_tmp_ai"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vL32b_nt_tmp_npred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", -tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b111; let Inst{31-21} = 0b00101000110; let isPredicated = 1; @@ -26887,6 +27410,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_tmp_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -26894,7 +27418,7 @@ def V6_vL32b_nt_tmp_npred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; @@ -26907,6 +27431,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_tmp_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26915,7 +27440,7 @@ def V6_vL32b_nt_tmp_npred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000111; let Inst{31-21} = 0b00101011110; let isPredicated = 1; @@ -26927,6 +27452,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_tmp_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -26935,7 +27461,7 @@ def V6_vL32b_nt_tmp_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32.tmp = vmem($Rx32++#$Ii):nt", -tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]>, PredRel { +tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b010; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001010; @@ -26946,8 +27472,9 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_tmp_pi"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -26955,7 +27482,7 @@ def V6_vL32b_nt_tmp_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.tmp = vmem($Rx32++$Mu2):nt", -tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]>, PredRel { +tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { let Inst{12-5} = 0b00000010; let Inst{31-21} = 0b00101011010; let hasNewValue = 1; @@ -26965,8 +27492,9 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_tmp_ppu"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -26974,7 +27502,7 @@ def V6_vL32b_nt_tmp_pred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", -tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b110; let Inst{31-21} = 0b00101000110; let isPredicated = 1; @@ -26985,6 +27513,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_tmp_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -26992,7 +27521,7 @@ def V6_vL32b_nt_tmp_pred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; @@ -27004,6 +27533,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_tmp_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -27012,7 +27542,7 @@ def V6_vL32b_nt_tmp_pred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000110; let Inst{31-21} = 0b00101011110; let isPredicated = 1; @@ -27023,6 +27553,7 @@ let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; let isNonTemporal = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_nt_tmp_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -27031,7 +27562,7 @@ def V6_vL32b_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32 = vmem($Rx32++#$Ii)", -tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]>, PredRel { +tc_eb669007, TypeCVI_VM_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b000; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001000; @@ -27041,6 +27572,8 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; +let BaseOpcode = "V6_vL32b_pi"; let isCVLoadable = 1; let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; @@ -27050,7 +27583,7 @@ def V6_vL32b_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32 = vmem($Rx32++$Mu2)", -tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]>, PredRel { +tc_eb669007, TypeCVI_VM_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b00101011000; let hasNewValue = 1; @@ -27059,9 +27592,10 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; +let BaseOpcode = "V6_vL32b_ppu"; let isCVLoadable = 1; let isPredicable = 1; -let BaseOpcode = "V6_vL32b_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -27069,7 +27603,7 @@ def V6_vL32b_pred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)", -tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_5cbf490b, TypeCVI_VM_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b010; let Inst{31-21} = 0b00101000100; let isPredicated = 1; @@ -27079,6 +27613,7 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -27086,7 +27621,7 @@ def V6_vL32b_pred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; @@ -27097,6 +27632,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -27105,7 +27641,7 @@ def V6_vL32b_pred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)", -tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_da979fb3, TypeCVI_VM_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000010; let Inst{31-21} = 0b00101011100; let isPredicated = 1; @@ -27115,6 +27651,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -27123,7 +27660,7 @@ def V6_vL32b_tmp_ai : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), "$Vd32.tmp = vmem($Rt32+#$Ii)", -tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[HasV60T,UseHVX]>, PredRel { +tc_77a4c701, TypeCVI_VM_TMP_LD>, Enc_f3f408, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b010; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000000; @@ -27133,15 +27670,16 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vL32b_tmp_npred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", -tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b111; let Inst{31-21} = 0b00101000100; let isPredicated = 1; @@ -27152,6 +27690,7 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -27159,7 +27698,7 @@ def V6_vL32b_tmp_npred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; @@ -27171,6 +27710,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -27179,7 +27719,7 @@ def V6_vL32b_tmp_npred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000111; let Inst{31-21} = 0b00101011100; let isPredicated = 1; @@ -27190,6 +27730,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -27198,7 +27739,7 @@ def V6_vL32b_tmp_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii), "$Vd32.tmp = vmem($Rx32++#$Ii)", -tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[HasV60T,UseHVX]>, PredRel { +tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_a255dc, Requires<[UseHVXV60]>, PredRel { let Inst{7-5} = 0b010; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001000; @@ -27208,8 +27749,9 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -27217,7 +27759,7 @@ def V6_vL32b_tmp_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Vd32.tmp = vmem($Rx32++$Mu2)", -tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[HasV60T,UseHVX]>, PredRel { +tc_9c267309, TypeCVI_VM_TMP_LD>, Enc_2ebe3b, Requires<[UseHVXV60]>, PredRel { let Inst{12-5} = 0b00000010; let Inst{31-21} = 0b00101011000; let hasNewValue = 1; @@ -27226,8 +27768,9 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; -let isPredicable = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; +let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } @@ -27235,7 +27778,7 @@ def V6_vL32b_tmp_pred_ai : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", -tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[HasV62T,UseHVX]>, PredRel { +tc_51cd3aab, TypeCVI_VM_TMP_LD>, Enc_8d8a30, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b110; let Inst{31-21} = 0b00101000100; let isPredicated = 1; @@ -27245,6 +27788,7 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; let DecoderNamespace = "EXT_mmvec"; } @@ -27252,7 +27796,7 @@ def V6_vL32b_tmp_pred_pi : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), "if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[HasV62T,UseHVX]>, PredRel { +tc_38208312, TypeCVI_VM_TMP_LD>, Enc_58a8bf, Requires<[UseHVXV62]>, PredRel { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; @@ -27263,6 +27807,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -27271,7 +27816,7 @@ def V6_vL32b_tmp_pred_ppu : HInst< (outs HvxVR:$Vd32, IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), "if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", -tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[HasV62T,UseHVX]>, PredRel { +tc_38208312, TypeCVI_VM_TMP_LD>, Enc_f8c1c4, Requires<[UseHVXV62]>, PredRel { let Inst{10-5} = 0b000110; let Inst{31-21} = 0b00101011100; let isPredicated = 1; @@ -27281,6 +27826,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let mayLoad = 1; +let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -27289,7 +27835,7 @@ def V6_vS32Ub_ai : HInst< (outs), (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "vmemu($Rt32+#$Ii) = $Vs32", -tc_354299ad, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_354299ad, TypeCVI_VM_STU>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b111; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; @@ -27304,7 +27850,7 @@ def V6_vS32Ub_npred_ai : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32", -tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b111; let Inst{31-21} = 0b00101000101; let isPredicated = 1; @@ -27319,7 +27865,7 @@ def V6_vS32Ub_npred_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32", -tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001101; @@ -27336,7 +27882,7 @@ def V6_vS32Ub_npred_ppu : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32", -tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { let Inst{10-5} = 0b000111; let Inst{31-21} = 0b00101011101; let isPredicated = 1; @@ -27352,7 +27898,7 @@ def V6_vS32Ub_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "vmemu($Rx32++#$Ii) = $Vs32", -tc_7fa82b08, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_7fa82b08, TypeCVI_VM_STU>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b111; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; @@ -27368,7 +27914,7 @@ def V6_vS32Ub_ppu : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "vmemu($Rx32++$Mu2) = $Vs32", -tc_7fa82b08, TypeCVI_VM_STU>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_7fa82b08, TypeCVI_VM_STU>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel { let Inst{12-5} = 0b00000111; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; @@ -27383,7 +27929,7 @@ def V6_vS32Ub_pred_ai : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32", -tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_d642eff3, TypeCVI_VM_STU>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b110; let Inst{31-21} = 0b00101000101; let isPredicated = 1; @@ -27397,7 +27943,7 @@ def V6_vS32Ub_pred_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32", -tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_6fd9ad30, TypeCVI_VM_STU>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001101; @@ -27413,7 +27959,7 @@ def V6_vS32Ub_pred_ppu : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32", -tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_6fd9ad30, TypeCVI_VM_STU>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { let Inst{10-5} = 0b000110; let Inst{31-21} = 0b00101011101; let isPredicated = 1; @@ -27428,7 +27974,7 @@ def V6_vS32b_ai : HInst< (outs), (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rt32+#$Ii) = $Vs32", -tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; @@ -27444,7 +27990,7 @@ def V6_vS32b_new_ai : HInst< (outs), (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "vmem($Rt32+#$Ii) = $Os8.new", -tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b00100; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; @@ -27463,7 +28009,7 @@ def V6_vS32b_new_npred_ai : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new", -tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b01101; let Inst{31-21} = 0b00101000101; let isPredicated = 1; @@ -27482,7 +28028,7 @@ def V6_vS32b_new_npred_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b01101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001101; @@ -27503,7 +28049,7 @@ def V6_vS32b_new_npred_ppu : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel { let Inst{10-3} = 0b00001101; let Inst{31-21} = 0b00101011101; let isPredicated = 1; @@ -27523,7 +28069,7 @@ def V6_vS32b_new_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "vmem($Rx32++#$Ii) = $Os8.new", -tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b00100; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; @@ -27543,7 +28089,7 @@ def V6_vS32b_new_ppu : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "vmem($Rx32++$Mu2) = $Os8.new", -tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel { let Inst{12-3} = 0b0000000100; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; @@ -27562,7 +28108,7 @@ def V6_vS32b_new_pred_ai : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new", -tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b01000; let Inst{31-21} = 0b00101000101; let isPredicated = 1; @@ -27580,7 +28126,7 @@ def V6_vS32b_new_pred_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b01000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001101; @@ -27600,7 +28146,7 @@ def V6_vS32b_new_pred_ppu : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel { let Inst{10-3} = 0b00001000; let Inst{31-21} = 0b00101011101; let isPredicated = 1; @@ -27619,7 +28165,7 @@ def V6_vS32b_npred_ai : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32", -tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101000101; let isPredicated = 1; @@ -27635,7 +28181,7 @@ def V6_vS32b_npred_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001101; @@ -27653,7 +28199,7 @@ def V6_vS32b_npred_ppu : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { let Inst{10-5} = 0b000001; let Inst{31-21} = 0b00101011101; let isPredicated = 1; @@ -27670,7 +28216,7 @@ def V6_vS32b_nqpred_ai : HInst< (outs), (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32", -tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { +tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101000100; let addrMode = BaseImmOffset; @@ -27682,7 +28228,7 @@ def V6_vS32b_nqpred_pi : HInst< (outs IntRegs:$Rx32), (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { +tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; @@ -27696,7 +28242,7 @@ def V6_vS32b_nqpred_ppu : HInst< (outs IntRegs:$Rx32), (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { +tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> { let Inst{10-5} = 0b000001; let Inst{31-21} = 0b00101011100; let addrMode = PostInc; @@ -27709,7 +28255,7 @@ def V6_vS32b_nt_ai : HInst< (outs), (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rt32+#$Ii):nt = $Vs32", -tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_e3748cdf, TypeCVI_VM_ST>, Enc_c9e3bc, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000011; @@ -27726,7 +28272,7 @@ def V6_vS32b_nt_new_ai : HInst< (outs), (ins IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "vmem($Rt32+#$Ii):nt = $Os8.new", -tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_1b93bdc6, TypeCVI_VM_NEW_ST>, Enc_f77fbc, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b00100; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000011; @@ -27746,7 +28292,7 @@ def V6_vS32b_nt_new_npred_ai : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", -tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b01111; let Inst{31-21} = 0b00101000111; let isPredicated = 1; @@ -27766,7 +28312,7 @@ def V6_vS32b_nt_new_npred_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b01111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001111; @@ -27788,7 +28334,7 @@ def V6_vS32b_nt_new_npred_ppu : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel { let Inst{10-3} = 0b00001111; let Inst{31-21} = 0b00101011111; let isPredicated = 1; @@ -27809,7 +28355,7 @@ def V6_vS32b_nt_new_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "vmem($Rx32++#$Ii):nt = $Os8.new", -tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_1aaec1, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b00100; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001011; @@ -27830,7 +28376,7 @@ def V6_vS32b_nt_new_ppu : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "vmem($Rx32++$Mu2):nt = $Os8.new", -tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_db5b9e2f, TypeCVI_VM_NEW_ST>, Enc_cf1927, Requires<[UseHVXV60]>, NewValueRel { let Inst{12-3} = 0b0000000100; let Inst{31-21} = 0b00101011011; let addrMode = PostInc; @@ -27850,7 +28396,7 @@ def V6_vS32b_nt_new_pred_ai : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", -tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_d5090f3e, TypeCVI_VM_NEW_ST>, Enc_f7430e, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b01010; let Inst{31-21} = 0b00101000111; let isPredicated = 1; @@ -27869,7 +28415,7 @@ def V6_vS32b_nt_new_pred_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Os8), "if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_784502, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-3} = 0b01010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001111; @@ -27890,7 +28436,7 @@ def V6_vS32b_nt_new_pred_ppu : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Os8), "if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", -tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_8b6a873f, TypeCVI_VM_NEW_ST>, Enc_372c9d, Requires<[UseHVXV60]>, NewValueRel { let Inst{10-3} = 0b00001010; let Inst{31-21} = 0b00101011111; let isPredicated = 1; @@ -27910,7 +28456,7 @@ def V6_vS32b_nt_npred_ai : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32", -tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101000111; let isPredicated = 1; @@ -27927,7 +28473,7 @@ def V6_vS32b_nt_npred_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001111; @@ -27946,7 +28492,7 @@ def V6_vS32b_nt_npred_ppu : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { let Inst{10-5} = 0b000001; let Inst{31-21} = 0b00101011111; let isPredicated = 1; @@ -27964,7 +28510,7 @@ def V6_vS32b_nt_nqpred_ai : HInst< (outs), (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32", -tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { +tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101000110; let addrMode = BaseImmOffset; @@ -27977,7 +28523,7 @@ def V6_vS32b_nt_nqpred_pi : HInst< (outs IntRegs:$Rx32), (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { +tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; @@ -27992,7 +28538,7 @@ def V6_vS32b_nt_nqpred_ppu : HInst< (outs IntRegs:$Rx32), (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { +tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> { let Inst{10-5} = 0b000001; let Inst{31-21} = 0b00101011110; let addrMode = PostInc; @@ -28006,7 +28552,7 @@ def V6_vS32b_nt_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rx32++#$Ii):nt = $Vs32", -tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001011; @@ -28024,7 +28570,7 @@ def V6_vS32b_nt_ppu : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "vmem($Rx32++$Mu2):nt = $Vs32", -tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b00101011011; let addrMode = PostInc; @@ -28041,7 +28587,7 @@ def V6_vS32b_nt_pred_ai : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32", -tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000111; let isPredicated = 1; @@ -28057,7 +28603,7 @@ def V6_vS32b_nt_pred_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001111; @@ -28075,7 +28621,7 @@ def V6_vS32b_nt_pred_ppu : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011111; let isPredicated = 1; @@ -28092,7 +28638,7 @@ def V6_vS32b_nt_qpred_ai : HInst< (outs), (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32", -tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { +tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000110; let addrMode = BaseImmOffset; @@ -28105,7 +28651,7 @@ def V6_vS32b_nt_qpred_pi : HInst< (outs IntRegs:$Rx32), (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { +tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; @@ -28120,7 +28666,7 @@ def V6_vS32b_nt_qpred_ppu : HInst< (outs IntRegs:$Rx32), (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { +tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> { let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011110; let addrMode = PostInc; @@ -28134,7 +28680,7 @@ def V6_vS32b_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "vmem($Rx32++#$Ii) = $Vs32", -tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_a4c9df3b, TypeCVI_VM_ST>, Enc_b62ef7, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; @@ -28151,7 +28697,7 @@ def V6_vS32b_ppu : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "vmem($Rx32++$Mu2) = $Vs32", -tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_a4c9df3b, TypeCVI_VM_ST>, Enc_d15d19, Requires<[UseHVXV60]>, NewValueRel { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; @@ -28166,7 +28712,7 @@ def V6_vS32b_pred_ai : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32+#$Ii) = $Vs32", -tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_85d237e3, TypeCVI_VM_ST>, Enc_27b757, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000101; let isPredicated = 1; @@ -28181,7 +28727,7 @@ def V6_vS32b_pred_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++#$Ii) = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_0317c6ca, TypeCVI_VM_ST>, Enc_865390, Requires<[UseHVXV60]>, NewValueRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001101; @@ -28198,7 +28744,7 @@ def V6_vS32b_pred_ppu : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Pv4) vmem($Rx32++$Mu2) = $Vs32", -tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[HasV60T,UseHVX]>, NewValueRel { +tc_0317c6ca, TypeCVI_VM_ST>, Enc_1ef990, Requires<[UseHVXV60]>, NewValueRel { let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011101; let isPredicated = 1; @@ -28214,7 +28760,7 @@ def V6_vS32b_qpred_ai : HInst< (outs), (ins HvxQR:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32+#$Ii) = $Vs32", -tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[HasV60T,UseHVX]> { +tc_aedb9f9e, TypeCVI_VM_ST>, Enc_2ea740, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000100; let addrMode = BaseImmOffset; @@ -28226,7 +28772,7 @@ def V6_vS32b_qpred_pi : HInst< (outs IntRegs:$Rx32), (ins HvxQR:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++#$Ii) = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[HasV60T,UseHVX]> { +tc_99093773, TypeCVI_VM_ST>, Enc_0b51ce, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; @@ -28240,7 +28786,7 @@ def V6_vS32b_qpred_ppu : HInst< (outs IntRegs:$Rx32), (ins HvxQR:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, HvxVR:$Vs32), "if ($Qv4) vmem($Rx32++$Mu2) = $Vs32", -tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[HasV60T,UseHVX]> { +tc_99093773, TypeCVI_VM_ST>, Enc_4dff07, Requires<[UseHVXV60]> { let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011100; let addrMode = PostInc; @@ -28249,11 +28795,100 @@ let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; } +def V6_vS32b_srls_ai : HInst< +(outs), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"vmem($Rt32+#$Ii):scatter_release", +tc_29841470, TypeCVI_SCATTER_NEW_RST>, Enc_ff3442, Requires<[UseHVXV65]> { +let Inst{7-0} = 0b00101000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = HVXVectorAccess; +let CVINew = 1; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_srls_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"vmem($Rx32++#$Ii):scatter_release", +tc_5c03dc63, TypeCVI_SCATTER_NEW_RST>, Enc_6c9ee0, Requires<[UseHVXV65]> { +let Inst{7-0} = 0b00101000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = HVXVectorAccess; +let CVINew = 1; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_srls_ppu : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"vmem($Rx32++$Mu2):scatter_release", +tc_5c03dc63, TypeCVI_SCATTER_NEW_RST>, Enc_44661f, Requires<[UseHVXV65]> { +let Inst{12-0} = 0b0000000101000; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = HVXVectorAccess; +let CVINew = 1; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vabsb : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), +"$Vd32.b = vabs($Vu32.b)", +tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsb_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), +"$Vd32 = vabsb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsb_sat : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), +"$Vd32.b = vabs($Vu32.b):sat", +tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsb_sat_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), +"$Vd32 = vabsb($Vu32):sat", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} def V6_vabsdiffh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; @@ -28265,7 +28900,7 @@ def V6_vabsdiffh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28276,7 +28911,7 @@ def V6_vabsdiffub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; @@ -28288,7 +28923,7 @@ def V6_vabsdiffub_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28299,7 +28934,7 @@ def V6_vabsdiffuh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; @@ -28311,7 +28946,7 @@ def V6_vabsdiffuh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28322,7 +28957,7 @@ def V6_vabsdiffw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; @@ -28334,7 +28969,7 @@ def V6_vabsdiffw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vabsdiffw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28345,7 +28980,7 @@ def V6_vabsh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.h = vabs($Vu32.h)", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; @@ -28357,7 +28992,7 @@ def V6_vabsh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vabsh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28368,7 +29003,7 @@ def V6_vabsh_sat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.h = vabs($Vu32.h):sat", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; @@ -28380,7 +29015,40 @@ def V6_vabsh_sat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vabsh($Vu32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsub_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), +"$Vd32.ub = vabs($Vu32.b)", +tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsuh_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), +"$Vd32.uh = vabs($Vu32.h)", +tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsuw_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32), +"$Vd32.uw = vabs($Vu32.w)", +tc_71337255, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28391,7 +29059,7 @@ def V6_vabsw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.w = vabs($Vu32.w)", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; @@ -28403,7 +29071,7 @@ def V6_vabsw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vabsw($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28414,7 +29082,7 @@ def V6_vabsw_sat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.w = vabs($Vu32.w):sat", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; @@ -28426,7 +29094,7 @@ def V6_vabsw_sat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vabsw($Vu32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28437,7 +29105,7 @@ def V6_vaddb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vadd($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; @@ -28449,7 +29117,7 @@ def V6_vaddb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28460,7 +29128,7 @@ def V6_vaddb_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; @@ -28472,7 +29140,7 @@ def V6_vaddb_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddb($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28483,7 +29151,7 @@ def V6_vaddbnq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.b += $Vu32.b", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000001; @@ -28498,7 +29166,7 @@ def V6_vaddbnq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.b) $Vx32.b += $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -28511,7 +29179,7 @@ def V6_vaddbq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.b += $Vu32.b", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000001; @@ -28526,7 +29194,7 @@ def V6_vaddbq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.b) $Vx32.b += $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -28539,7 +29207,7 @@ def V6_vaddbsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vadd($Vu32.b,$Vv32.b):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; @@ -28551,7 +29219,7 @@ def V6_vaddbsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28562,7 +29230,7 @@ def V6_vaddbsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; @@ -28574,7 +29242,7 @@ def V6_vaddbsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddb($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28585,14 +29253,12 @@ def V6_vaddcarry : HInst< (outs HvxVR:$Vd32, HvxQR:$Qx4), (ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in), "$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry", -tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[HasV62T,UseHVX]> { +tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -28600,7 +29266,7 @@ def V6_vaddclbh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; @@ -28612,7 +29278,7 @@ def V6_vaddclbw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; @@ -28624,7 +29290,7 @@ def V6_vaddh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vadd($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; @@ -28636,7 +29302,7 @@ def V6_vaddh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28647,7 +29313,7 @@ def V6_vaddh_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; @@ -28659,7 +29325,7 @@ def V6_vaddh_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddh($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28670,7 +29336,7 @@ def V6_vaddhnq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.h += $Vu32.h", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000001; @@ -28685,7 +29351,7 @@ def V6_vaddhnq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.h) $Vx32.h += $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -28698,7 +29364,7 @@ def V6_vaddhq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.h += $Vu32.h", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000001; @@ -28713,7 +29379,7 @@ def V6_vaddhq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.h) $Vx32.h += $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -28726,7 +29392,7 @@ def V6_vaddhsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vadd($Vu32.h,$Vv32.h):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; @@ -28738,7 +29404,7 @@ def V6_vaddhsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28749,7 +29415,7 @@ def V6_vaddhsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; @@ -28761,7 +29427,7 @@ def V6_vaddhsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28772,7 +29438,7 @@ def V6_vaddhw : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vadd($Vu32.h,$Vv32.h)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; @@ -28784,7 +29450,7 @@ def V6_vaddhw_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vadd($Vu32.h,$Vv32.h)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100001; @@ -28798,7 +29464,7 @@ def V6_vaddhw_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vaddh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -28811,7 +29477,7 @@ def V6_vaddhw_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vaddh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28822,7 +29488,7 @@ def V6_vaddubh : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; @@ -28834,7 +29500,7 @@ def V6_vaddubh_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100010; @@ -28848,7 +29514,7 @@ def V6_vaddubh_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vaddub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -28861,7 +29527,7 @@ def V6_vaddubh_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vaddub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28872,7 +29538,7 @@ def V6_vaddubsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; @@ -28884,7 +29550,7 @@ def V6_vaddubsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28895,7 +29561,7 @@ def V6_vaddubsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; @@ -28907,7 +29573,7 @@ def V6_vaddubsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddub($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28918,7 +29584,7 @@ def V6_vaddububb_sat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; @@ -28930,7 +29596,7 @@ def V6_vadduhsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; @@ -28942,7 +29608,7 @@ def V6_vadduhsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vadduh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28953,7 +29619,7 @@ def V6_vadduhsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; @@ -28965,7 +29631,7 @@ def V6_vadduhsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vadduh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -28976,7 +29642,7 @@ def V6_vadduhw : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; @@ -28988,7 +29654,7 @@ def V6_vadduhw_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100010; @@ -29002,7 +29668,7 @@ def V6_vadduhw_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vadduh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -29015,7 +29681,7 @@ def V6_vadduhw_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vadduh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29026,7 +29692,7 @@ def V6_vadduwsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; @@ -29038,7 +29704,7 @@ def V6_vadduwsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vadduw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29049,7 +29715,7 @@ def V6_vadduwsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; @@ -29061,7 +29727,7 @@ def V6_vadduwsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vadduw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29072,7 +29738,7 @@ def V6_vaddw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vadd($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; @@ -29084,7 +29750,7 @@ def V6_vaddw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29095,7 +29761,7 @@ def V6_vaddw_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; @@ -29107,7 +29773,7 @@ def V6_vaddw_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddw($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29118,7 +29784,7 @@ def V6_vaddwnq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.w += $Vu32.w", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000001; @@ -29133,7 +29799,7 @@ def V6_vaddwnq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.w) $Vx32.w += $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -29146,7 +29812,7 @@ def V6_vaddwq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.w += $Vu32.w", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000001; @@ -29161,7 +29827,7 @@ def V6_vaddwq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.w) $Vx32.w += $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -29174,7 +29840,7 @@ def V6_vaddwsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vadd($Vu32.w,$Vv32.w):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; @@ -29186,7 +29852,7 @@ def V6_vaddwsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaddw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29197,7 +29863,7 @@ def V6_vaddwsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; @@ -29209,7 +29875,7 @@ def V6_vaddwsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vaddw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29220,7 +29886,7 @@ def V6_valignb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = valign($Vu32,$Vv32,$Rt8)", -tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> { +tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; @@ -29232,7 +29898,7 @@ def V6_valignbi : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vd32 = valign($Vu32,$Vv32,#$Ii)", -tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV60T,UseHVX]> { +tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> { let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110001; let hasNewValue = 1; @@ -29243,7 +29909,7 @@ def V6_vand : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vand($Vu32,$Vv32)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; @@ -29255,7 +29921,7 @@ def V6_vandnqrt : HInst< (outs HvxVR:$Vd32), (ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32 = vand(!$Qu4,$Rt32)", -tc_e231aa4f, TypeCVI_VX>, Enc_7b7ba8, Requires<[HasV62T,UseHVX]> { +tc_e231aa4f, TypeCVI_VX>, Enc_7b7ba8, Requires<[UseHVXV62]> { let Inst{7-5} = 0b101; let Inst{13-10} = 0b0001; let Inst{31-21} = 0b00011001101; @@ -29267,7 +29933,7 @@ def V6_vandnqrt_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32 |= vand(!$Qu4,$Rt32)", -tc_9311da3f, TypeCVI_VX>, Enc_895bd9, Requires<[HasV62T,UseHVX]> { +tc_9311da3f, TypeCVI_VX>, Enc_895bd9, Requires<[UseHVXV62]> { let Inst{7-5} = 0b011; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b00011001011; @@ -29281,7 +29947,7 @@ def V6_vandnqrt_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -29294,7 +29960,7 @@ def V6_vandnqrt_alt : HInst< (outs HvxVR:$Vd32), (ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29305,7 +29971,7 @@ def V6_vandqrt : HInst< (outs HvxVR:$Vd32), (ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32 = vand($Qu4,$Rt32)", -tc_e231aa4f, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[HasV60T,UseHVX]> { +tc_e231aa4f, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b00011001101; @@ -29317,7 +29983,7 @@ def V6_vandqrt_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32 |= vand($Qu4,$Rt32)", -tc_9311da3f, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[HasV60T,UseHVX]> { +tc_9311da3f, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b00011001011; @@ -29331,7 +29997,7 @@ def V6_vandqrt_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -29344,7 +30010,7 @@ def V6_vandqrt_alt : HInst< (outs HvxVR:$Vd32), (ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29355,7 +30021,7 @@ def V6_vandvnqv : HInst< (outs HvxVR:$Vd32), (ins HvxQR:$Qv4, HvxVR:$Vu32), "$Vd32 = vand(!$Qv4,$Vu32)", -tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[HasV62T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000011; @@ -29368,7 +30034,7 @@ def V6_vandvqv : HInst< (outs HvxVR:$Vd32), (ins HvxQR:$Qv4, HvxVR:$Vu32), "$Vd32 = vand($Qv4,$Vu32)", -tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[HasV62T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_c4dc92, Requires<[UseHVXV62]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000011; @@ -29381,7 +30047,7 @@ def V6_vandvrt : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Qd4 = vand($Vu32,$Rt32)", -tc_e231aa4f, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[HasV60T,UseHVX]> { +tc_e231aa4f, TypeCVI_VX_LATE>, Enc_0f8bab, Requires<[UseHVXV60]> { let Inst{7-2} = 0b010010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; @@ -29393,12 +30059,10 @@ def V6_vandvrt_acc : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32), "$Qx4 |= vand($Vu32,$Rt32)", -tc_9311da3f, TypeCVI_VX_LATE>, Enc_adf111, Requires<[HasV60T,UseHVX]> { +tc_9311da3f, TypeCVI_VX_LATE>, Enc_adf111, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001011; -let hasNewValue = 1; -let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; @@ -29407,9 +30071,7 @@ def V6_vandvrt_acc_alt : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, IntRegs:$Rt32), "$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { -let hasNewValue = 1; -let opNewValue = 0; +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -29420,7 +30082,7 @@ def V6_vandvrt_alt : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29431,7 +30093,7 @@ def V6_vaslh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vasl($Vu32.h,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; @@ -29439,11 +30101,38 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } +def V6_vaslh_acc : HInst< +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), +"$Vx32.h += vasl($Vu32.h,$Rt32)", +tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaslh_acc_alt : HInst< +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), +"$Vx32 += vaslh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} def V6_vaslh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vaslh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29454,7 +30143,7 @@ def V6_vaslhv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vasl($Vu32.h,$Vv32.h)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; @@ -29466,7 +30155,7 @@ def V6_vaslhv_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaslh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29477,7 +30166,7 @@ def V6_vaslw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vasl($Vu32.w,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; @@ -29489,7 +30178,7 @@ def V6_vaslw_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vasl($Vu32.w,$Rt32)", -tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { +tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001011; @@ -29503,7 +30192,7 @@ def V6_vaslw_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vaslw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -29516,7 +30205,7 @@ def V6_vaslw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vaslw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29527,7 +30216,7 @@ def V6_vaslwv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vasl($Vu32.w,$Vv32.w)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; @@ -29539,7 +30228,7 @@ def V6_vaslwv_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vaslw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29550,7 +30239,7 @@ def V6_vasrh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vasr($Vu32.h,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; @@ -29558,11 +30247,38 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } +def V6_vasrh_acc : HInst< +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), +"$Vx32.h += vasr($Vu32.h,$Rt32)", +tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vasrh_acc_alt : HInst< +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), +"$Vx32 += vasrh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} def V6_vasrh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vasrh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29573,7 +30289,7 @@ def V6_vasrhbrndsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; @@ -29595,7 +30311,7 @@ def V6_vasrhbsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> { +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; @@ -29607,7 +30323,7 @@ def V6_vasrhubrndsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; @@ -29629,7 +30345,7 @@ def V6_vasrhubsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; @@ -29651,7 +30367,7 @@ def V6_vasrhv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vasr($Vu32.h,$Vv32.h)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; @@ -29663,18 +30379,42 @@ def V6_vasrhv_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vasrh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } +def V6_vasruhubrndsat : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):rnd:sat", +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasruhubsat : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.ub = vasr($Vu32.uh,$Vv32.uh,$Rt8):sat", +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} def V6_vasruwuhrndsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> { +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; @@ -29682,11 +30422,23 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } +def V6_vasruwuhsat : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):sat", +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} def V6_vasrw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vasr($Vu32.w,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; @@ -29698,7 +30450,7 @@ def V6_vasrw_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vasr($Vu32.w,$Rt32)", -tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { +tc_c00bf9c9, TypeCVI_VS>, Enc_5138b3, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001011; @@ -29712,7 +30464,7 @@ def V6_vasrw_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vasrw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -29725,7 +30477,7 @@ def V6_vasrw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vasrw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29736,7 +30488,7 @@ def V6_vasrwh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; @@ -29758,7 +30510,7 @@ def V6_vasrwhrndsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; @@ -29780,7 +30532,7 @@ def V6_vasrwhsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; @@ -29802,7 +30554,7 @@ def V6_vasrwuhrndsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV62T,UseHVX]> { +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV62]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; @@ -29814,7 +30566,7 @@ def V6_vasrwuhsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat", -tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[HasV60T,UseHVX]> { +tc_7fa8b40f, TypeCVI_VS>, Enc_a30110, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; @@ -29836,7 +30588,7 @@ def V6_vasrwv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vasr($Vu32.w,$Vv32.w)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; @@ -29848,7 +30600,7 @@ def V6_vasrwv_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vasrw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29859,7 +30611,7 @@ def V6_vassign : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = $Vu32", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b1; let Inst{31-16} = 0b0001111000000011; @@ -29871,17 +30623,63 @@ def V6_vassignp : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32), "$Vdd32 = $Vuu32", -CVI_VA, TypeCVI_VA_DV>, Requires<[HasV60T,UseHVX]> { +CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; } +def V6_vavgb : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32.b = vavg($Vu32.b,$Vv32.b)", +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgb_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32 = vavgb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgbrnd : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32.b = vavg($Vu32.b,$Vv32.b):rnd", +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgbrnd_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32 = vavgb($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} def V6_vavgh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vavg($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; @@ -29893,7 +30691,7 @@ def V6_vavgh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29904,7 +30702,7 @@ def V6_vavghrnd : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; @@ -29916,7 +30714,7 @@ def V6_vavghrnd_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgh($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29927,7 +30725,7 @@ def V6_vavgub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; @@ -29939,7 +30737,7 @@ def V6_vavgub_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29950,7 +30748,7 @@ def V6_vavgubrnd : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; @@ -29962,7 +30760,7 @@ def V6_vavgubrnd_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgub($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29973,7 +30771,7 @@ def V6_vavguh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; @@ -29985,7 +30783,7 @@ def V6_vavguh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavguh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -29996,7 +30794,7 @@ def V6_vavguhrnd : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; @@ -30008,7 +30806,53 @@ def V6_vavguhrnd_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavguh($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguw : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw)", +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguw_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32 = vavguw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguwrnd : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32.uw = vavg($Vu32.uw,$Vv32.uw):rnd", +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguwrnd_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32 = vavguw($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30019,7 +30863,7 @@ def V6_vavgw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vavg($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; @@ -30031,7 +30875,7 @@ def V6_vavgw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30042,7 +30886,7 @@ def V6_vavgwrnd : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; @@ -30054,7 +30898,7 @@ def V6_vavgwrnd_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vavgw($Vu32,$Vv32):rnd", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30065,7 +30909,7 @@ def V6_vccombine : HInst< (outs HvxWR:$Vdd32), (ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32), "if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", -tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[HasV60T,UseHVX]> { +tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011010011; @@ -30078,7 +30922,7 @@ def V6_vcl0h : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.uh = vcl0($Vu32.uh)", -tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; @@ -30090,7 +30934,7 @@ def V6_vcl0h_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vcl0h($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30101,7 +30945,7 @@ def V6_vcl0w : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.uw = vcl0($Vu32.uw)", -tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; @@ -30113,7 +30957,7 @@ def V6_vcl0w_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vcl0w($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30124,7 +30968,7 @@ def V6_vcmov : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Ps4, HvxVR:$Vu32), "if ($Ps4) $Vd32 = $Vu32", -tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[HasV60T,UseHVX]> { +tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001101000000000; @@ -30137,7 +30981,7 @@ def V6_vcombine : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vcombine($Vu32,$Vv32)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; @@ -30150,7 +30994,18 @@ def V6_vd0 : HInst< (outs HvxVR:$Vd32), (ins), "$Vd32 = #0", -CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdd0 : HInst< +(outs HvxWR:$Vdd32), +(ins), +"$Vdd32 = #0", +tc_8a6eb39a, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30161,7 +31016,7 @@ def V6_vdeal : HInst< (outs HvxVR:$Vy32, HvxVR:$Vx32), (ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), "vdeal($Vy32,$Vx32,$Rt32)", -tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[HasV60T,UseHVX]> { +tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001111; @@ -30176,7 +31031,7 @@ def V6_vdealb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.b = vdeal($Vu32.b)", -tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; @@ -30188,7 +31043,7 @@ def V6_vdealb4w : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vdeale($Vu32.b,$Vv32.b)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; @@ -30200,7 +31055,7 @@ def V6_vdealb4w_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vdealb4w($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30211,7 +31066,7 @@ def V6_vdealb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vdealb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30222,7 +31077,7 @@ def V6_vdealh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.h = vdeal($Vu32.h)", -tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; @@ -30234,7 +31089,7 @@ def V6_vdealh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vdealh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30245,7 +31100,7 @@ def V6_vdealvdd : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)", -tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> { +tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; @@ -30257,7 +31112,7 @@ def V6_vdelta : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vdelta($Vu32,$Vv32)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; @@ -30269,7 +31124,7 @@ def V6_vdmpybus : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; @@ -30281,7 +31136,7 @@ def V6_vdmpybus_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { +tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001000; @@ -30295,7 +31150,7 @@ def V6_vdmpybus_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -30308,7 +31163,7 @@ def V6_vdmpybus_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30319,7 +31174,7 @@ def V6_vdmpybus_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; @@ -30331,7 +31186,7 @@ def V6_vdmpybus_dv_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001000; @@ -30345,7 +31200,7 @@ def V6_vdmpybus_dv_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vdmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -30358,7 +31213,7 @@ def V6_vdmpybus_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vdmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30369,7 +31224,7 @@ def V6_vdmpyhb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vu32.h,$Rt32.b)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; @@ -30381,7 +31236,7 @@ def V6_vdmpyhb_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vu32.h,$Rt32.b)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { +tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001000; @@ -30395,7 +31250,7 @@ def V6_vdmpyhb_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpyhb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -30408,7 +31263,7 @@ def V6_vdmpyhb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpyhb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30419,7 +31274,7 @@ def V6_vdmpyhb_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; @@ -30431,7 +31286,7 @@ def V6_vdmpyhb_dv_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001001; @@ -30445,7 +31300,7 @@ def V6_vdmpyhb_dv_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vdmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -30458,7 +31313,7 @@ def V6_vdmpyhb_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vdmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30469,7 +31324,7 @@ def V6_vdmpyhisat : HInst< (outs HvxVR:$Vd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; @@ -30481,7 +31336,7 @@ def V6_vdmpyhisat_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001001; @@ -30495,7 +31350,7 @@ def V6_vdmpyhisat_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vx32 += vdmpyh($Vuu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -30508,7 +31363,7 @@ def V6_vdmpyhisat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vd32 = vdmpyh($Vuu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30519,7 +31374,7 @@ def V6_vdmpyhsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; @@ -30531,7 +31386,7 @@ def V6_vdmpyhsat_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001001; @@ -30545,7 +31400,7 @@ def V6_vdmpyhsat_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpyh($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -30558,7 +31413,7 @@ def V6_vdmpyhsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpyh($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30569,7 +31424,7 @@ def V6_vdmpyhsuisat : HInst< (outs HvxVR:$Vd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_0e41fa, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; @@ -30581,7 +31436,7 @@ def V6_vdmpyhsuisat_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_cc857d, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001001; @@ -30595,7 +31450,7 @@ def V6_vdmpyhsuisat_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -30608,7 +31463,7 @@ def V6_vdmpyhsuisat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30619,7 +31474,7 @@ def V6_vdmpyhsusat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; @@ -30631,7 +31486,7 @@ def V6_vdmpyhsusat_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001001; @@ -30645,7 +31500,7 @@ def V6_vdmpyhsusat_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -30658,7 +31513,7 @@ def V6_vdmpyhsusat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30669,7 +31524,7 @@ def V6_vdmpyhvsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; @@ -30681,7 +31536,7 @@ def V6_vdmpyhvsat_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100000; @@ -30695,7 +31550,7 @@ def V6_vdmpyhvsat_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vdmpyh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -30708,7 +31563,7 @@ def V6_vdmpyhvsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vdmpyh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30719,7 +31574,7 @@ def V6_vdsaduh : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; @@ -30731,7 +31586,7 @@ def V6_vdsaduh_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001011; @@ -30745,7 +31600,7 @@ def V6_vdsaduh_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vdsaduh($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -30758,7 +31613,7 @@ def V6_vdsaduh_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vdsaduh($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -30769,7 +31624,7 @@ def V6_veqb : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; @@ -30781,12 +31636,10 @@ def V6_veqb_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -30794,12 +31647,10 @@ def V6_veqb_or : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; @@ -30808,12 +31659,10 @@ def V6_veqb_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -30821,7 +31670,7 @@ def V6_veqh : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; @@ -30833,12 +31682,10 @@ def V6_veqh_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -30846,12 +31693,10 @@ def V6_veqh_or : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b010001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; @@ -30860,12 +31705,10 @@ def V6_veqh_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -30873,7 +31716,7 @@ def V6_veqw : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; @@ -30885,12 +31728,10 @@ def V6_veqw_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -30898,12 +31739,10 @@ def V6_veqw_or : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b010010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; @@ -30912,20 +31751,114 @@ def V6_veqw_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgathermh : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), +"vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h", +tc_66bb62ea, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> { +let Inst{12-5} = 0b00001000; +let Inst{31-21} = 0b00101111000; let hasNewValue = 1; let opNewValue = 0; +let accessSize = HalfWordAccess; +let isCVLoad = 1; +let hasTmpDst = 1; +let mayLoad = 1; +let Defs = [VTMP]; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgathermhq : HInst< +(outs), +(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), +"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h", +tc_63e3d94c, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> { +let Inst{12-7} = 0b001010; +let Inst{31-21} = 0b00101111000; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let isCVLoad = 1; +let hasTmpDst = 1; +let mayLoad = 1; +let Defs = [VTMP]; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgathermhw : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32), +"vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h", +tc_bfe309d5, TypeCVI_GATHER>, Enc_28dcbb, Requires<[UseHVXV65]> { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b00101111000; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let isCVLoad = 1; +let hasTmpDst = 1; +let mayLoad = 1; +let Defs = [VTMP]; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgathermhwq : HInst< +(outs), +(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32), +"if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h", +tc_98733e9d, TypeCVI_GATHER>, Enc_4e4a80, Requires<[UseHVXV65]> { +let Inst{12-7} = 0b001100; +let Inst{31-21} = 0b00101111000; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let isCVLoad = 1; +let hasTmpDst = 1; +let mayLoad = 1; +let Defs = [VTMP]; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgathermw : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), +"vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w", +tc_66bb62ea, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101111000; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = WordAccess; +let isCVLoad = 1; +let hasTmpDst = 1; +let mayLoad = 1; +let Defs = [VTMP]; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgathermwq : HInst< +(outs), +(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), +"if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w", +tc_63e3d94c, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> { +let Inst{12-7} = 0b001000; +let Inst{31-21} = 0b00101111000; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = WordAccess; +let isCVLoad = 1; +let hasTmpDst = 1; +let mayLoad = 1; +let Defs = [VTMP]; let DecoderNamespace = "EXT_mmvec"; -let Constraints = "$Qx4 = $Qx4in"; } def V6_vgtb : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; @@ -30937,12 +31870,10 @@ def V6_vgtb_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -30950,12 +31881,10 @@ def V6_vgtb_or : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b010100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; @@ -30964,12 +31893,10 @@ def V6_vgtb_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -30977,7 +31904,7 @@ def V6_vgth : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; @@ -30989,12 +31916,10 @@ def V6_vgth_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31002,12 +31927,10 @@ def V6_vgth_or : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b010101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; @@ -31016,12 +31939,10 @@ def V6_vgth_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31029,7 +31950,7 @@ def V6_vgtub : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; @@ -31041,12 +31962,10 @@ def V6_vgtub_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31054,12 +31973,10 @@ def V6_vgtub_or : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; @@ -31068,12 +31985,10 @@ def V6_vgtub_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31081,7 +31996,7 @@ def V6_vgtuh : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; @@ -31093,12 +32008,10 @@ def V6_vgtuh_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31106,12 +32019,10 @@ def V6_vgtuh_or : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b011001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; @@ -31120,12 +32031,10 @@ def V6_vgtuh_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b101001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31133,7 +32042,7 @@ def V6_vgtuw : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; @@ -31145,12 +32054,10 @@ def V6_vgtuw_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31158,12 +32065,10 @@ def V6_vgtuw_or : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b011010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; @@ -31172,12 +32077,10 @@ def V6_vgtuw_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b101010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31185,7 +32088,7 @@ def V6_vgtw : HInst< (outs HvxQR:$Qd4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_95441f, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; @@ -31197,12 +32100,10 @@ def V6_vgtw_and : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31210,12 +32111,10 @@ def V6_vgtw_or : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b010110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let isAccumulator = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; @@ -31224,12 +32123,10 @@ def V6_vgtw_xor : HInst< (outs HvxQR:$Qx4), (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)", -tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; -let hasNewValue = 1; -let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31237,7 +32134,7 @@ def V6_vhist : HInst< (outs), (ins), "vhist", -tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV60T,UseHVX]> { +tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> { let Inst{13-0} = 0b10000010000000; let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; @@ -31246,7 +32143,7 @@ def V6_vhistq : HInst< (outs), (ins HvxQR:$Qv4), "vhist($Qv4)", -tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV60T,UseHVX]> { +tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> { let Inst{13-0} = 0b10000010000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; @@ -31256,7 +32153,7 @@ def V6_vinsertwr : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, IntRegs:$Rt32), "$Vx32.w = vinsert($Rt32)", -tc_e231aa4f, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[HasV60T,UseHVX]> { +tc_e231aa4f, TypeCVI_VX_LATE>, Enc_569cfe, Requires<[UseHVXV60]> { let Inst{13-5} = 0b100000001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; @@ -31268,7 +32165,7 @@ def V6_vlalignb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32 = vlalign($Vu32,$Vv32,$Rt8)", -tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> { +tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; @@ -31280,7 +32177,7 @@ def V6_vlalignbi : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vd32 = vlalign($Vu32,$Vv32,#$Ii)", -tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV60T,UseHVX]> { +tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV60]> { let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110011; let hasNewValue = 1; @@ -31291,7 +32188,7 @@ def V6_vlsrb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.ub = vlsr($Vu32.ub,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV62T,UseHVX]> { +tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV62]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; @@ -31303,7 +32200,7 @@ def V6_vlsrh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.uh = vlsr($Vu32.uh,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; @@ -31315,7 +32212,7 @@ def V6_vlsrh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vlsrh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31326,7 +32223,7 @@ def V6_vlsrhv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vlsr($Vu32.h,$Vv32.h)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; @@ -31338,7 +32235,7 @@ def V6_vlsrhv_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vlsrh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31349,7 +32246,7 @@ def V6_vlsrw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.uw = vlsr($Vu32.uw,$Rt32)", -tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_41f4b64e, TypeCVI_VS>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; @@ -31361,7 +32258,7 @@ def V6_vlsrw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vlsrw($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31372,7 +32269,7 @@ def V6_vlsrwv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vlsr($Vu32.w,$Vv32.w)", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; @@ -31384,18 +32281,30 @@ def V6_vlsrwv_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vlsrw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } +def V6_vlut4 : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vd32.h = vlut4($Vu32.uh,$Rtt32.h)", +tc_fa99dc24, TypeCVI_VX_DV>, Enc_263841, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} def V6_vlutvvb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)", -tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV60T,UseHVX]> { +tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; @@ -31407,7 +32316,7 @@ def V6_vlutvvb_nm : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch", -tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[HasV62T,UseHVX]> { +tc_c4b515c5, TypeCVI_VP>, Enc_a30110, Requires<[UseHVXV62]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; @@ -31419,7 +32328,7 @@ def V6_vlutvvb_oracc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)", -tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_245865, Requires<[HasV60T,UseHVX]> { +tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_245865, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; @@ -31433,7 +32342,7 @@ def V6_vlutvvb_oracci : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)", -tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_cd4705, Requires<[HasV62T,UseHVX]> { +tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_cd4705, Requires<[UseHVXV62]> { let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; @@ -31446,7 +32355,7 @@ def V6_vlutvvbi : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)", -tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[HasV62T,UseHVX]> { +tc_c4b515c5, TypeCVI_VP>, Enc_0b2e5b, Requires<[UseHVXV62]> { let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110001; let hasNewValue = 1; @@ -31457,7 +32366,7 @@ def V6_vlutvwh : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)", -tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> { +tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; @@ -31469,7 +32378,7 @@ def V6_vlutvwh_nm : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch", -tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV62T,UseHVX]> { +tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV62]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; @@ -31481,7 +32390,7 @@ def V6_vlutvwh_oracc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)", -tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_7b523d, Requires<[HasV60T,UseHVX]> { +tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_7b523d, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; @@ -31495,7 +32404,7 @@ def V6_vlutvwh_oracci : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)", -tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_1178da, Requires<[HasV62T,UseHVX]> { +tc_cbf6d1dc, TypeCVI_VP_VS>, Enc_1178da, Requires<[UseHVXV62]> { let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; @@ -31508,7 +32417,7 @@ def V6_vlutvwhi : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, u3_0Imm:$Ii), "$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)", -tc_4e2a5159, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[HasV62T,UseHVX]> { +tc_4e2a5159, TypeCVI_VP_VS>, Enc_4b39e4, Requires<[UseHVXV62]> { let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110011; let hasNewValue = 1; @@ -31519,7 +32428,7 @@ def V6_vmaxb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vmax($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; @@ -31531,7 +32440,7 @@ def V6_vmaxb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31542,7 +32451,7 @@ def V6_vmaxh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmax($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; @@ -31554,7 +32463,7 @@ def V6_vmaxh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31565,7 +32474,7 @@ def V6_vmaxub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; @@ -31577,7 +32486,7 @@ def V6_vmaxub_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31588,7 +32497,7 @@ def V6_vmaxuh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; @@ -31600,7 +32509,7 @@ def V6_vmaxuh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31611,7 +32520,7 @@ def V6_vmaxw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmax($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; @@ -31623,7 +32532,7 @@ def V6_vmaxw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmaxw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31634,7 +32543,7 @@ def V6_vminb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vmin($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; @@ -31646,7 +32555,7 @@ def V6_vminb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31657,7 +32566,7 @@ def V6_vminh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmin($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; @@ -31669,7 +32578,7 @@ def V6_vminh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31680,7 +32589,7 @@ def V6_vminub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; @@ -31692,7 +32601,7 @@ def V6_vminub_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31703,7 +32612,7 @@ def V6_vminuh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; @@ -31715,7 +32624,7 @@ def V6_vminuh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31726,7 +32635,7 @@ def V6_vminw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmin($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; @@ -31738,7 +32647,7 @@ def V6_vminw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vminw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31749,7 +32658,7 @@ def V6_vmpabus : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; @@ -31761,7 +32670,7 @@ def V6_vmpabus_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001001; @@ -31775,7 +32684,7 @@ def V6_vmpabus_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vmpabus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -31788,7 +32697,7 @@ def V6_vmpabus_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vmpabus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31799,7 +32708,7 @@ def V6_vmpabusv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; @@ -31811,7 +32720,57 @@ def V6_vmpabusv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vmpabus($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabuu : HInst< +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.ub)", +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabuu_acc : HInst< +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.ub)", +tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpabuu_acc_alt : HInst< +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vmpabuu($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpabuu_alt : HInst< +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vmpabuu($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31822,7 +32781,7 @@ def V6_vmpabuuv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; @@ -31834,7 +32793,7 @@ def V6_vmpabuuv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vmpabuu($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31845,7 +32804,7 @@ def V6_vmpahb : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; @@ -31857,7 +32816,7 @@ def V6_vmpahb_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001001; @@ -31871,7 +32830,7 @@ def V6_vmpahb_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vmpahb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -31884,18 +32843,31 @@ def V6_vmpahb_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vmpahb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } +def V6_vmpahhsat : HInst< +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vx32.h = vmpa($Vx32in.h,$Vu32.h,$Rtt32.h):sat", +tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} def V6_vmpauhb : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV62T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV62]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; @@ -31907,7 +32879,7 @@ def V6_vmpauhb_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV62T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV62]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001100; @@ -31921,7 +32893,7 @@ def V6_vmpauhb_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vmpauhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -31934,18 +32906,44 @@ def V6_vmpauhb_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vmpauhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } +def V6_vmpauhuhsat : HInst< +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vx32.h = vmpa($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat", +tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpsuhuhsat : HInst< +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vx32.h = vmps($Vx32in.h,$Vu32.uh,$Rtt32.uh):sat", +tc_7474003e, TypeCVI_VX_DV>, Enc_310ba1, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} def V6_vmpybus : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; @@ -31957,7 +32955,7 @@ def V6_vmpybus_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001001; @@ -31971,7 +32969,7 @@ def V6_vmpybus_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -31984,7 +32982,7 @@ def V6_vmpybus_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -31995,7 +32993,7 @@ def V6_vmpybusv : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; @@ -32007,7 +33005,7 @@ def V6_vmpybusv_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100000; @@ -32021,7 +33019,7 @@ def V6_vmpybusv_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32034,7 +33032,7 @@ def V6_vmpybusv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32045,7 +33043,7 @@ def V6_vmpybv : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vmpy($Vu32.b,$Vv32.b)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; @@ -32057,7 +33055,7 @@ def V6_vmpybv_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.h += vmpy($Vu32.b,$Vv32.b)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100000; @@ -32071,7 +33069,7 @@ def V6_vmpybv_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32084,7 +33082,7 @@ def V6_vmpybv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32095,7 +33093,7 @@ def V6_vmpyewuh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpye($Vu32.w,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; @@ -32107,7 +33105,7 @@ def V6_vmpyewuh_64 : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpye($Vu32.w,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV62T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV62]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; @@ -32119,7 +33117,7 @@ def V6_vmpyewuh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyewuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32130,7 +33128,7 @@ def V6_vmpyh : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.w = vmpy($Vu32.h,$Rt32.h)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; @@ -32138,11 +33136,38 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } +def V6_vmpyh_acc : HInst< +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), +"$Vxx32.w += vmpy($Vu32.h,$Rt32.h)", +tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyh_acc_alt : HInst< +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} def V6_vmpyh_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpyh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32153,7 +33178,7 @@ def V6_vmpyhsat_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001010; @@ -32167,7 +33192,7 @@ def V6_vmpyhsat_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpyh($Vu32,$Rt32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32180,7 +33205,7 @@ def V6_vmpyhsrs : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; @@ -32192,7 +33217,7 @@ def V6_vmpyhsrs_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32203,7 +33228,7 @@ def V6_vmpyhss : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; @@ -32215,7 +33240,7 @@ def V6_vmpyhss_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32226,7 +33251,7 @@ def V6_vmpyhus : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; @@ -32238,7 +33263,7 @@ def V6_vmpyhus_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100001; @@ -32252,7 +33277,7 @@ def V6_vmpyhus_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyhus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32265,7 +33290,7 @@ def V6_vmpyhus_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyhus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32276,7 +33301,7 @@ def V6_vmpyhv : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vmpy($Vu32.h,$Vv32.h)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; @@ -32288,7 +33313,7 @@ def V6_vmpyhv_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.w += vmpy($Vu32.h,$Vv32.h)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100000; @@ -32302,7 +33327,7 @@ def V6_vmpyhv_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32315,7 +33340,7 @@ def V6_vmpyhv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32326,7 +33351,7 @@ def V6_vmpyhvsrs : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; @@ -32338,7 +33363,7 @@ def V6_vmpyhvsrs_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32349,7 +33374,7 @@ def V6_vmpyieoh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; @@ -32361,7 +33386,7 @@ def V6_vmpyiewh_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyie($Vu32.w,$Vv32.h)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100010; @@ -32375,7 +33400,7 @@ def V6_vmpyiewh_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyiewh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32388,7 +33413,7 @@ def V6_vmpyiewuh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; @@ -32400,7 +33425,7 @@ def V6_vmpyiewuh_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100001; @@ -32414,7 +33439,7 @@ def V6_vmpyiewuh_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyiewuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32427,7 +33452,7 @@ def V6_vmpyiewuh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyiewuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32438,7 +33463,7 @@ def V6_vmpyih : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vmpyi($Vu32.h,$Vv32.h)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; @@ -32450,7 +33475,7 @@ def V6_vmpyih_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.h += vmpyi($Vu32.h,$Vv32.h)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100001; @@ -32464,7 +33489,7 @@ def V6_vmpyih_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyih($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32477,7 +33502,7 @@ def V6_vmpyih_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyih($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32488,7 +33513,7 @@ def V6_vmpyihb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.h = vmpyi($Vu32.h,$Rt32.b)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; @@ -32500,7 +33525,7 @@ def V6_vmpyihb_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.h += vmpyi($Vu32.h,$Rt32.b)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { +tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001011; @@ -32514,7 +33539,7 @@ def V6_vmpyihb_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyihb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32527,7 +33552,7 @@ def V6_vmpyihb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyihb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32538,7 +33563,7 @@ def V6_vmpyiowh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyio($Vu32.w,$Vv32.h)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; @@ -32550,7 +33575,7 @@ def V6_vmpyiowh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyiowh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32561,7 +33586,7 @@ def V6_vmpyiwb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vmpyi($Vu32.w,$Rt32.b)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; @@ -32573,7 +33598,7 @@ def V6_vmpyiwb_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vmpyi($Vu32.w,$Rt32.b)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { +tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001010; @@ -32587,7 +33612,7 @@ def V6_vmpyiwb_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyiwb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32600,7 +33625,7 @@ def V6_vmpyiwb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyiwb($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32611,7 +33636,7 @@ def V6_vmpyiwh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vmpyi($Vu32.w,$Rt32.h)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; @@ -32623,7 +33648,7 @@ def V6_vmpyiwh_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vmpyi($Vu32.w,$Rt32.h)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_5138b3, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001010; @@ -32637,7 +33662,7 @@ def V6_vmpyiwh_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyiwh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32650,7 +33675,7 @@ def V6_vmpyiwh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyiwh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32661,7 +33686,7 @@ def V6_vmpyiwub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV62T,UseHVX]> { +tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV62]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; @@ -32673,7 +33698,7 @@ def V6_vmpyiwub_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV62T,UseHVX]> { +tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV62]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001100; @@ -32687,7 +33712,7 @@ def V6_vmpyiwub_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vmpyiwub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32700,7 +33725,7 @@ def V6_vmpyiwub_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vmpyiwub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32711,7 +33736,7 @@ def V6_vmpyowh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; @@ -32723,7 +33748,7 @@ def V6_vmpyowh_64_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyo($Vu32.w,$Vv32.h)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV62T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV62]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100001; @@ -32737,7 +33762,7 @@ def V6_vmpyowh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32748,7 +33773,7 @@ def V6_vmpyowh_rnd : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; @@ -32760,7 +33785,7 @@ def V6_vmpyowh_rnd_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32771,7 +33796,7 @@ def V6_vmpyowh_rnd_sacc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100001; @@ -32785,7 +33810,7 @@ def V6_vmpyowh_rnd_sacc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32797,7 +33822,7 @@ def V6_vmpyowh_sacc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100001; @@ -32811,7 +33836,7 @@ def V6_vmpyowh_sacc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32823,7 +33848,7 @@ def V6_vmpyub : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001110; @@ -32835,7 +33860,7 @@ def V6_vmpyub_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001100; @@ -32849,7 +33874,7 @@ def V6_vmpyub_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32862,7 +33887,7 @@ def V6_vmpyub_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32873,7 +33898,7 @@ def V6_vmpyubv : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; @@ -32885,7 +33910,7 @@ def V6_vmpyubv_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100000; @@ -32899,7 +33924,7 @@ def V6_vmpyubv_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32912,7 +33937,7 @@ def V6_vmpyubv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -32923,7 +33948,7 @@ def V6_vmpyuh : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_01d3d0, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; @@ -32935,7 +33960,7 @@ def V6_vmpyuh_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_5e8512, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001010; @@ -32949,7 +33974,7 @@ def V6_vmpyuh_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vxx32 += vmpyuh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -32962,18 +33987,44 @@ def V6_vmpyuh_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vdd32 = vmpyuh($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } +def V6_vmpyuhe : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, IntRegs:$Rt32), +"$Vd32.uw = vmpye($Vu32.uh,$Rt32.uh)", +tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyuhe_acc : HInst< +(outs HvxVR:$Vx32), +(ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), +"$Vx32.uw += vmpye($Vu32.uh,$Rt32.uh)", +tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} def V6_vmpyuhv : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; @@ -32985,7 +34036,7 @@ def V6_vmpyuhv_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_3fc427, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100001; @@ -32999,7 +34050,7 @@ def V6_vmpyuhv_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vxx32 += vmpyuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -33012,7 +34063,7 @@ def V6_vmpyuhv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vmpyuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33023,7 +34074,7 @@ def V6_vmux : HInst< (outs HvxVR:$Vd32), (ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vmux($Qt4,$Vu32,$Vv32)", -tc_a3127e12, TypeCVI_VA>, Enc_31db33, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_31db33, Requires<[UseHVXV60]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110111; @@ -33031,11 +34082,34 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } +def V6_vnavgb : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32.b = vnavg($Vu32.b,$Vv32.b)", +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgb_alt : HInst< +(outs HvxVR:$Vd32), +(ins HvxVR:$Vu32, HvxVR:$Vv32), +"$Vd32 = vnavgb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} def V6_vnavgh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vnavg($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; @@ -33047,7 +34121,7 @@ def V6_vnavgh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vnavgh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33058,7 +34132,7 @@ def V6_vnavgub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; @@ -33070,7 +34144,7 @@ def V6_vnavgub_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vnavgub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33081,7 +34155,7 @@ def V6_vnavgw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vnavg($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; @@ -33093,7 +34167,7 @@ def V6_vnavgw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vnavgw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33104,7 +34178,7 @@ def V6_vnccombine : HInst< (outs HvxWR:$Vdd32), (ins PredRegs:$Ps4, HvxVR:$Vu32, HvxVR:$Vv32), "if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", -tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[HasV60T,UseHVX]> { +tc_2171ebae, TypeCVI_VA_DV>, Enc_8c2412, Requires<[UseHVXV60]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011010010; @@ -33118,7 +34192,7 @@ def V6_vncmov : HInst< (outs HvxVR:$Vd32), (ins PredRegs:$Ps4, HvxVR:$Vu32), "if (!$Ps4) $Vd32 = $Vu32", -tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[HasV60T,UseHVX]> { +tc_b06ab583, TypeCVI_VA>, Enc_770858, Requires<[UseHVXV60]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001101000100000; @@ -33132,7 +34206,7 @@ def V6_vnormamth : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.h = vnormamt($Vu32.h)", -tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000011; @@ -33144,7 +34218,7 @@ def V6_vnormamth_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vnormamth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33155,7 +34229,7 @@ def V6_vnormamtw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.w = vnormamt($Vu32.w)", -tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000011; @@ -33167,7 +34241,7 @@ def V6_vnormamtw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vnormamtw($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33178,7 +34252,7 @@ def V6_vnot : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vnot($Vu32)", -tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_71337255, TypeCVI_VA>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; @@ -33190,7 +34264,7 @@ def V6_vor : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vor($Vu32,$Vv32)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; @@ -33202,7 +34276,7 @@ def V6_vpackeb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vpacke($Vu32.h,$Vv32.h)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; @@ -33214,7 +34288,7 @@ def V6_vpackeb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackeb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33225,7 +34299,7 @@ def V6_vpackeh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vpacke($Vu32.w,$Vv32.w)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; @@ -33237,7 +34311,7 @@ def V6_vpackeh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackeh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33248,7 +34322,7 @@ def V6_vpackhb_sat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vpack($Vu32.h,$Vv32.h):sat", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; @@ -33260,7 +34334,7 @@ def V6_vpackhb_sat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackhb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33271,7 +34345,7 @@ def V6_vpackhub_sat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; @@ -33283,7 +34357,7 @@ def V6_vpackhub_sat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackhub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33294,7 +34368,7 @@ def V6_vpackob : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vpacko($Vu32.h,$Vv32.h)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; @@ -33306,7 +34380,7 @@ def V6_vpackob_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackob($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33317,7 +34391,7 @@ def V6_vpackoh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vpacko($Vu32.w,$Vv32.w)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; @@ -33329,7 +34403,7 @@ def V6_vpackoh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackoh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33340,7 +34414,7 @@ def V6_vpackwh_sat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vpack($Vu32.w,$Vv32.w):sat", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; @@ -33352,7 +34426,7 @@ def V6_vpackwh_sat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackwh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33363,7 +34437,7 @@ def V6_vpackwuh_sat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; @@ -33375,7 +34449,7 @@ def V6_vpackwuh_sat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vpackwuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33386,7 +34460,7 @@ def V6_vpopcounth : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.h = vpopcount($Vu32.h)", -tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_d2cb81ea, TypeCVI_VS>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; @@ -33398,18 +34472,54 @@ def V6_vpopcounth_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vpopcounth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } +def V6_vprefixqb : HInst< +(outs HvxVR:$Vd32), +(ins HvxQR:$Qv4), +"$Vd32.b = prefixsum($Qv4)", +tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> { +let Inst{13-5} = 0b100000010; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vprefixqh : HInst< +(outs HvxVR:$Vd32), +(ins HvxQR:$Qv4), +"$Vd32.h = prefixsum($Qv4)", +tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> { +let Inst{13-5} = 0b100001010; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vprefixqw : HInst< +(outs HvxVR:$Vd32), +(ins HvxQR:$Qv4), +"$Vd32.w = prefixsum($Qv4)", +tc_d2cb81ea, TypeCVI_VS>, Enc_6f83e7, Requires<[UseHVXV65]> { +let Inst{13-5} = 0b100010010; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} def V6_vrdelta : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrdelta($Vu32,$Vv32)", -tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_f3fc3f83, TypeCVI_VP>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; @@ -33417,11 +34527,61 @@ let hasNewValue = 1; let opNewValue = 0; let DecoderNamespace = "EXT_mmvec"; } +def V6_vrmpybub_rtt : HInst< +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)", +tc_a807365d, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybub_rtt_acc : HInst< +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)", +tc_ee927c0e, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpybub_rtt_acc_alt : HInst< +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpybub_rtt_alt : HInst< +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} def V6_vrmpybus : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; @@ -33433,7 +34593,7 @@ def V6_vrmpybus_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { +tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001000; @@ -33447,7 +34607,7 @@ def V6_vrmpybus_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vrmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -33460,7 +34620,7 @@ def V6_vrmpybus_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vrmpybus($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33471,7 +34631,7 @@ def V6_vrmpybusi : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", -tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> { +tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; @@ -33483,7 +34643,7 @@ def V6_vrmpybusi_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", -tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> { +tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> { let Inst{7-6} = 0b10; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001010; @@ -33497,7 +34657,7 @@ def V6_vrmpybusi_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -33510,7 +34670,7 @@ def V6_vrmpybusi_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33521,7 +34681,7 @@ def V6_vrmpybusv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; @@ -33533,7 +34693,7 @@ def V6_vrmpybusv_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100000; @@ -33547,7 +34707,7 @@ def V6_vrmpybusv_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vrmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -33560,7 +34720,7 @@ def V6_vrmpybusv_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrmpybus($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33571,7 +34731,7 @@ def V6_vrmpybv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vrmpy($Vu32.b,$Vv32.b)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; @@ -33583,7 +34743,7 @@ def V6_vrmpybv_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.w += vrmpy($Vu32.b,$Vv32.b)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100000; @@ -33597,7 +34757,7 @@ def V6_vrmpybv_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vrmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -33610,7 +34770,7 @@ def V6_vrmpybv_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrmpyb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33621,7 +34781,7 @@ def V6_vrmpyub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)", -tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_69b6dd20, TypeCVI_VX>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; @@ -33633,7 +34793,7 @@ def V6_vrmpyub_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)", -tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[HasV60T,UseHVX]> { +tc_d725e5b0, TypeCVI_VX>, Enc_5138b3, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001000; @@ -33647,7 +34807,7 @@ def V6_vrmpyub_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, IntRegs:$Rt32), "$Vx32 += vrmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -33660,7 +34820,57 @@ def V6_vrmpyub_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vrmpyub($Vu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyub_rtt : HInst< +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)", +tc_a807365d, TypeCVI_VS_VX>, Enc_cb785b, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyub_rtt_acc : HInst< +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)", +tc_ee927c0e, TypeCVI_VS_VX>, Enc_ad9bef, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpyub_rtt_acc_alt : HInst< +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpyub_rtt_alt : HInst< +(outs HvxWR:$Vdd32), +(ins HvxVR:$Vu32, DoubleRegs:$Rtt32), +"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33671,7 +34881,7 @@ def V6_vrmpyubi : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", -tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> { +tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> { let Inst{7-6} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; @@ -33683,7 +34893,7 @@ def V6_vrmpyubi_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", -tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> { +tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> { let Inst{7-6} = 0b11; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001011; @@ -33697,7 +34907,7 @@ def V6_vrmpyubi_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -33710,7 +34920,7 @@ def V6_vrmpyubi_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33721,7 +34931,7 @@ def V6_vrmpyubv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)", -tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_908a4c8c, TypeCVI_VX>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; @@ -33733,7 +34943,7 @@ def V6_vrmpyubv_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)", -tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[HasV60T,UseHVX]> { +tc_e172d86a, TypeCVI_VX_DV>, Enc_a7341a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100000; @@ -33747,7 +34957,7 @@ def V6_vrmpyubv_acc_alt : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxVR:$Vu32, HvxVR:$Vv32), "$Vx32 += vrmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -33760,7 +34970,7 @@ def V6_vrmpyubv_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrmpyub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33771,7 +34981,7 @@ def V6_vror : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, IntRegs:$Rt32), "$Vd32 = vror($Vu32,$Rt32)", -tc_bf142ae2, TypeCVI_VP>, Enc_b087ac, Requires<[HasV60T,UseHVX]> { +tc_bf142ae2, TypeCVI_VP>, Enc_b087ac, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; @@ -33783,7 +34993,7 @@ def V6_vroundhb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vround($Vu32.h,$Vv32.h):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; @@ -33795,7 +35005,7 @@ def V6_vroundhb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundhb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33806,7 +35016,7 @@ def V6_vroundhub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vround($Vu32.h,$Vv32.h):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; @@ -33818,7 +35028,7 @@ def V6_vroundhub_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundhub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33829,7 +35039,7 @@ def V6_vrounduhub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; @@ -33841,7 +35051,7 @@ def V6_vrounduhub_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrounduhub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33852,7 +35062,7 @@ def V6_vrounduwuh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; @@ -33864,7 +35074,7 @@ def V6_vrounduwuh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vrounduwuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33875,7 +35085,7 @@ def V6_vroundwh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vround($Vu32.w,$Vv32.w):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; @@ -33887,7 +35097,7 @@ def V6_vroundwh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundwh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33898,7 +35108,7 @@ def V6_vroundwuh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vround($Vu32.w,$Vv32.w):sat", -tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_45453b98, TypeCVI_VS>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; @@ -33910,7 +35120,7 @@ def V6_vroundwuh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vroundwuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33921,7 +35131,7 @@ def V6_vrsadubi : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", -tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[HasV60T,UseHVX]> { +tc_7e9f581b, TypeCVI_VX_DV>, Enc_2f2f04, Requires<[UseHVXV60]> { let Inst{7-6} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; @@ -33933,7 +35143,7 @@ def V6_vrsadubi_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", -tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[HasV60T,UseHVX]> { +tc_41f99e1c, TypeCVI_VX_DV>, Enc_d483b9, Requires<[UseHVXV60]> { let Inst{7-6} = 0b11; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001010; @@ -33947,7 +35157,7 @@ def V6_vrsadubi_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -33960,7 +35170,7 @@ def V6_vrsadubi_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), "$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33971,7 +35181,7 @@ def V6_vsathub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vsat($Vu32.h,$Vv32.h)", -tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; @@ -33983,7 +35193,7 @@ def V6_vsathub_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsathub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -33994,7 +35204,7 @@ def V6_vsatuwuh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; @@ -34006,7 +35216,7 @@ def V6_vsatuwuh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsatuwuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34017,7 +35227,7 @@ def V6_vsatwh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vsat($Vu32.w,$Vv32.w)", -tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_9b9642a1, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; @@ -34029,7 +35239,7 @@ def V6_vsatwh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsatwh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34040,7 +35250,7 @@ def V6_vsb : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32.h = vsxt($Vu32.b)", -tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { +tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; @@ -34052,18 +35262,204 @@ def V6_vsb_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32 = vsxtb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } +def V6_vscattermh : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32", +tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101111001; +let accessSize = HalfWordAccess; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermh_add : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vv32.h).h += $Vw32", +tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b101; +let Inst{31-21} = 0b00101111001; +let accessSize = HalfWordAccess; +let isAccumulator = 1; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermh_add_alt : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermh_alt : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermhq : HInst< +(outs), +(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h).h = $Vw32", +tc_df54ad52, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> { +let Inst{7-7} = 0b1; +let Inst{31-21} = 0b00101111100; +let accessSize = HalfWordAccess; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermhq_alt : HInst< +(outs), +(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermhw : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32", +tc_ec58f88a, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b00101111001; +let accessSize = HalfWordAccess; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermhw_add : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vvv32.w).h += $Vw32", +tc_ec58f88a, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b00101111001; +let accessSize = HalfWordAccess; +let isAccumulator = 1; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermhwq : HInst< +(outs), +(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), +"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w).h = $Vw32", +tc_94f43c04, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> { +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b00101111101; +let accessSize = HalfWordAccess; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermw : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32", +tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101111001; +let accessSize = WordAccess; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermw_add : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vv32.w).w += $Vw32", +tc_4f190ba3, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { +let Inst{7-5} = 0b100; +let Inst{31-21} = 0b00101111001; +let accessSize = WordAccess; +let isAccumulator = 1; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermw_add_alt : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermw_alt : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermwh_add_alt : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermwh_alt : HInst< +(outs), +(ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), +"vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermwhq_alt : HInst< +(outs), +(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), +"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermwq : HInst< +(outs), +(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w).w = $Vw32", +tc_df54ad52, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> { +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b00101111100; +let accessSize = WordAccess; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vscattermwq_alt : HInst< +(outs), +(ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), +"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} def V6_vsh : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32.w = vsxt($Vu32.h)", -tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { +tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; @@ -34075,7 +35471,7 @@ def V6_vsh_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32 = vsxth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34086,7 +35482,7 @@ def V6_vshufeh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vshuffe($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; @@ -34098,7 +35494,7 @@ def V6_vshufeh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffeh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34109,7 +35505,7 @@ def V6_vshuff : HInst< (outs HvxVR:$Vy32, HvxVR:$Vx32), (ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), "vshuff($Vy32,$Vx32,$Rt32)", -tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[HasV60T,UseHVX]> { +tc_5c120602, TypeCVI_VP_VS>, Enc_989021, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001111; @@ -34124,7 +35520,7 @@ def V6_vshuffb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.b = vshuff($Vu32.b)", -tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; @@ -34136,7 +35532,7 @@ def V6_vshuffb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vshuffb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34147,7 +35543,7 @@ def V6_vshuffeb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vshuffe($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; @@ -34159,7 +35555,7 @@ def V6_vshuffeb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffeb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34170,7 +35566,7 @@ def V6_vshuffh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32.h = vshuff($Vu32.h)", -tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[HasV60T,UseHVX]> { +tc_e6299d16, TypeCVI_VP>, Enc_e7581c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; @@ -34182,7 +35578,7 @@ def V6_vshuffh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32), "$Vd32 = vshuffh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34193,7 +35589,7 @@ def V6_vshuffob : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vshuffo($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; @@ -34205,7 +35601,7 @@ def V6_vshuffob_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffob($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34216,7 +35612,7 @@ def V6_vshuffvdd : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), "$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)", -tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[HasV60T,UseHVX]> { +tc_4e2a5159, TypeCVI_VP_VS>, Enc_24a7dc, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; @@ -34228,7 +35624,7 @@ def V6_vshufoeb : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; @@ -34240,7 +35636,7 @@ def V6_vshufoeb_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vshuffoeb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34251,7 +35647,7 @@ def V6_vshufoeh : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; @@ -34263,7 +35659,7 @@ def V6_vshufoeh_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vshuffoeh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34274,7 +35670,7 @@ def V6_vshufoh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vshuffo($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; @@ -34286,7 +35682,7 @@ def V6_vshufoh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vshuffoh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34297,7 +35693,7 @@ def V6_vsubb : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vsub($Vu32.b,$Vv32.b)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; @@ -34309,7 +35705,7 @@ def V6_vsubb_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubb($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34320,7 +35716,7 @@ def V6_vsubb_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; @@ -34332,7 +35728,7 @@ def V6_vsubb_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubb($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34343,7 +35739,7 @@ def V6_vsubbnq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.b -= $Vu32.b", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000010; @@ -34357,7 +35753,7 @@ def V6_vsubbnq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.b) $Vx32.b -= $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34369,7 +35765,7 @@ def V6_vsubbq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.b -= $Vu32.b", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000001; @@ -34383,7 +35779,7 @@ def V6_vsubbq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.b) $Vx32.b -= $Vu32.b", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34395,7 +35791,7 @@ def V6_vsubbsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.b = vsub($Vu32.b,$Vv32.b):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; @@ -34407,7 +35803,7 @@ def V6_vsubbsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubb($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34418,7 +35814,7 @@ def V6_vsubbsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; @@ -34430,7 +35826,7 @@ def V6_vsubbsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubb($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34441,14 +35837,12 @@ def V6_vsubcarry : HInst< (outs HvxVR:$Vd32, HvxQR:$Qx4), (ins HvxVR:$Vu32, HvxVR:$Vv32, HvxQR:$Qx4in), "$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry", -tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[HasV62T,UseHVX]> { +tc_5a9fc4ec, TypeCVI_VA>, Enc_b43b67, Requires<[UseHVXV62]> { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; -let hasNewValue2 = 1; -let opNewValue2 = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -34456,7 +35850,7 @@ def V6_vsubh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vsub($Vu32.h,$Vv32.h)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; @@ -34468,7 +35862,7 @@ def V6_vsubh_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34479,7 +35873,7 @@ def V6_vsubh_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; @@ -34491,7 +35885,7 @@ def V6_vsubh_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubh($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34502,7 +35896,7 @@ def V6_vsubhnq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.h -= $Vu32.h", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000010; @@ -34516,7 +35910,7 @@ def V6_vsubhnq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.h) $Vx32.h -= $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34528,7 +35922,7 @@ def V6_vsubhq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.h -= $Vu32.h", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000001; @@ -34542,7 +35936,7 @@ def V6_vsubhq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.h) $Vx32.h -= $Vu32.h", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34554,7 +35948,7 @@ def V6_vsubhsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vsub($Vu32.h,$Vv32.h):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; @@ -34566,7 +35960,7 @@ def V6_vsubhsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34577,7 +35971,7 @@ def V6_vsubhsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; @@ -34589,7 +35983,7 @@ def V6_vsubhsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34600,7 +35994,7 @@ def V6_vsubhw : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vsub($Vu32.h,$Vv32.h)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; @@ -34612,7 +36006,7 @@ def V6_vsubhw_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vsubh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34623,7 +36017,7 @@ def V6_vsububh : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; @@ -34635,7 +36029,7 @@ def V6_vsububh_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vsubub($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34646,7 +36040,7 @@ def V6_vsububsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; @@ -34658,7 +36052,7 @@ def V6_vsububsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubub($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34669,7 +36063,7 @@ def V6_vsububsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; @@ -34681,7 +36075,7 @@ def V6_vsububsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubub($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34692,7 +36086,7 @@ def V6_vsubububb_sat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; @@ -34704,7 +36098,7 @@ def V6_vsubuhsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; @@ -34716,7 +36110,7 @@ def V6_vsubuhsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubuh($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34727,7 +36121,7 @@ def V6_vsubuhsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; @@ -34739,7 +36133,7 @@ def V6_vsubuhsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34750,7 +36144,7 @@ def V6_vsubuhw : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)", -tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[HasV60T,UseHVX]> { +tc_eda67dcd, TypeCVI_VX_DV>, Enc_71bb9b, Requires<[UseHVXV60]> { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; @@ -34762,7 +36156,7 @@ def V6_vsubuhw_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vsubuh($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34773,7 +36167,7 @@ def V6_vsubuwsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV62T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV62]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; @@ -34785,7 +36179,7 @@ def V6_vsubuwsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubuw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34796,7 +36190,7 @@ def V6_vsubuwsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV62T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV62]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; @@ -34808,7 +36202,7 @@ def V6_vsubuwsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubuw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34819,7 +36213,7 @@ def V6_vsubw : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vsub($Vu32.w,$Vv32.w)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; @@ -34831,7 +36225,7 @@ def V6_vsubw_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubw($Vu32,$Vv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34842,7 +36236,7 @@ def V6_vsubw_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; @@ -34854,7 +36248,7 @@ def V6_vsubw_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubw($Vuu32,$Vvv32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34865,7 +36259,7 @@ def V6_vsubwnq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4) $Vx32.w -= $Vu32.w", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000010; @@ -34879,7 +36273,7 @@ def V6_vsubwnq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if (!$Qv4.w) $Vx32.w -= $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34891,7 +36285,7 @@ def V6_vsubwq : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4) $Vx32.w -= $Vu32.w", -tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[HasV60T,UseHVX]> { +tc_a3127e12, TypeCVI_VA>, Enc_a90628, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{21-16} = 0b000010; @@ -34905,7 +36299,7 @@ def V6_vsubwq_alt : HInst< (outs HvxVR:$Vx32), (ins HvxQR:$Qv4, HvxVR:$Vx32in, HvxVR:$Vu32), "if ($Qv4.w) $Vx32.w -= $Vu32.w", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34917,7 +36311,7 @@ def V6_vsubwsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w = vsub($Vu32.w,$Vv32.w):sat", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; @@ -34929,7 +36323,7 @@ def V6_vsubwsat_alt : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vsubw($Vu32,$Vv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34940,7 +36334,7 @@ def V6_vsubwsat_dv : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat", -tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[HasV60T,UseHVX]> { +tc_97c165b9, TypeCVI_VA_DV>, Enc_f8ecf9, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; @@ -34952,7 +36346,7 @@ def V6_vsubwsat_dv_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, HvxWR:$Vvv32), "$Vdd32 = vsubw($Vuu32,$Vvv32):sat", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -34963,7 +36357,7 @@ def V6_vswap : HInst< (outs HvxWR:$Vdd32), (ins HvxQR:$Qt4, HvxVR:$Vu32, HvxVR:$Vv32), "$Vdd32 = vswap($Qt4,$Vu32,$Vv32)", -tc_316c637c, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[HasV60T,UseHVX]> { +tc_316c637c, TypeCVI_VA_DV>, Enc_3dac0b, Requires<[UseHVXV60]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110101; @@ -34975,7 +36369,7 @@ def V6_vtmpyb : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; @@ -34987,7 +36381,7 @@ def V6_vtmpyb_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001000; @@ -35001,7 +36395,7 @@ def V6_vtmpyb_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vtmpyb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -35014,7 +36408,7 @@ def V6_vtmpyb_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vtmpyb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -35025,7 +36419,7 @@ def V6_vtmpybus : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; @@ -35037,7 +36431,7 @@ def V6_vtmpybus_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001000; @@ -35051,7 +36445,7 @@ def V6_vtmpybus_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vtmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -35064,7 +36458,7 @@ def V6_vtmpybus_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vtmpybus($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -35075,7 +36469,7 @@ def V6_vtmpyhb : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)", -tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[HasV60T,UseHVX]> { +tc_7c3f55c4, TypeCVI_VX_DV>, Enc_aad80c, Requires<[UseHVXV60]> { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; @@ -35087,7 +36481,7 @@ def V6_vtmpyhb_acc : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)", -tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[HasV60T,UseHVX]> { +tc_d98f4d63, TypeCVI_VX_DV>, Enc_d6990d, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001000; @@ -35101,7 +36495,7 @@ def V6_vtmpyhb_acc_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxWR:$Vuu32, IntRegs:$Rt32), "$Vxx32 += vtmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -35114,7 +36508,7 @@ def V6_vtmpyhb_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxWR:$Vuu32, IntRegs:$Rt32), "$Vdd32 = vtmpyhb($Vuu32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -35125,7 +36519,7 @@ def V6_vtran2x2_map : HInst< (outs HvxVR:$Vy32, HvxVR:$Vx32), (ins HvxVR:$Vy32in, HvxVR:$Vx32in, IntRegs:$Rt32), "vtrans2x2($Vy32,$Vx32,$Rt32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let hasNewValue2 = 1; @@ -35139,7 +36533,7 @@ def V6_vunpackb : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32.h = vunpack($Vu32.b)", -tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { +tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; @@ -35151,7 +36545,7 @@ def V6_vunpackb_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32 = vunpackb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -35162,7 +36556,7 @@ def V6_vunpackh : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32.w = vunpack($Vu32.h)", -tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { +tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; @@ -35174,7 +36568,7 @@ def V6_vunpackh_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32 = vunpackh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -35185,7 +36579,7 @@ def V6_vunpackob : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32), "$Vxx32.h |= vunpacko($Vu32.b)", -tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[HasV60T,UseHVX]> { +tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b1; let Inst{31-16} = 0b0001111000000000; @@ -35199,7 +36593,7 @@ def V6_vunpackob_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32), "$Vxx32 |= vunpackob($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -35211,7 +36605,7 @@ def V6_vunpackoh : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32), "$Vxx32.w |= vunpacko($Vu32.h)", -tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[HasV60T,UseHVX]> { +tc_72ad7b54, TypeCVI_VP_VS>, Enc_500cb0, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-16} = 0b0001111000000000; @@ -35225,7 +36619,7 @@ def V6_vunpackoh_alt : HInst< (outs HvxWR:$Vxx32), (ins HvxWR:$Vxx32in, HvxVR:$Vu32), "$Vxx32 |= vunpackoh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; @@ -35238,7 +36632,7 @@ def V6_vunpackub : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32.uh = vunpack($Vu32.ub)", -tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { +tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; @@ -35250,7 +36644,7 @@ def V6_vunpackub_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32 = vunpackub($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -35261,7 +36655,7 @@ def V6_vunpackuh : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32.uw = vunpack($Vu32.uh)", -tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { +tc_d7bea0ec, TypeCVI_VP_VS>, Enc_dd766a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; @@ -35273,7 +36667,7 @@ def V6_vunpackuh_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32 = vunpackuh($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -35284,7 +36678,7 @@ def V6_vwhist128 : HInst< (outs), (ins), "vwhist128", -tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> { +tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10010010000000; let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; @@ -35293,7 +36687,7 @@ def V6_vwhist128m : HInst< (outs), (ins u1_0Imm:$Ii), "vwhist128(#$Ii)", -tc_b77635b4, TypeCVI_HIST>, Enc_efaed8, Requires<[HasV62T,UseHVX]> { +tc_b77635b4, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> { let Inst{7-0} = 0b10000000; let Inst{13-9} = 0b10011; let Inst{31-16} = 0b0001111000000000; @@ -35303,7 +36697,7 @@ def V6_vwhist128q : HInst< (outs), (ins HvxQR:$Qv4), "vwhist128($Qv4)", -tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> { +tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10010010000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; @@ -35313,7 +36707,7 @@ def V6_vwhist128qm : HInst< (outs), (ins HvxQR:$Qv4, u1_0Imm:$Ii), "vwhist128($Qv4,#$Ii)", -tc_28978789, TypeCVI_HIST>, Enc_802dc0, Requires<[HasV62T,UseHVX]> { +tc_28978789, TypeCVI_HIST>, Enc_802dc0, Requires<[UseHVXV62]> { let Inst{7-0} = 0b10000000; let Inst{13-9} = 0b10011; let Inst{21-16} = 0b000010; @@ -35324,7 +36718,7 @@ def V6_vwhist256 : HInst< (outs), (ins), "vwhist256", -tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> { +tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001010000000; let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; @@ -35333,7 +36727,7 @@ def V6_vwhist256_sat : HInst< (outs), (ins), "vwhist256:sat", -tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[HasV62T,UseHVX]> { +tc_e5053c8f, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001110000000; let Inst{31-16} = 0b0001111000000000; let DecoderNamespace = "EXT_mmvec"; @@ -35342,7 +36736,7 @@ def V6_vwhist256q : HInst< (outs), (ins HvxQR:$Qv4), "vwhist256($Qv4)", -tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> { +tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001010000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; @@ -35352,7 +36746,7 @@ def V6_vwhist256q_sat : HInst< (outs), (ins HvxQR:$Qv4), "vwhist256($Qv4):sat", -tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[HasV62T,UseHVX]> { +tc_cedf314b, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001110000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; @@ -35362,7 +36756,7 @@ def V6_vxor : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32 = vxor($Vu32,$Vv32)", -tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[HasV60T,UseHVX]> { +tc_bbaf280e, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; @@ -35374,7 +36768,7 @@ def V6_vzb : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32.uh = vzxt($Vu32.ub)", -tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { +tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; @@ -35386,7 +36780,7 @@ def V6_vzb_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32 = vzxtb($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -35397,7 +36791,7 @@ def V6_vzh : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32.uw = vzxt($Vu32.uh)", -tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[HasV60T,UseHVX]> { +tc_644584f8, TypeCVI_VA_DV>, Enc_dd766a, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; @@ -35409,7 +36803,7 @@ def V6_vzh_alt : HInst< (outs HvxWR:$Vdd32), (ins HvxVR:$Vu32), "$Vdd32 = vzxth($Vu32)", -PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -35420,7 +36814,7 @@ def Y2_barrier : HInst< (outs), (ins), "barrier", -tc_ef2676fd, TypeST>, Enc_e3b0c4 { +tc_367f7f3d, TypeST>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b1010100000000000; let isSoloAX = 1; @@ -35430,7 +36824,7 @@ def Y2_break : HInst< (outs), (ins), "brkpt", -tc_bcf0e36e, TypeCR>, Enc_e3b0c4 { +tc_4ca572d4, TypeCR>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b0110110000100000; let isSolo = 1; @@ -35439,27 +36833,27 @@ def Y2_dccleana : HInst< (outs), (ins IntRegs:$Rs32), "dccleana($Rs32)", -tc_30665cb0, TypeST>, Enc_ecbcc8 { +tc_00e7c26e, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000000; -let isSoloAin1 = 1; +let isRestrictSlot1AOK = 1; let hasSideEffects = 1; } def Y2_dccleaninva : HInst< (outs), (ins IntRegs:$Rs32), "dccleaninva($Rs32)", -tc_30665cb0, TypeST>, Enc_ecbcc8 { +tc_00e7c26e, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000010; -let isSoloAin1 = 1; +let isRestrictSlot1AOK = 1; let hasSideEffects = 1; } def Y2_dcfetch : HInst< (outs), (ins IntRegs:$Rs32), "dcfetch($Rs32)", -tc_34e882a4, TypeMAPPING> { +tc_3da80ba5, TypeMAPPING> { let hasSideEffects = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -35468,38 +36862,39 @@ def Y2_dcfetchbo : HInst< (outs), (ins IntRegs:$Rs32, u11_3Imm:$Ii), "dcfetch($Rs32+#$Ii)", -tc_ef0ebaaa, TypeLD>, Enc_2d829e { +tc_4d9914c9, TypeLD>, Enc_2d829e { let Inst{13-11} = 0b000; let Inst{31-21} = 0b10010100000; let addrMode = BaseImmOffset; +let isRestrictNoSlot1Store = 1; let hasSideEffects = 1; } def Y2_dcinva : HInst< (outs), (ins IntRegs:$Rs32), "dcinva($Rs32)", -tc_30665cb0, TypeST>, Enc_ecbcc8 { +tc_00e7c26e, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000001; -let isSoloAin1 = 1; +let isRestrictSlot1AOK = 1; let hasSideEffects = 1; } def Y2_dczeroa : HInst< (outs), (ins IntRegs:$Rs32), "dczeroa($Rs32)", -tc_30665cb0, TypeST>, Enc_ecbcc8 { +tc_00e7c26e, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000110; -let isSoloAin1 = 1; -let hasSideEffects = 1; +let isRestrictSlot1AOK = 1; let mayStore = 1; +let hasSideEffects = 1; } def Y2_icinva : HInst< (outs), (ins IntRegs:$Rs32), "icinva($Rs32)", -tc_049dfb74, TypeJ>, Enc_ecbcc8 { +tc_999d32db, TypeJ>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010110110; let isSolo = 1; @@ -35508,7 +36903,7 @@ def Y2_isync : HInst< (outs), (ins), "isync", -tc_d267fa19, TypeJ>, Enc_e3b0c4 { +tc_b13761ae, TypeJ>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000010; let Inst{31-16} = 0b0101011111000000; let isSolo = 1; @@ -35517,7 +36912,7 @@ def Y2_syncht : HInst< (outs), (ins), "syncht", -tc_ef2676fd, TypeST>, Enc_e3b0c4 { +tc_367f7f3d, TypeST>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b1010100001000000; let isSolo = 1; @@ -35526,7 +36921,7 @@ def Y4_l2fetch : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "l2fetch($Rs32,$Rt32)", -tc_f4608adc, TypeST>, Enc_ca3887 { +tc_daa058fa, TypeST>, Enc_ca3887 { let Inst{7-0} = 0b00000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100110000; @@ -35538,7 +36933,7 @@ def Y4_trace : HInst< (outs), (ins IntRegs:$Rs32), "trace($Rs32)", -tc_4997da4a, TypeCR>, Enc_ecbcc8 { +tc_c82dc1ff, TypeCR>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01100010010; let isSoloAX = 1; @@ -35547,7 +36942,7 @@ def Y5_l2fetch : HInst< (outs), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "l2fetch($Rs32,$Rtt32)", -tc_f4608adc, TypeST>, Enc_e6abcf, Requires<[HasV5T]> { +tc_daa058fa, TypeST>, Enc_e6abcf, Requires<[HasV5T]> { let Inst{7-0} = 0b00000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100110100; @@ -35559,7 +36954,7 @@ def dep_A2_addsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add($Rs32,$Rt32):sat:deprecated", -tc_47ab9233, TypeALU64>, Enc_5ab2be { +tc_b44c6e2a, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101100; @@ -35572,7 +36967,7 @@ def dep_A2_subsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32,$Rs32):sat:deprecated", -tc_47ab9233, TypeALU64>, Enc_bd6011 { +tc_b44c6e2a, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101100; @@ -35585,7 +36980,7 @@ def dep_S2_packhl : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = packhl($Rs32,$Rt32):deprecated", -tc_9c18c9a5, TypeALU64>, Enc_be32a5 { +tc_540fdfbc, TypeALU64>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010100000; diff --git a/llvm/lib/Target/Hexagon/HexagonDepMappings.td b/llvm/lib/Target/Hexagon/HexagonDepMappings.td index ebef4f10acb..7a156c39da9 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepMappings.td +++ b/llvm/lib/Target/Hexagon/HexagonDepMappings.td @@ -1,4 +1,4 @@ -//===--- HexagonDepMappings.td --------------------------------------------===// +//===- HexagonDepMappings.td ----------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,397 +6,470 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + -def A2_negAlias : InstAlias<"$Rd32=neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>; -def A2_notAlias : InstAlias<"$Rd32=not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>; -def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32=$Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; -def A2_tfrfnewAlias : InstAlias<"if (!$Pu4.new) $Rd32=$Rs32", (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; -def A2_tfrtAlias : InstAlias<"if ($Pu4) $Rd32=$Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; -def A2_tfrtnewAlias : InstAlias<"if ($Pu4.new) $Rd32=$Rs32", (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; -def A2_vaddb_mapAlias : InstAlias<"$Rdd32=vaddb($Rss32,$Rtt32)", (A2_vaddub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>; -def A2_vsubb_mapAlias : InstAlias<"$Rdd32=vsubb($Rss32,$Rtt32)", (A2_vsubub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>; -def A2_zxtbAlias : InstAlias<"$Rd32=zxtb($Rs32)", (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255)>; -def C2_cmpltAlias : InstAlias<"$Pd4=cmp.lt($Rs32,$Rt32)", (C2_cmpgt PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>; -def C2_cmpltuAlias : InstAlias<"$Pd4=cmp.ltu($Rs32,$Rt32)", (C2_cmpgtu PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>; -def C2_pxfer_mapAlias : InstAlias<"$Pd4=$Ps4", (C2_or PredRegs:$Pd4, PredRegs:$Ps4, PredRegs:$Ps4)>; +def A2_negAlias : InstAlias<"$Rd32 = neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>; +def A2_notAlias : InstAlias<"$Rd32 = not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>; +def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32 = $Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_tfrfnewAlias : InstAlias<"if (!$Pu4.new) $Rd32 = $Rs32", (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_tfrtAlias : InstAlias<"if ($Pu4) $Rd32 = $Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_tfrtnewAlias : InstAlias<"if ($Pu4.new) $Rd32 = $Rs32", (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_vaddb_mapAlias : InstAlias<"$Rdd32 = vaddb($Rss32,$Rtt32)", (A2_vaddub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>; +def A2_vsubb_mapAlias : InstAlias<"$Rdd32 = vsubb($Rss32,$Rtt32)", (A2_vsubub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>; +def A2_zxtbAlias : InstAlias<"$Rd32 = zxtb($Rs32)", (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255)>; +def C2_cmpltAlias : InstAlias<"$Pd4 = cmp.lt($Rs32,$Rt32)", (C2_cmpgt PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>; +def C2_cmpltuAlias : InstAlias<"$Pd4 = cmp.ltu($Rs32,$Rt32)", (C2_cmpgtu PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>; +def C2_pxfer_mapAlias : InstAlias<"$Pd4 = $Ps4", (C2_or PredRegs:$Pd4, PredRegs:$Ps4, PredRegs:$Ps4)>; def J2_jumpf_nopred_mapAlias : InstAlias<"if (!$Pu4) jump $Ii", (J2_jumpf PredRegs:$Pu4, b30_2Imm:$Ii)>; def J2_jumprf_nopred_mapAlias : InstAlias<"if (!$Pu4) jumpr $Rs32", (J2_jumprf PredRegs:$Pu4, IntRegs:$Rs32)>; def J2_jumprt_nopred_mapAlias : InstAlias<"if ($Pu4) jumpr $Rs32", (J2_jumprt PredRegs:$Pu4, IntRegs:$Rs32)>; def J2_jumpt_nopred_mapAlias : InstAlias<"if ($Pu4) jump $Ii", (J2_jumpt PredRegs:$Pu4, b30_2Imm:$Ii)>; -def L2_loadalignb_zomapAlias : InstAlias<"$Ryy32=memb_fifo($Rs32)", (L2_loadalignb_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>; -def L2_loadalignh_zomapAlias : InstAlias<"$Ryy32=memh_fifo($Rs32)", (L2_loadalignh_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>; -def L2_loadbsw2_zomapAlias : InstAlias<"$Rd32=membh($Rs32)", (L2_loadbsw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; -def L2_loadbsw4_zomapAlias : InstAlias<"$Rdd32=membh($Rs32)", (L2_loadbsw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; -def L2_loadbzw2_zomapAlias : InstAlias<"$Rd32=memubh($Rs32)", (L2_loadbzw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; -def L2_loadbzw4_zomapAlias : InstAlias<"$Rdd32=memubh($Rs32)", (L2_loadbzw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; -def L2_loadrb_zomapAlias : InstAlias<"$Rd32=memb($Rs32)", (L2_loadrb_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; -def L2_loadrd_zomapAlias : InstAlias<"$Rdd32=memd($Rs32)", (L2_loadrd_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; -def L2_loadrh_zomapAlias : InstAlias<"$Rd32=memh($Rs32)", (L2_loadrh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; -def L2_loadri_zomapAlias : InstAlias<"$Rd32=memw($Rs32)", (L2_loadri_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; -def L2_loadrub_zomapAlias : InstAlias<"$Rd32=memub($Rs32)", (L2_loadrub_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; -def L2_loadruh_zomapAlias : InstAlias<"$Rd32=memuh($Rs32)", (L2_loadruh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; -def L2_ploadrbf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memb($Rs32)", (L2_ploadrbf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrbfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memb($Rs32)", (L2_ploadrbfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrbt_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memb($Rs32)", (L2_ploadrbt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrbtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memb($Rs32)", (L2_ploadrbtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrdf_zomapAlias : InstAlias<"if (!$Pt4) $Rdd32=memd($Rs32)", (L2_ploadrdf_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrdfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rdd32=memd($Rs32)", (L2_ploadrdfnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrdt_zomapAlias : InstAlias<"if ($Pt4) $Rdd32=memd($Rs32)", (L2_ploadrdt_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrdtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rdd32=memd($Rs32)", (L2_ploadrdtnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memh($Rs32)", (L2_ploadrhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memh($Rs32)", (L2_ploadrhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrht_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memh($Rs32)", (L2_ploadrht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memh($Rs32)", (L2_ploadrhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrif_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memw($Rs32)", (L2_ploadrif_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrifnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memw($Rs32)", (L2_ploadrifnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrit_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memw($Rs32)", (L2_ploadrit_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadritnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memw($Rs32)", (L2_ploadritnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrubf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memub($Rs32)", (L2_ploadrubf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrubfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memub($Rs32)", (L2_ploadrubfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrubt_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memub($Rs32)", (L2_ploadrubt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadrubtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memub($Rs32)", (L2_ploadrubtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadruhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memuh($Rs32)", (L2_ploadruhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadruhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memuh($Rs32)", (L2_ploadruhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadruht_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memuh($Rs32)", (L2_ploadruht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L2_ploadruhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memuh($Rs32)", (L2_ploadruhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; -def L4_add_memopb_zomapAlias : InstAlias<"memb($Rs32)+=$Rt32", (L4_add_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def L4_add_memoph_zomapAlias : InstAlias<"memh($Rs32)+=$Rt32", (L4_add_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def L4_add_memopw_zomapAlias : InstAlias<"memw($Rs32)+=$Rt32", (L4_add_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def L4_and_memopb_zomapAlias : InstAlias<"memb($Rs32)&=$Rt32", (L4_and_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def L4_and_memoph_zomapAlias : InstAlias<"memh($Rs32)&=$Rt32", (L4_and_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def L4_and_memopw_zomapAlias : InstAlias<"memw($Rs32)&=$Rt32", (L4_and_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def L4_iadd_memopb_zomapAlias : InstAlias<"memb($Rs32)+=#$II", (L4_iadd_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_iadd_memoph_zomapAlias : InstAlias<"memh($Rs32)+=#$II", (L4_iadd_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_iadd_memopw_zomapAlias : InstAlias<"memw($Rs32)+=#$II", (L4_iadd_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_iand_memopb_zomapAlias : InstAlias<"memb($Rs32)=clrbit(#$II)", (L4_iand_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_iand_memoph_zomapAlias : InstAlias<"memh($Rs32)=clrbit(#$II)", (L4_iand_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_iand_memopw_zomapAlias : InstAlias<"memw($Rs32)=clrbit(#$II)", (L4_iand_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_ior_memopb_zomapAlias : InstAlias<"memb($Rs32)=setbit(#$II)", (L4_ior_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_ior_memoph_zomapAlias : InstAlias<"memh($Rs32)=setbit(#$II)", (L4_ior_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_ior_memopw_zomapAlias : InstAlias<"memw($Rs32)=setbit(#$II)", (L4_ior_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_isub_memopb_zomapAlias : InstAlias<"memb($Rs32)-=#$II", (L4_isub_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_isub_memoph_zomapAlias : InstAlias<"memh($Rs32)-=#$II", (L4_isub_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_isub_memopw_zomapAlias : InstAlias<"memw($Rs32)-=#$II", (L4_isub_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; -def L4_or_memopb_zomapAlias : InstAlias<"memb($Rs32)|=$Rt32", (L4_or_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def L4_or_memoph_zomapAlias : InstAlias<"memh($Rs32)|=$Rt32", (L4_or_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def L4_or_memopw_zomapAlias : InstAlias<"memw($Rs32)|=$Rt32", (L4_or_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def L4_sub_memopb_zomapAlias : InstAlias<"memb($Rs32)-=$Rt32", (L4_sub_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def L4_sub_memoph_zomapAlias : InstAlias<"memh($Rs32)-=$Rt32", (L4_sub_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def L4_sub_memopw_zomapAlias : InstAlias<"memw($Rs32)-=$Rt32", (L4_sub_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def M2_mpyuiAlias : InstAlias<"$Rd32=mpyui($Rs32,$Rt32)", (M2_mpyi IntRegs:$Rd32, IntRegs:$Rs32, IntRegs:$Rt32)>; -def S2_pstorerbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=$Rt32", (S2_pstorerbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_pstorerbnewf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=$Nt8.new", (S2_pstorerbnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S2_pstorerbnewt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=$Nt8.new", (S2_pstorerbnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S2_pstorerbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=$Rt32", (S2_pstorerbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_pstorerdf_zomapAlias : InstAlias<"if (!$Pv4) memd($Rs32)=$Rtt32", (S2_pstorerdf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; -def S2_pstorerdt_zomapAlias : InstAlias<"if ($Pv4) memd($Rs32)=$Rtt32", (S2_pstorerdt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; -def S2_pstorerff_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Rt32.h", (S2_pstorerff_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_pstorerft_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Rt32.h", (S2_pstorerft_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_pstorerhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Rt32", (S2_pstorerhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_pstorerhnewf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Nt8.new", (S2_pstorerhnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S2_pstorerhnewt_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Nt8.new", (S2_pstorerhnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S2_pstorerht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Rt32", (S2_pstorerht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_pstorerif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=$Rt32", (S2_pstorerif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_pstorerinewf_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=$Nt8.new", (S2_pstorerinewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S2_pstorerinewt_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=$Nt8.new", (S2_pstorerinewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S2_pstorerit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=$Rt32", (S2_pstorerit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_storerb_zomapAlias : InstAlias<"memb($Rs32)=$Rt32", (S2_storerb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_storerbnew_zomapAlias : InstAlias<"memb($Rs32)=$Nt8.new", (S2_storerbnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S2_storerd_zomapAlias : InstAlias<"memd($Rs32)=$Rtt32", (S2_storerd_io IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; -def S2_storerf_zomapAlias : InstAlias<"memh($Rs32)=$Rt32.h", (S2_storerf_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_storerh_zomapAlias : InstAlias<"memh($Rs32)=$Rt32", (S2_storerh_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_storerhnew_zomapAlias : InstAlias<"memh($Rs32)=$Nt8.new", (S2_storerhnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S2_storeri_zomapAlias : InstAlias<"memw($Rs32)=$Rt32", (S2_storeri_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S2_storerinew_zomapAlias : InstAlias<"memw($Rs32)=$Nt8.new", (S2_storerinew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S2_tableidxb_goodsyntaxAlias : InstAlias<"$Rx32=tableidxb($Rs32,#$Ii,#$II)", (S2_tableidxb IntRegs:$Rx32, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II)>; -def S4_pstorerbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=$Rt32", (S4_pstorerbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S4_pstorerbnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=$Nt8.new", (S4_pstorerbnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S4_pstorerbnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=$Nt8.new", (S4_pstorerbnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S4_pstorerbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=$Rt32", (S4_pstorerbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S4_pstorerdfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memd($Rs32)=$Rtt32", (S4_pstorerdfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; -def S4_pstorerdtnew_zomapAlias : InstAlias<"if ($Pv4.new) memd($Rs32)=$Rtt32", (S4_pstorerdtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; -def S4_pstorerffnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Rt32.h", (S4_pstorerffnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S4_pstorerftnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Rt32.h", (S4_pstorerftnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S4_pstorerhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Rt32", (S4_pstorerhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S4_pstorerhnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Nt8.new", (S4_pstorerhnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S4_pstorerhnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Nt8.new", (S4_pstorerhnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S4_pstorerhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Rt32", (S4_pstorerhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S4_pstorerifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=$Rt32", (S4_pstorerifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S4_pstorerinewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=$Nt8.new", (S4_pstorerinewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S4_pstorerinewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=$Nt8.new", (S4_pstorerinewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; -def S4_pstoreritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=$Rt32", (S4_pstoreritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; -def S4_storeirb_zomapAlias : InstAlias<"memb($Rs32)=#$II", (S4_storeirb_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=#$II", (S4_storeirbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=#$II", (S4_storeirbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=#$II", (S4_storeirbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=#$II", (S4_storeirbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirh_zomapAlias : InstAlias<"memh($Rs32)=#$II", (S4_storeirh_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=#$II", (S4_storeirhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=#$II", (S4_storeirhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=#$II", (S4_storeirht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=#$II", (S4_storeirhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeiri_zomapAlias : InstAlias<"memw($Rs32)=#$II", (S4_storeiri_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=#$II", (S4_storeirif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=#$II", (S4_storeirifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeirit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=#$II", (S4_storeirit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def S4_storeiritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=#$II", (S4_storeiritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; -def V6_MAP_equbAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equb_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equhAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equh_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equwAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_MAP_equw_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_extractw_altAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, HvxVR:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; -def V6_ld0Alias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ldnt0Alias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_ldu0Alias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; -def V6_st0Alias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stn0Alias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8)>, Requires<[UseHVX]>; -def V6_stnnt0Alias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8)>, Requires<[UseHVX]>; -def V6_stnp0Alias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stnpnt0Alias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stnq0Alias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stnqnt0Alias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stnt0Alias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stp0Alias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stpnt0Alias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stq0Alias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stu0Alias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; -def V6_vabsdiffh_altAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffub_altAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffuh_altAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsdiffw_altAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vabsh_altAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsh_sat_altAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsuh_altAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsuw_altAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsw_altAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vabsw_sat_altAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddb_altAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddb_dv_altAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddh_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddh_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddhsat_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddhsat_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddhw_altAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubh_altAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubsat_altAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddubsat_dv_altAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vadduhsat_altAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vadduhsat_dv_altAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vadduhw_altAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddw_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddw_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vaddwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vaddwsat_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vaddwsat_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vandqrt_acc_altAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc HvxVR:$Vx32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandqrt_altAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt HvxVR:$Vd32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandvrt_acc_altAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc HvxQR:$Qx4, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vandvrt_altAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt HvxQR:$Qd4, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslh_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslhv_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vaslw_acc_altAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslw_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vaslwv_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vasrh_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32=vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrhubsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrhv_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vasrw_acc_altAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrw_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vasrwh_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwhsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32=vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; -def V6_vasrwv_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgh_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vavghrnd_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgub_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgubrnd_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vavguh_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vavguhrnd_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgw_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vavgwrnd_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vcl0h_altAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vcl0w_altAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vd0Alias : InstAlias<"$Vd32=#0", (V6_vxor HvxVR:$Vd32, HvxVR:$Vd32, HvxVR:$Vd32)>, Requires<[UseHVX]>; -def V6_vdd0Alias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv HvxWR:$Vdd32, W15, W15)>, Requires<[UseHVX]>; -def V6_vdealb4w_altAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vdealb_altAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vdealh_altAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vdmpybus_acc_altAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_altAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpybus_dv_altAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_acc_altAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_altAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhb_dv_altAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhisat_altAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsuisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsuisat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsusat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhsusat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdmpyhvsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vdmpyhvsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vdsaduh_acc_altAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vdsaduh_altAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrh_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrhv_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vlsrw_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vlsrwv_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxh_altAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxub_altAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxuh_altAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmaxw_altAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vminh_altAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vminub_altAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vminuh_altAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vminw_altAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpabus_acc_altAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpabus_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpabusv_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vmpabuuv_altAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vmpahb_acc_altAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpahb_altAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybus_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybus_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpybusv_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybusv_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybv_acc_altAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpybv_altAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyewuh_altAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyh_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhsat_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhss_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyhus_acc_altAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhus_altAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhv_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyhvsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewuh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiewuh_altAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyih_acc_altAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyih_altAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyihb_acc_altAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyihb_altAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiowh_altAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyiwb_acc_altAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwb_altAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwh_acc_altAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyiwh_altAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyowh_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyowh_rnd_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyub_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyub_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyubv_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyubv_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyuh_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyuh_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vmpyuhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vmpyuhv_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgh_altAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgub_altAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vnavgw_altAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vnormamth_altAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vnormamtw_altAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vpackeb_altAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackeh_altAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackhb_sat_altAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackhub_sat_altAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackob_altAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackoh_altAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackwh_sat_altAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vpackwuh_sat_altAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vpopcounth_altAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vrmpybus_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpybus_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpybusi_acc_altAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpybusi_altAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpybusv_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybusv_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybv_acc_altAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpybv_altAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpyub_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpyub_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vrmpyubv_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundhb_altAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundhub_altAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundwh_altAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vroundwuh_altAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vrsadubi_acc_altAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vrsadubi_altAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; -def V6_vsathub_altAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsatwh_altAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsb_altAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vsh_altAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vshufeh_altAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vshuffb_altAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vshuffeb_altAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vshuffh_altAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vshuffob_altAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoeb_altAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoeh_altAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vshufoh_altAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubb_altAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubb_dv_altAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubh_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubh_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubhsat_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubhsat_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubhw_altAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububh_altAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububsat_altAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsububsat_dv_altAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubuhsat_altAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubuhsat_dv_altAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubuhw_altAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubw_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubw_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vsubwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vsubwsat_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; -def V6_vsubwsat_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; -def V6_vtmpyb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyb_altAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpybus_acc_altAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpybus_altAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyhb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vtmpyhb_altAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def L2_loadalignb_zomapAlias : InstAlias<"$Ryy32 = memb_fifo($Rs32)", (L2_loadalignb_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>; +def L2_loadalignh_zomapAlias : InstAlias<"$Ryy32 = memh_fifo($Rs32)", (L2_loadalignh_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>; +def L2_loadbsw2_zomapAlias : InstAlias<"$Rd32 = membh($Rs32)", (L2_loadbsw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadbsw4_zomapAlias : InstAlias<"$Rdd32 = membh($Rs32)", (L2_loadbsw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; +def L2_loadbzw2_zomapAlias : InstAlias<"$Rd32 = memubh($Rs32)", (L2_loadbzw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadbzw4_zomapAlias : InstAlias<"$Rdd32 = memubh($Rs32)", (L2_loadbzw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; +def L2_loadrb_zomapAlias : InstAlias<"$Rd32 = memb($Rs32)", (L2_loadrb_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadrd_zomapAlias : InstAlias<"$Rdd32 = memd($Rs32)", (L2_loadrd_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; +def L2_loadrh_zomapAlias : InstAlias<"$Rd32 = memh($Rs32)", (L2_loadrh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadri_zomapAlias : InstAlias<"$Rd32 = memw($Rs32)", (L2_loadri_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadrub_zomapAlias : InstAlias<"$Rd32 = memub($Rs32)", (L2_loadrub_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadruh_zomapAlias : InstAlias<"$Rd32 = memuh($Rs32)", (L2_loadruh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_ploadrbf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32 = memb($Rs32)", (L2_ploadrbf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrbfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32 = memb($Rs32)", (L2_ploadrbfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrbt_zomapAlias : InstAlias<"if ($Pt4) $Rd32 = memb($Rs32)", (L2_ploadrbt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrbtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32 = memb($Rs32)", (L2_ploadrbtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdf_zomapAlias : InstAlias<"if (!$Pt4) $Rdd32 = memd($Rs32)", (L2_ploadrdf_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rdd32 = memd($Rs32)", (L2_ploadrdfnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdt_zomapAlias : InstAlias<"if ($Pt4) $Rdd32 = memd($Rs32)", (L2_ploadrdt_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rdd32 = memd($Rs32)", (L2_ploadrdtnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32 = memh($Rs32)", (L2_ploadrhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32 = memh($Rs32)", (L2_ploadrhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrht_zomapAlias : InstAlias<"if ($Pt4) $Rd32 = memh($Rs32)", (L2_ploadrht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32 = memh($Rs32)", (L2_ploadrhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrif_zomapAlias : InstAlias<"if (!$Pt4) $Rd32 = memw($Rs32)", (L2_ploadrif_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrifnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32 = memw($Rs32)", (L2_ploadrifnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrit_zomapAlias : InstAlias<"if ($Pt4) $Rd32 = memw($Rs32)", (L2_ploadrit_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadritnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32 = memw($Rs32)", (L2_ploadritnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32 = memub($Rs32)", (L2_ploadrubf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32 = memub($Rs32)", (L2_ploadrubfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubt_zomapAlias : InstAlias<"if ($Pt4) $Rd32 = memub($Rs32)", (L2_ploadrubt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32 = memub($Rs32)", (L2_ploadrubtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32 = memuh($Rs32)", (L2_ploadruhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32 = memuh($Rs32)", (L2_ploadruhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruht_zomapAlias : InstAlias<"if ($Pt4) $Rd32 = memuh($Rs32)", (L2_ploadruht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32 = memuh($Rs32)", (L2_ploadruhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L4_add_memopb_zomapAlias : InstAlias<"memb($Rs32) += $Rt32", (L4_add_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_add_memoph_zomapAlias : InstAlias<"memh($Rs32) += $Rt32", (L4_add_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_add_memopw_zomapAlias : InstAlias<"memw($Rs32) += $Rt32", (L4_add_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_and_memopb_zomapAlias : InstAlias<"memb($Rs32) &= $Rt32", (L4_and_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_and_memoph_zomapAlias : InstAlias<"memh($Rs32) &= $Rt32", (L4_and_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_and_memopw_zomapAlias : InstAlias<"memw($Rs32) &= $Rt32", (L4_and_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_iadd_memopb_zomapAlias : InstAlias<"memb($Rs32) += #$II", (L4_iadd_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iadd_memoph_zomapAlias : InstAlias<"memh($Rs32) += #$II", (L4_iadd_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iadd_memopw_zomapAlias : InstAlias<"memw($Rs32) += #$II", (L4_iadd_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iand_memopb_zomapAlias : InstAlias<"memb($Rs32) = clrbit(#$II)", (L4_iand_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iand_memoph_zomapAlias : InstAlias<"memh($Rs32) = clrbit(#$II)", (L4_iand_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iand_memopw_zomapAlias : InstAlias<"memw($Rs32) = clrbit(#$II)", (L4_iand_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_ior_memopb_zomapAlias : InstAlias<"memb($Rs32) = setbit(#$II)", (L4_ior_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_ior_memoph_zomapAlias : InstAlias<"memh($Rs32) = setbit(#$II)", (L4_ior_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_ior_memopw_zomapAlias : InstAlias<"memw($Rs32) = setbit(#$II)", (L4_ior_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_isub_memopb_zomapAlias : InstAlias<"memb($Rs32) -= #$II", (L4_isub_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_isub_memoph_zomapAlias : InstAlias<"memh($Rs32) -= #$II", (L4_isub_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_isub_memopw_zomapAlias : InstAlias<"memw($Rs32) -= #$II", (L4_isub_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_or_memopb_zomapAlias : InstAlias<"memb($Rs32) |= $Rt32", (L4_or_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_or_memoph_zomapAlias : InstAlias<"memh($Rs32) |= $Rt32", (L4_or_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_or_memopw_zomapAlias : InstAlias<"memw($Rs32) |= $Rt32", (L4_or_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_return_map_to_raw_fAlias : InstAlias<"if (!$Pv4) dealloc_return", (L4_return_f D15, PredRegs:$Pv4, R30)>; +def L4_return_map_to_raw_fnew_pntAlias : InstAlias<"if (!$Pv4.new) dealloc_return:nt", (L4_return_fnew_pnt D15, PredRegs:$Pv4, R30)>; +def L4_return_map_to_raw_fnew_ptAlias : InstAlias<"if (!$Pv4.new) dealloc_return:t", (L4_return_fnew_pt D15, PredRegs:$Pv4, R30)>; +def L4_return_map_to_raw_tAlias : InstAlias<"if ($Pv4) dealloc_return", (L4_return_t D15, PredRegs:$Pv4, R30)>; +def L4_return_map_to_raw_tnew_pntAlias : InstAlias<"if ($Pv4.new) dealloc_return:nt", (L4_return_tnew_pnt D15, PredRegs:$Pv4, R30)>; +def L4_return_map_to_raw_tnew_ptAlias : InstAlias<"if ($Pv4.new) dealloc_return:t", (L4_return_tnew_pt D15, PredRegs:$Pv4, R30)>; +def L4_sub_memopb_zomapAlias : InstAlias<"memb($Rs32) -= $Rt32", (L4_sub_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_sub_memoph_zomapAlias : InstAlias<"memh($Rs32) -= $Rt32", (L4_sub_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_sub_memopw_zomapAlias : InstAlias<"memw($Rs32) -= $Rt32", (L4_sub_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L6_deallocframe_map_to_rawAlias : InstAlias<"deallocframe", (L2_deallocframe D15, R30)>; +def L6_return_map_to_rawAlias : InstAlias<"dealloc_return", (L4_return D15, R30)>; +def M2_mpyuiAlias : InstAlias<"$Rd32 = mpyui($Rs32,$Rt32)", (M2_mpyi IntRegs:$Rd32, IntRegs:$Rs32, IntRegs:$Rt32)>; +def S2_pstorerbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32) = $Rt32", (S2_pstorerbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerbnewf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32) = $Nt8.new", (S2_pstorerbnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerbnewt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32) = $Nt8.new", (S2_pstorerbnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32) = $Rt32", (S2_pstorerbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerdf_zomapAlias : InstAlias<"if (!$Pv4) memd($Rs32) = $Rtt32", (S2_pstorerdf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S2_pstorerdt_zomapAlias : InstAlias<"if ($Pv4) memd($Rs32) = $Rtt32", (S2_pstorerdt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S2_pstorerff_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32) = $Rt32.h", (S2_pstorerff_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerft_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32) = $Rt32.h", (S2_pstorerft_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32) = $Rt32", (S2_pstorerhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerhnewf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32) = $Nt8.new", (S2_pstorerhnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerhnewt_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32) = $Nt8.new", (S2_pstorerhnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32) = $Rt32", (S2_pstorerht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32) = $Rt32", (S2_pstorerif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerinewf_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32) = $Nt8.new", (S2_pstorerinewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerinewt_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32) = $Nt8.new", (S2_pstorerinewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32) = $Rt32", (S2_pstorerit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerb_zomapAlias : InstAlias<"memb($Rs32) = $Rt32", (S2_storerb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerbnew_zomapAlias : InstAlias<"memb($Rs32) = $Nt8.new", (S2_storerbnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_storerd_zomapAlias : InstAlias<"memd($Rs32) = $Rtt32", (S2_storerd_io IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S2_storerf_zomapAlias : InstAlias<"memh($Rs32) = $Rt32.h", (S2_storerf_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerh_zomapAlias : InstAlias<"memh($Rs32) = $Rt32", (S2_storerh_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerhnew_zomapAlias : InstAlias<"memh($Rs32) = $Nt8.new", (S2_storerhnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_storeri_zomapAlias : InstAlias<"memw($Rs32) = $Rt32", (S2_storeri_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerinew_zomapAlias : InstAlias<"memw($Rs32) = $Nt8.new", (S2_storerinew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_tableidxb_goodsyntaxAlias : InstAlias<"$Rx32 = tableidxb($Rs32,#$Ii,#$II)", (S2_tableidxb IntRegs:$Rx32, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II)>; +def S4_pstorerbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32) = $Rt32", (S4_pstorerbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerbnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32) = $Nt8.new", (S4_pstorerbnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerbnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32) = $Nt8.new", (S4_pstorerbnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32) = $Rt32", (S4_pstorerbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerdfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memd($Rs32) = $Rtt32", (S4_pstorerdfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S4_pstorerdtnew_zomapAlias : InstAlias<"if ($Pv4.new) memd($Rs32) = $Rtt32", (S4_pstorerdtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S4_pstorerffnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32) = $Rt32.h", (S4_pstorerffnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerftnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32) = $Rt32.h", (S4_pstorerftnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32) = $Rt32", (S4_pstorerhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerhnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32) = $Nt8.new", (S4_pstorerhnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerhnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32) = $Nt8.new", (S4_pstorerhnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32) = $Rt32", (S4_pstorerhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32) = $Rt32", (S4_pstorerifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerinewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32) = $Nt8.new", (S4_pstorerinewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerinewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32) = $Nt8.new", (S4_pstorerinewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstoreritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32) = $Rt32", (S4_pstoreritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_storeirb_zomapAlias : InstAlias<"memb($Rs32) = #$II", (S4_storeirb_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32) = #$II", (S4_storeirbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32) = #$II", (S4_storeirbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32) = #$II", (S4_storeirbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32) = #$II", (S4_storeirbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirh_zomapAlias : InstAlias<"memh($Rs32) = #$II", (S4_storeirh_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32) = #$II", (S4_storeirhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32) = #$II", (S4_storeirhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32) = #$II", (S4_storeirht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32) = #$II", (S4_storeirhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeiri_zomapAlias : InstAlias<"memw($Rs32) = #$II", (S4_storeiri_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32) = #$II", (S4_storeirif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32) = #$II", (S4_storeirifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32) = #$II", (S4_storeirit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeiritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32) = #$II", (S4_storeiritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S6_allocframe_to_rawAlias : InstAlias<"allocframe(#$Ii)", (S2_allocframe R29, u11_3Imm:$Ii)>; +def V6_MAP_equbAlias : InstAlias<"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_andAlias : InstAlias<"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_iorAlias : InstAlias<"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_xorAlias : InstAlias<"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equhAlias : InstAlias<"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_andAlias : InstAlias<"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_iorAlias : InstAlias<"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_xorAlias : InstAlias<"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equwAlias : InstAlias<"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw HvxQR:$Qd4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_andAlias : InstAlias<"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_iorAlias : InstAlias<"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_xorAlias : InstAlias<"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor HvxQR:$Qx4, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_extractw_altAlias : InstAlias<"$Rd32.w = vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, HvxVR:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; +def V6_ld0Alias : InstAlias<"$Vd32 = vmem($Rt32)", (V6_vL32b_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldcnp0Alias : InstAlias<"if (!$Pv4) $Vd32.cur = vmem($Rt32)", (V6_vL32b_cur_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>; +def V6_ldcnpnt0Alias : InstAlias<"if (!$Pv4) $Vd32.cur = vmem($Rt32):nt", (V6_vL32b_nt_cur_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>; +def V6_ldcp0Alias : InstAlias<"if ($Pv4) $Vd32.cur = vmem($Rt32)", (V6_vL32b_cur_pred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>; +def V6_ldcpnt0Alias : InstAlias<"if ($Pv4) $Vd32.cur = vmem($Rt32):nt", (V6_vL32b_nt_cur_pred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>; +def V6_ldnp0Alias : InstAlias<"if (!$Pv4) $Vd32 = vmem($Rt32)", (V6_vL32b_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>; +def V6_ldnpnt0Alias : InstAlias<"if (!$Pv4) $Vd32 = vmem($Rt32):nt", (V6_vL32b_nt_npred_pi HvxVR:$Vd32, IntRegs:$Rt32, PredRegs:$Pv4, 0)>, Requires<[UseHVX]>; +def V6_ldnt0Alias : InstAlias<"$Vd32 = vmem($Rt32):nt", (V6_vL32b_nt_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldntnt0Alias : InstAlias<"$Vd32 = vmem($Rt32):nt", (V6_vL32b_nt_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>; +def V6_ldp0Alias : InstAlias<"if ($Pv4) $Vd32 = vmem($Rt32)", (V6_vL32b_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldpnt0Alias : InstAlias<"if ($Pv4) $Vd32 = vmem($Rt32):nt", (V6_vL32b_nt_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldtnp0Alias : InstAlias<"if (!$Pv4) $Vd32.tmp = vmem($Rt32)", (V6_vL32b_npred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldtnpnt0Alias : InstAlias<"if (!$Pv4) $Vd32.tmp = vmem($Rt32):nt", (V6_vL32b_nt_npred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldtp0Alias : InstAlias<"if ($Pv4) $Vd32.tmp = vmem($Rt32)", (V6_vL32b_tmp_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldtpnt0Alias : InstAlias<"if ($Pv4) $Vd32.tmp = vmem($Rt32):nt", (V6_vL32b_nt_tmp_pred_ai HvxVR:$Vd32, PredRegs:$Pv4, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldu0Alias : InstAlias<"$Vd32 = vmemu($Rt32)", (V6_vL32Ub_ai HvxVR:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_st0Alias : InstAlias<"vmem($Rt32) = $Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stn0Alias : InstAlias<"vmem($Rt32) = $Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8)>, Requires<[UseHVX]>; +def V6_stnnt0Alias : InstAlias<"vmem($Rt32):nt = $Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, HvxVR:$Os8)>, Requires<[UseHVX]>; +def V6_stnp0Alias : InstAlias<"if (!$Pv4) vmem($Rt32) = $Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnpnt0Alias : InstAlias<"if (!$Pv4) vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnq0Alias : InstAlias<"if (!$Qv4) vmem($Rt32) = $Vs32", (V6_vS32b_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnqnt0Alias : InstAlias<"if (!$Qv4) vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_nqpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stnt0Alias : InstAlias<"vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stp0Alias : InstAlias<"if ($Pv4) vmem($Rt32) = $Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stpnt0Alias : InstAlias<"if ($Pv4) vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stq0Alias : InstAlias<"if ($Qv4) vmem($Rt32) = $Vs32", (V6_vS32b_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_qpred_ai HvxQR:$Qv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stu0Alias : InstAlias<"vmemu($Rt32) = $Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32) = $Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32) = $Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_vabsb_altAlias : InstAlias<"$Vd32 = vabsb($Vu32)", (V6_vabsb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsb_sat_altAlias : InstAlias<"$Vd32 = vabsb($Vu32):sat", (V6_vabsb_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsdiffh_altAlias : InstAlias<"$Vd32 = vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffub_altAlias : InstAlias<"$Vd32 = vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffuh_altAlias : InstAlias<"$Vd32 = vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffw_altAlias : InstAlias<"$Vd32 = vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsh_altAlias : InstAlias<"$Vd32 = vabsh($Vu32)", (V6_vabsh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsh_sat_altAlias : InstAlias<"$Vd32 = vabsh($Vu32):sat", (V6_vabsh_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsub_altAlias : InstAlias<"$Vd32.ub = vabs($Vu32.b)", (V6_vabsb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuh_altAlias : InstAlias<"$Vd32.uh = vabs($Vu32.h)", (V6_vabsh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuw_altAlias : InstAlias<"$Vd32.uw = vabs($Vu32.w)", (V6_vabsw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_altAlias : InstAlias<"$Vd32 = vabsw($Vu32)", (V6_vabsw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_sat_altAlias : InstAlias<"$Vd32 = vabsw($Vu32):sat", (V6_vabsw_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddb_altAlias : InstAlias<"$Vd32 = vaddb($Vu32,$Vv32)", (V6_vaddb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddb_dv_altAlias : InstAlias<"$Vdd32 = vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b += $Vu32.b", (V6_vaddbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b += $Vu32.b", (V6_vaddbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddbsat_altAlias : InstAlias<"$Vd32 = vaddb($Vu32,$Vv32):sat", (V6_vaddbsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddbsat_dv_altAlias : InstAlias<"$Vdd32 = vaddb($Vuu32,$Vvv32):sat", (V6_vaddbsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddh_altAlias : InstAlias<"$Vd32 = vaddh($Vu32,$Vv32)", (V6_vaddh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddh_dv_altAlias : InstAlias<"$Vdd32 = vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h += $Vu32.h", (V6_vaddhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h += $Vu32.h", (V6_vaddhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhsat_altAlias : InstAlias<"$Vd32 = vaddh($Vu32,$Vv32):sat", (V6_vaddhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddhsat_dv_altAlias : InstAlias<"$Vdd32 = vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhw_acc_altAlias : InstAlias<"$Vxx32 += vaddh($Vu32,$Vv32)", (V6_vaddhw_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddhw_altAlias : InstAlias<"$Vdd32 = vaddh($Vu32,$Vv32)", (V6_vaddhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubh_acc_altAlias : InstAlias<"$Vxx32 += vaddub($Vu32,$Vv32)", (V6_vaddubh_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubh_altAlias : InstAlias<"$Vdd32 = vaddub($Vu32,$Vv32)", (V6_vaddubh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_altAlias : InstAlias<"$Vd32 = vaddub($Vu32,$Vv32):sat", (V6_vaddubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_dv_altAlias : InstAlias<"$Vdd32 = vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_altAlias : InstAlias<"$Vd32 = vadduh($Vu32,$Vv32):sat", (V6_vadduhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_dv_altAlias : InstAlias<"$Vdd32 = vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhw_acc_altAlias : InstAlias<"$Vxx32 += vadduh($Vu32,$Vv32)", (V6_vadduhw_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduhw_altAlias : InstAlias<"$Vdd32 = vadduh($Vu32,$Vv32)", (V6_vadduhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduwsat_altAlias : InstAlias<"$Vd32 = vadduw($Vu32,$Vv32):sat", (V6_vadduwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduwsat_dv_altAlias : InstAlias<"$Vdd32 = vadduw($Vuu32,$Vvv32):sat", (V6_vadduwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddw_altAlias : InstAlias<"$Vd32 = vaddw($Vu32,$Vv32)", (V6_vaddw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddw_dv_altAlias : InstAlias<"$Vdd32 = vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w += $Vu32.w", (V6_vaddwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w += $Vu32.w", (V6_vaddwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwsat_altAlias : InstAlias<"$Vd32 = vaddw($Vu32,$Vv32):sat", (V6_vaddwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddwsat_dv_altAlias : InstAlias<"$Vdd32 = vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vandnqrt_acc_altAlias : InstAlias<"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)", (V6_vandnqrt_acc HvxVR:$Vx32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandnqrt_altAlias : InstAlias<"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)", (V6_vandnqrt HvxVR:$Vd32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandqrt_acc_altAlias : InstAlias<"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc HvxVR:$Vx32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandqrt_altAlias : InstAlias<"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt HvxVR:$Vd32, HvxQR:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_acc_altAlias : InstAlias<"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc HvxQR:$Qx4, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_altAlias : InstAlias<"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt HvxQR:$Qd4, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslh_acc_altAlias : InstAlias<"$Vx32 += vaslh($Vu32,$Rt32)", (V6_vaslh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslh_altAlias : InstAlias<"$Vd32 = vaslh($Vu32,$Rt32)", (V6_vaslh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslhv_altAlias : InstAlias<"$Vd32 = vaslh($Vu32,$Vv32)", (V6_vaslhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vaslw_acc_altAlias : InstAlias<"$Vx32 += vaslw($Vu32,$Rt32)", (V6_vaslw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslw_altAlias : InstAlias<"$Vd32 = vaslw($Vu32,$Rt32)", (V6_vaslw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslwv_altAlias : InstAlias<"$Vd32 = vaslw($Vu32,$Vv32)", (V6_vaslwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrh_acc_altAlias : InstAlias<"$Vx32 += vasrh($Vu32,$Rt32)", (V6_vasrh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrh_altAlias : InstAlias<"$Vd32 = vasrh($Vu32,$Rt32)", (V6_vasrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhubsat_altAlias : InstAlias<"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhv_altAlias : InstAlias<"$Vd32 = vasrh($Vu32,$Vv32)", (V6_vasrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrw_acc_altAlias : InstAlias<"$Vx32 += vasrw($Vu32,$Rt32)", (V6_vasrw_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrw_altAlias : InstAlias<"$Vd32 = vasrw($Vu32,$Rt32)", (V6_vasrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrwh_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwhsat_altAlias : InstAlias<"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwv_altAlias : InstAlias<"$Vd32 = vasrw($Vu32,$Vv32)", (V6_vasrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgb_altAlias : InstAlias<"$Vd32 = vavgb($Vu32,$Vv32)", (V6_vavgb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgbrnd_altAlias : InstAlias<"$Vd32 = vavgb($Vu32,$Vv32):rnd", (V6_vavgbrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgh_altAlias : InstAlias<"$Vd32 = vavgh($Vu32,$Vv32)", (V6_vavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavghrnd_altAlias : InstAlias<"$Vd32 = vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgub_altAlias : InstAlias<"$Vd32 = vavgub($Vu32,$Vv32)", (V6_vavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgubrnd_altAlias : InstAlias<"$Vd32 = vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguh_altAlias : InstAlias<"$Vd32 = vavguh($Vu32,$Vv32)", (V6_vavguh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguhrnd_altAlias : InstAlias<"$Vd32 = vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguw_altAlias : InstAlias<"$Vd32 = vavguw($Vu32,$Vv32)", (V6_vavguw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguwrnd_altAlias : InstAlias<"$Vd32 = vavguw($Vu32,$Vv32):rnd", (V6_vavguwrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgw_altAlias : InstAlias<"$Vd32 = vavgw($Vu32,$Vv32)", (V6_vavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgwrnd_altAlias : InstAlias<"$Vd32 = vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vcl0h_altAlias : InstAlias<"$Vd32 = vcl0h($Vu32)", (V6_vcl0h HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vcl0w_altAlias : InstAlias<"$Vd32 = vcl0w($Vu32)", (V6_vcl0w HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vd0Alias : InstAlias<"$Vd32 = #0", (V6_vxor HvxVR:$Vd32, HvxVR:$Vd32, HvxVR:$Vd32)>, Requires<[UseHVX]>; +def V6_vdd0Alias : InstAlias<"$Vdd32 = #0", (V6_vsubw_dv HvxWR:$Vdd32, W15, W15)>, Requires<[UseHVX]>; +def V6_vdealb4w_altAlias : InstAlias<"$Vd32 = vdealb4w($Vu32,$Vv32)", (V6_vdealb4w HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vdealb_altAlias : InstAlias<"$Vd32 = vdealb($Vu32)", (V6_vdealb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vdealh_altAlias : InstAlias<"$Vd32 = vdealh($Vu32)", (V6_vdealh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vdmpybus_acc_altAlias : InstAlias<"$Vx32 += vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_altAlias : InstAlias<"$Vd32 = vdmpybus($Vu32,$Rt32)", (V6_vdmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_acc_altAlias : InstAlias<"$Vxx32 += vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_altAlias : InstAlias<"$Vdd32 = vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_acc_altAlias : InstAlias<"$Vx32 += vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_altAlias : InstAlias<"$Vd32 = vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_acc_altAlias : InstAlias<"$Vxx32 += vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_altAlias : InstAlias<"$Vdd32 = vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_acc_altAlias : InstAlias<"$Vx32 += vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_altAlias : InstAlias<"$Vd32 = vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_acc_altAlias : InstAlias<"$Vx32 += vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_altAlias : InstAlias<"$Vd32 = vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_acc_altAlias : InstAlias<"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc HvxVR:$Vx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_altAlias : InstAlias<"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat HvxVR:$Vd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_acc_altAlias : InstAlias<"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_altAlias : InstAlias<"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_acc_altAlias : InstAlias<"$Vx32 += vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_altAlias : InstAlias<"$Vd32 = vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vdsaduh_acc_altAlias : InstAlias<"$Vxx32 += vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdsaduh_altAlias : InstAlias<"$Vdd32 = vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrh_altAlias : InstAlias<"$Vd32 = vlsrh($Vu32,$Rt32)", (V6_vlsrh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrhv_altAlias : InstAlias<"$Vd32 = vlsrh($Vu32,$Vv32)", (V6_vlsrhv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vlsrw_altAlias : InstAlias<"$Vd32 = vlsrw($Vu32,$Rt32)", (V6_vlsrw HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrwv_altAlias : InstAlias<"$Vd32 = vlsrw($Vu32,$Vv32)", (V6_vlsrwv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxb_altAlias : InstAlias<"$Vd32 = vmaxb($Vu32,$Vv32)", (V6_vmaxb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxh_altAlias : InstAlias<"$Vd32 = vmaxh($Vu32,$Vv32)", (V6_vmaxh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxub_altAlias : InstAlias<"$Vd32 = vmaxub($Vu32,$Vv32)", (V6_vmaxub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxuh_altAlias : InstAlias<"$Vd32 = vmaxuh($Vu32,$Vv32)", (V6_vmaxuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxw_altAlias : InstAlias<"$Vd32 = vmaxw($Vu32,$Vv32)", (V6_vmaxw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminb_altAlias : InstAlias<"$Vd32 = vminb($Vu32,$Vv32)", (V6_vminb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminh_altAlias : InstAlias<"$Vd32 = vminh($Vu32,$Vv32)", (V6_vminh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminub_altAlias : InstAlias<"$Vd32 = vminub($Vu32,$Vv32)", (V6_vminub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminuh_altAlias : InstAlias<"$Vd32 = vminuh($Vu32,$Vv32)", (V6_vminuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vminw_altAlias : InstAlias<"$Vd32 = vminw($Vu32,$Vv32)", (V6_vminw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpabus_acc_altAlias : InstAlias<"$Vxx32 += vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabus_altAlias : InstAlias<"$Vdd32 = vmpabus($Vuu32,$Rt32)", (V6_vmpabus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabusv_altAlias : InstAlias<"$Vdd32 = vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpabuu_acc_altAlias : InstAlias<"$Vxx32 += vmpabuu($Vuu32,$Rt32)", (V6_vmpabuu_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabuu_altAlias : InstAlias<"$Vdd32 = vmpabuu($Vuu32,$Rt32)", (V6_vmpabuu HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabuuv_altAlias : InstAlias<"$Vdd32 = vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpahb_acc_altAlias : InstAlias<"$Vxx32 += vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpahb_altAlias : InstAlias<"$Vdd32 = vmpahb($Vuu32,$Rt32)", (V6_vmpahb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpauhb_acc_altAlias : InstAlias<"$Vxx32 += vmpauhb($Vuu32,$Rt32)", (V6_vmpauhb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpauhb_altAlias : InstAlias<"$Vdd32 = vmpauhb($Vuu32,$Rt32)", (V6_vmpauhb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_acc_altAlias : InstAlias<"$Vxx32 += vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_altAlias : InstAlias<"$Vdd32 = vmpybus($Vu32,$Rt32)", (V6_vmpybus HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybusv_acc_altAlias : InstAlias<"$Vxx32 += vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybusv_altAlias : InstAlias<"$Vdd32 = vmpybus($Vu32,$Vv32)", (V6_vmpybusv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_acc_altAlias : InstAlias<"$Vxx32 += vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_altAlias : InstAlias<"$Vdd32 = vmpyb($Vu32,$Vv32)", (V6_vmpybv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyewuh_altAlias : InstAlias<"$Vd32 = vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyh_acc_altAlias : InstAlias<"$Vxx32 += vmpyh($Vu32,$Rt32)", (V6_vmpyh_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyh_altAlias : InstAlias<"$Vdd32 = vmpyh($Vu32,$Rt32)", (V6_vmpyh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsat_acc_altAlias : InstAlias<"$Vxx32 += vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsrs_altAlias : InstAlias<"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhss_altAlias : InstAlias<"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhus_acc_altAlias : InstAlias<"$Vxx32 += vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhus_altAlias : InstAlias<"$Vdd32 = vmpyhus($Vu32,$Vv32)", (V6_vmpyhus HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_acc_altAlias : InstAlias<"$Vxx32 += vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_altAlias : InstAlias<"$Vdd32 = vmpyh($Vu32,$Vv32)", (V6_vmpyhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhvsrs_altAlias : InstAlias<"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewh_acc_altAlias : InstAlias<"$Vx32 += vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_acc_altAlias : InstAlias<"$Vx32 += vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_altAlias : InstAlias<"$Vd32 = vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_acc_altAlias : InstAlias<"$Vx32 += vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_altAlias : InstAlias<"$Vd32 = vmpyih($Vu32,$Vv32)", (V6_vmpyih HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyihb_acc_altAlias : InstAlias<"$Vx32 += vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyihb_altAlias : InstAlias<"$Vd32 = vmpyihb($Vu32,$Rt32)", (V6_vmpyihb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiowh_altAlias : InstAlias<"$Vd32 = vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_acc_altAlias : InstAlias<"$Vx32 += vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_altAlias : InstAlias<"$Vd32 = vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_acc_altAlias : InstAlias<"$Vx32 += vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_altAlias : InstAlias<"$Vd32 = vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwub_acc_altAlias : InstAlias<"$Vx32 += vmpyiwub($Vu32,$Rt32)", (V6_vmpyiwub_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwub_altAlias : InstAlias<"$Vd32 = vmpyiwub($Vu32,$Rt32)", (V6_vmpyiwub HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyowh_altAlias : InstAlias<"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyowh_rnd_altAlias : InstAlias<"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyub_acc_altAlias : InstAlias<"$Vxx32 += vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyub_altAlias : InstAlias<"$Vdd32 = vmpyub($Vu32,$Rt32)", (V6_vmpyub HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyubv_acc_altAlias : InstAlias<"$Vxx32 += vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyubv_altAlias : InstAlias<"$Vdd32 = vmpyub($Vu32,$Vv32)", (V6_vmpyubv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuh_acc_altAlias : InstAlias<"$Vxx32 += vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc HvxWR:$Vxx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuh_altAlias : InstAlias<"$Vdd32 = vmpyuh($Vu32,$Rt32)", (V6_vmpyuh HvxWR:$Vdd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_acc_altAlias : InstAlias<"$Vxx32 += vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc HvxWR:$Vxx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_altAlias : InstAlias<"$Vdd32 = vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgb_altAlias : InstAlias<"$Vd32 = vnavgb($Vu32,$Vv32)", (V6_vnavgb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgh_altAlias : InstAlias<"$Vd32 = vnavgh($Vu32,$Vv32)", (V6_vnavgh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgub_altAlias : InstAlias<"$Vd32 = vnavgub($Vu32,$Vv32)", (V6_vnavgub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgw_altAlias : InstAlias<"$Vd32 = vnavgw($Vu32,$Vv32)", (V6_vnavgw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vnormamth_altAlias : InstAlias<"$Vd32 = vnormamth($Vu32)", (V6_vnormamth HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vnormamtw_altAlias : InstAlias<"$Vd32 = vnormamtw($Vu32)", (V6_vnormamtw HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vpackeb_altAlias : InstAlias<"$Vd32 = vpackeb($Vu32,$Vv32)", (V6_vpackeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackeh_altAlias : InstAlias<"$Vd32 = vpackeh($Vu32,$Vv32)", (V6_vpackeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhb_sat_altAlias : InstAlias<"$Vd32 = vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhub_sat_altAlias : InstAlias<"$Vd32 = vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackob_altAlias : InstAlias<"$Vd32 = vpackob($Vu32,$Vv32)", (V6_vpackob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackoh_altAlias : InstAlias<"$Vd32 = vpackoh($Vu32,$Vv32)", (V6_vpackoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwh_sat_altAlias : InstAlias<"$Vd32 = vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwuh_sat_altAlias : InstAlias<"$Vd32 = vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vpopcounth_altAlias : InstAlias<"$Vd32 = vpopcounth($Vu32)", (V6_vpopcounth HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vrmpybub_rtt_acc_altAlias : InstAlias<"$Vxx32.w += vrmpy($Vu32.b,$Rtt32.ub)", (V6_vrmpybub_rtt_acc HvxWR:$Vxx32, HvxVR:$Vu32, DoubleRegs:$Rtt32)>, Requires<[UseHVX]>; +def V6_vrmpybub_rtt_altAlias : InstAlias<"$Vdd32.w = vrmpy($Vu32.b,$Rtt32.ub)", (V6_vrmpybub_rtt HvxWR:$Vdd32, HvxVR:$Vu32, DoubleRegs:$Rtt32)>, Requires<[UseHVX]>; +def V6_vrmpybus_acc_altAlias : InstAlias<"$Vx32 += vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybus_altAlias : InstAlias<"$Vd32 = vrmpybus($Vu32,$Rt32)", (V6_vrmpybus HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybusi_acc_altAlias : InstAlias<"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusi_altAlias : InstAlias<"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusv_acc_altAlias : InstAlias<"$Vx32 += vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybusv_altAlias : InstAlias<"$Vd32 = vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_acc_altAlias : InstAlias<"$Vx32 += vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_altAlias : InstAlias<"$Vd32 = vrmpyb($Vu32,$Vv32)", (V6_vrmpybv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyub_acc_altAlias : InstAlias<"$Vx32 += vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc HvxVR:$Vx32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyub_altAlias : InstAlias<"$Vd32 = vrmpyub($Vu32,$Rt32)", (V6_vrmpyub HvxVR:$Vd32, HvxVR:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyub_rtt_acc_altAlias : InstAlias<"$Vxx32.uw += vrmpy($Vu32.ub,$Rtt32.ub)", (V6_vrmpyub_rtt_acc HvxWR:$Vxx32, HvxVR:$Vu32, DoubleRegs:$Rtt32)>, Requires<[UseHVX]>; +def V6_vrmpyub_rtt_altAlias : InstAlias<"$Vdd32.uw = vrmpy($Vu32.ub,$Rtt32.ub)", (V6_vrmpyub_rtt HvxWR:$Vdd32, HvxVR:$Vu32, DoubleRegs:$Rtt32)>, Requires<[UseHVX]>; +def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32 += vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc HvxVR:$Vx32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyubv_altAlias : InstAlias<"$Vd32 = vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhb_altAlias : InstAlias<"$Vd32 = vroundhb($Vu32,$Vv32):sat", (V6_vroundhb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhub_altAlias : InstAlias<"$Vd32 = vroundhub($Vu32,$Vv32):sat", (V6_vroundhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrounduhub_altAlias : InstAlias<"$Vd32 = vrounduhub($Vu32,$Vv32):sat", (V6_vrounduhub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrounduwuh_altAlias : InstAlias<"$Vd32 = vrounduwuh($Vu32,$Vv32):sat", (V6_vrounduwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwh_altAlias : InstAlias<"$Vd32 = vroundwh($Vu32,$Vv32):sat", (V6_vroundwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwuh_altAlias : InstAlias<"$Vd32 = vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vrsadubi_acc_altAlias : InstAlias<"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrsadubi_altAlias : InstAlias<"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vsathub_altAlias : InstAlias<"$Vd32 = vsathub($Vu32,$Vv32)", (V6_vsathub HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsatuwuh_altAlias : InstAlias<"$Vd32 = vsatuwuh($Vu32,$Vv32)", (V6_vsatuwuh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsatwh_altAlias : InstAlias<"$Vd32 = vsatwh($Vu32,$Vv32)", (V6_vsatwh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsb_altAlias : InstAlias<"$Vdd32 = vsxtb($Vu32)", (V6_vsb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vscattermh_add_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h", (V6_vscattermh_add IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>; +def V6_vscattermh_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", (V6_vscattermh IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>; +def V6_vscattermhq_altAlias : InstAlias<"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", (V6_vscattermhq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>; +def V6_vscattermw_add_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w", (V6_vscattermw_add IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>; +def V6_vscattermw_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", (V6_vscattermw IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>; +def V6_vscattermwh_add_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h", (V6_vscattermhw_add IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32)>, Requires<[UseHVX]>; +def V6_vscattermwh_altAlias : InstAlias<"vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", (V6_vscattermhw IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32)>, Requires<[UseHVX]>; +def V6_vscattermwhq_altAlias : InstAlias<"if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", (V6_vscattermhwq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32)>, Requires<[UseHVX]>; +def V6_vscattermwq_altAlias : InstAlias<"if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", (V6_vscattermwq HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32)>, Requires<[UseHVX]>; +def V6_vsh_altAlias : InstAlias<"$Vdd32 = vsxth($Vu32)", (V6_vsh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vshufeh_altAlias : InstAlias<"$Vd32 = vshuffeh($Vu32,$Vv32)", (V6_vshufeh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffb_altAlias : InstAlias<"$Vd32 = vshuffb($Vu32)", (V6_vshuffb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffeb_altAlias : InstAlias<"$Vd32 = vshuffeb($Vu32,$Vv32)", (V6_vshuffeb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffh_altAlias : InstAlias<"$Vd32 = vshuffh($Vu32)", (V6_vshuffh HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffob_altAlias : InstAlias<"$Vd32 = vshuffob($Vu32,$Vv32)", (V6_vshuffob HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeb_altAlias : InstAlias<"$Vdd32 = vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeh_altAlias : InstAlias<"$Vdd32 = vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoh_altAlias : InstAlias<"$Vd32 = vshuffoh($Vu32,$Vv32)", (V6_vshufoh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_altAlias : InstAlias<"$Vd32 = vsubb($Vu32,$Vv32)", (V6_vsubb HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_dv_altAlias : InstAlias<"$Vdd32 = vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b -= $Vu32.b", (V6_vsubbnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b -= $Vu32.b", (V6_vsubbq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubbsat_altAlias : InstAlias<"$Vd32 = vsubb($Vu32,$Vv32):sat", (V6_vsubbsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubbsat_dv_altAlias : InstAlias<"$Vdd32 = vsubb($Vuu32,$Vvv32):sat", (V6_vsubbsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubh_altAlias : InstAlias<"$Vd32 = vsubh($Vu32,$Vv32)", (V6_vsubh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubh_dv_altAlias : InstAlias<"$Vdd32 = vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h -= $Vu32.h", (V6_vsubhnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h -= $Vu32.h", (V6_vsubhq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhsat_altAlias : InstAlias<"$Vd32 = vsubh($Vu32,$Vv32):sat", (V6_vsubhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubhsat_dv_altAlias : InstAlias<"$Vdd32 = vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhw_altAlias : InstAlias<"$Vdd32 = vsubh($Vu32,$Vv32)", (V6_vsubhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububh_altAlias : InstAlias<"$Vdd32 = vsubub($Vu32,$Vv32)", (V6_vsububh HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_altAlias : InstAlias<"$Vd32 = vsubub($Vu32,$Vv32):sat", (V6_vsububsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_dv_altAlias : InstAlias<"$Vdd32 = vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_altAlias : InstAlias<"$Vd32 = vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_dv_altAlias : InstAlias<"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhw_altAlias : InstAlias<"$Vdd32 = vsubuh($Vu32,$Vv32)", (V6_vsubuhw HvxWR:$Vdd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubuwsat_altAlias : InstAlias<"$Vd32 = vsubuw($Vu32,$Vv32):sat", (V6_vsubuwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubuwsat_dv_altAlias : InstAlias<"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat", (V6_vsubuwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubw_altAlias : InstAlias<"$Vd32 = vsubw($Vu32,$Vv32)", (V6_vsubw HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubw_dv_altAlias : InstAlias<"$Vdd32 = vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w -= $Vu32.w", (V6_vsubwnq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w -= $Vu32.w", (V6_vsubwq HvxVR:$Vx32, HvxQR:$Qv4, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwsat_altAlias : InstAlias<"$Vd32 = vsubw($Vu32,$Vv32):sat", (V6_vsubwsat HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubwsat_dv_altAlias : InstAlias<"$Vdd32 = vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32)>, Requires<[UseHVX]>; +def V6_vtmpyb_acc_altAlias : InstAlias<"$Vxx32 += vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyb_altAlias : InstAlias<"$Vdd32 = vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_acc_altAlias : InstAlias<"$Vxx32 += vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_altAlias : InstAlias<"$Vdd32 = vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_acc_altAlias : InstAlias<"$Vxx32 += vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc HvxWR:$Vxx32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_altAlias : InstAlias<"$Vdd32 = vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb HvxWR:$Vdd32, HvxWR:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; def V6_vtran2x2_mapAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff HvxVR:$Vy32, HvxVR:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>; -def V6_vunpackb_altAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackh_altAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackoh_altAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh HvxWR:$Vxx32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackub_altAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vunpackuh_altAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vzb_altAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; -def V6_vzh_altAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackb_altAlias : InstAlias<"$Vdd32 = vunpackb($Vu32)", (V6_vunpackb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackh_altAlias : InstAlias<"$Vdd32 = vunpackh($Vu32)", (V6_vunpackh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackoh_altAlias : InstAlias<"$Vxx32 |= vunpackoh($Vu32)", (V6_vunpackoh HvxWR:$Vxx32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackub_altAlias : InstAlias<"$Vdd32 = vunpackub($Vu32)", (V6_vunpackub HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackuh_altAlias : InstAlias<"$Vdd32 = vunpackuh($Vu32)", (V6_vunpackuh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vzb_altAlias : InstAlias<"$Vdd32 = vzxtb($Vu32)", (V6_vzb HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; +def V6_vzh_altAlias : InstAlias<"$Vdd32 = vzxth($Vu32)", (V6_vzh HvxWR:$Vdd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; def Y2_dcfetchAlias : InstAlias<"dcfetch($Rs32)", (Y2_dcfetchbo IntRegs:$Rs32, 0)>; diff --git a/llvm/lib/Target/Hexagon/HexagonDepOperands.td b/llvm/lib/Target/Hexagon/HexagonDepOperands.td index 0e83b267873..9d960953f8f 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepOperands.td +++ b/llvm/lib/Target/Hexagon/HexagonDepOperands.td @@ -1,4 +1,4 @@ -//===--- HexagonDepOperands.td --------------------------------------------===// +//===- HexagonDepOperands.td ----------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,10 +6,10 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + -def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; } -def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; } -def s3_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 0>(N->getSExtValue());}]>; def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; } def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; } def s4_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 0>(N->getSExtValue());}]>; @@ -61,6 +61,9 @@ def u1_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<1, 0>(N->getSExtVal def s31_1ImmOperand : AsmOperandClass { let Name = "s31_1Imm"; let RenderMethod = "addSignedImmOperands"; } def s31_1Imm : Operand<i32> { let ParserMatchClass = s31_1ImmOperand; let DecoderMethod = "s31_1ImmDecoder"; } def s31_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 1>(N->getSExtValue());}]>; +def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; } +def s3_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 0>(N->getSExtValue());}]>; def s30_2ImmOperand : AsmOperandClass { let Name = "s30_2Imm"; let RenderMethod = "addSignedImmOperands"; } def s30_2Imm : Operand<i32> { let ParserMatchClass = s30_2ImmOperand; let DecoderMethod = "s30_2ImmDecoder"; } def s30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; diff --git a/llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h b/llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h index 2a3fb832733..656c83f2d0c 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h +++ b/llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h @@ -1,4 +1,4 @@ -//===--- HexagonDepTimingClasses.h ----------------------------------------===// +//===- HexagonDepTimingClasses.h ------------------------------------------===// // // The LLVM Compiler Infrastructure // @@ -6,6 +6,11 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + + + #ifndef TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H #define TARGET_HEXAGON_HEXAGON_DEP_TIMING_CLASSES_H @@ -15,21 +20,19 @@ namespace llvm { inline bool is_TC3x(unsigned SchedClass) { switch (SchedClass) { - case Hexagon::Sched::tc_1000eb10: - case Hexagon::Sched::tc_2aaab1e0: - case Hexagon::Sched::tc_4997da4a: - case Hexagon::Sched::tc_5d806107: - case Hexagon::Sched::tc_6264c5e0: - case Hexagon::Sched::tc_69bb508b: - case Hexagon::Sched::tc_8c8041e6: - case Hexagon::Sched::tc_8cb685d9: - case Hexagon::Sched::tc_a12a5971: - case Hexagon::Sched::tc_ae0722f7: - case Hexagon::Sched::tc_ae2c2dc2: - case Hexagon::Sched::tc_bc5561d8: - case Hexagon::Sched::tc_d6a805a8: - case Hexagon::Sched::tc_f055fbb6: - case Hexagon::Sched::tc_feb4974b: + case Hexagon::Sched::tc_16d0d8d5: + case Hexagon::Sched::tc_1853ea6d: + case Hexagon::Sched::tc_60571023: + case Hexagon::Sched::tc_7934b9df: + case Hexagon::Sched::tc_8fd5f294: + case Hexagon::Sched::tc_b9c0b731: + case Hexagon::Sched::tc_bcc96cee: + case Hexagon::Sched::tc_c6ce9b3f: + case Hexagon::Sched::tc_c6ebf8dd: + case Hexagon::Sched::tc_c82dc1ff: + case Hexagon::Sched::tc_caaebcba: + case Hexagon::Sched::tc_cf59f215: + case Hexagon::Sched::tc_e913dc32: return true; default: return false; @@ -38,8 +41,8 @@ inline bool is_TC3x(unsigned SchedClass) { inline bool is_TC2early(unsigned SchedClass) { switch (SchedClass) { - case Hexagon::Sched::tc_35fb9d13: - case Hexagon::Sched::tc_cbe45117: + case Hexagon::Sched::tc_14cd4cfa: + case Hexagon::Sched::tc_2a160009: return true; default: return false; @@ -48,12 +51,12 @@ inline bool is_TC2early(unsigned SchedClass) { inline bool is_TC4x(unsigned SchedClass) { switch (SchedClass) { - case Hexagon::Sched::tc_09c86199: - case Hexagon::Sched::tc_2d1e6f5c: - case Hexagon::Sched::tc_2e55aa16: - case Hexagon::Sched::tc_3bea1824: - case Hexagon::Sched::tc_e836c161: - case Hexagon::Sched::tc_f1aa2cdb: + case Hexagon::Sched::tc_038a1342: + case Hexagon::Sched::tc_4d99bca9: + case Hexagon::Sched::tc_6792d5ff: + case Hexagon::Sched::tc_9c00ce8d: + case Hexagon::Sched::tc_d580173f: + case Hexagon::Sched::tc_f3eaa14b: return true; default: return false; @@ -62,30 +65,23 @@ inline bool is_TC4x(unsigned SchedClass) { inline bool is_TC2(unsigned SchedClass) { switch (SchedClass) { - case Hexagon::Sched::tc_090485bb: - case Hexagon::Sched::tc_1fe8323c: - case Hexagon::Sched::tc_37326008: - case Hexagon::Sched::tc_3c10f809: - case Hexagon::Sched::tc_47ab9233: - case Hexagon::Sched::tc_485bb57c: - case Hexagon::Sched::tc_511f28f6: - case Hexagon::Sched::tc_583510c7: - case Hexagon::Sched::tc_63cd9d2d: - case Hexagon::Sched::tc_76c4c5ef: - case Hexagon::Sched::tc_7ca2ea10: - case Hexagon::Sched::tc_87601822: - case Hexagon::Sched::tc_88fa2da6: - case Hexagon::Sched::tc_94e6ffd9: - case Hexagon::Sched::tc_ab1b5e74: - case Hexagon::Sched::tc_b0f50e3c: - case Hexagon::Sched::tc_bd16579e: - case Hexagon::Sched::tc_c0cd91a8: - case Hexagon::Sched::tc_ca280e8b: - case Hexagon::Sched::tc_cd321066: - case Hexagon::Sched::tc_d95f4e98: - case Hexagon::Sched::tc_e17ce9ad: - case Hexagon::Sched::tc_f1240c08: - case Hexagon::Sched::tc_faab1248: + case Hexagon::Sched::tc_00afc57e: + case Hexagon::Sched::tc_1b9c9ee5: + case Hexagon::Sched::tc_234a11a5: + case Hexagon::Sched::tc_2b6f77c6: + case Hexagon::Sched::tc_41d5298e: + case Hexagon::Sched::tc_5ba5997d: + case Hexagon::Sched::tc_84df2cd3: + case Hexagon::Sched::tc_87735c3b: + case Hexagon::Sched::tc_897d1a9d: + case Hexagon::Sched::tc_976ddc4f: + case Hexagon::Sched::tc_b44c6e2a: + case Hexagon::Sched::tc_b9c4623f: + case Hexagon::Sched::tc_c2f7d806: + case Hexagon::Sched::tc_c74f796f: + case Hexagon::Sched::tc_d088982c: + case Hexagon::Sched::tc_ef84f62f: + case Hexagon::Sched::tc_f49e76f4: return true; default: return false; @@ -94,43 +90,45 @@ inline bool is_TC2(unsigned SchedClass) { inline bool is_TC1(unsigned SchedClass) { switch (SchedClass) { - case Hexagon::Sched::tc_07ac815d: - case Hexagon::Sched::tc_1b6011fb: - case Hexagon::Sched::tc_1b834fe7: - case Hexagon::Sched::tc_1e062b18: - case Hexagon::Sched::tc_1f9668cc: - case Hexagon::Sched::tc_43068634: - case Hexagon::Sched::tc_47f0b7ad: - case Hexagon::Sched::tc_537e2013: - case Hexagon::Sched::tc_548f402d: - case Hexagon::Sched::tc_5fa2857c: - case Hexagon::Sched::tc_5fe9fcd0: - case Hexagon::Sched::tc_78b3c689: - case Hexagon::Sched::tc_7c2dcd4d: - case Hexagon::Sched::tc_81a23d44: - case Hexagon::Sched::tc_821c4233: - case Hexagon::Sched::tc_92d1833c: - case Hexagon::Sched::tc_9a13af9d: - case Hexagon::Sched::tc_9c18c9a5: - case Hexagon::Sched::tc_9df8b0dc: - case Hexagon::Sched::tc_9f518242: - case Hexagon::Sched::tc_a1fb80e1: - case Hexagon::Sched::tc_a333d2a9: - case Hexagon::Sched::tc_a87879e8: - case Hexagon::Sched::tc_aad55963: - case Hexagon::Sched::tc_b08b653e: - case Hexagon::Sched::tc_b324366f: - case Hexagon::Sched::tc_b5bfaa60: - case Hexagon::Sched::tc_b86c7e8b: - case Hexagon::Sched::tc_c58f771a: - case Hexagon::Sched::tc_d108a090: - case Hexagon::Sched::tc_d1b5a4b6: - case Hexagon::Sched::tc_d2609065: - case Hexagon::Sched::tc_d63b71d1: - case Hexagon::Sched::tc_e2c31426: - case Hexagon::Sched::tc_e8c7a357: - case Hexagon::Sched::tc_eb07ef6f: - case Hexagon::Sched::tc_f16d5b17: + case Hexagon::Sched::tc_181af5d0: + case Hexagon::Sched::tc_1b82a277: + case Hexagon::Sched::tc_1e856f58: + case Hexagon::Sched::tc_351fed2d: + case Hexagon::Sched::tc_3669266a: + case Hexagon::Sched::tc_3cb8ea06: + case Hexagon::Sched::tc_452f85af: + case Hexagon::Sched::tc_481e5e5c: + case Hexagon::Sched::tc_49eb22c8: + case Hexagon::Sched::tc_523fcf30: + case Hexagon::Sched::tc_52d7bbea: + case Hexagon::Sched::tc_53bc8a6a: + case Hexagon::Sched::tc_540fdfbc: + case Hexagon::Sched::tc_55050d58: + case Hexagon::Sched::tc_609d2efe: + case Hexagon::Sched::tc_68cb12ce: + case Hexagon::Sched::tc_6ebb4a12: + case Hexagon::Sched::tc_6efc556e: + case Hexagon::Sched::tc_73043bf4: + case Hexagon::Sched::tc_7a830544: + case Hexagon::Sched::tc_855b0b61: + case Hexagon::Sched::tc_8fe6b782: + case Hexagon::Sched::tc_90f3e30c: + case Hexagon::Sched::tc_97743097: + case Hexagon::Sched::tc_99be14ca: + case Hexagon::Sched::tc_9faf76ae: + case Hexagon::Sched::tc_a46f0df5: + case Hexagon::Sched::tc_a904d137: + case Hexagon::Sched::tc_b9488031: + case Hexagon::Sched::tc_be706f30: + case Hexagon::Sched::tc_c6aa82f7: + case Hexagon::Sched::tc_cde8b071: + case Hexagon::Sched::tc_d6bf0472: + case Hexagon::Sched::tc_dbdffe3d: + case Hexagon::Sched::tc_e0739b8c: + case Hexagon::Sched::tc_e1e99bfa: + case Hexagon::Sched::tc_e9fae2d6: + case Hexagon::Sched::tc_f2704b9a: + case Hexagon::Sched::tc_f8eeed7a: return true; default: return false; diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index a6a950ea045..3d8d561e31c 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -336,6 +336,8 @@ static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR, /// in the block. static bool hasTailCall(const MachineBasicBlock &MBB) { MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr(); + if (I == MBB.end()) + return false; unsigned RetOpc = I->getOpcode(); return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r; } @@ -636,7 +638,9 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const { // Handle EH_RETURN. if (RetOpc == Hexagon::EH_RETURN_JMPR) { - BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe)); + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe)) + .addDef(Hexagon::D15) + .addReg(Hexagon::R30); BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP) .addReg(SP) .addReg(Hexagon::R28); @@ -682,11 +686,15 @@ void HexagonFrameLowering::insertEpilogueInBlock(MachineBasicBlock &MBB) const { // otherwise just add deallocframe. The function could be returning via a // tail call. if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) { - BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe)); + BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe)) + .addDef(Hexagon::D15) + .addReg(Hexagon::R30); return; } unsigned NewOpc = Hexagon::L4_return; - MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc)); + MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc)) + .addDef(Hexagon::D15) + .addReg(Hexagon::R30); // Transfer the function live-out registers. NewI->copyImplicitOps(MF, *RetI); MBB.erase(RetI); @@ -709,10 +717,13 @@ void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB, MachineMemOperand::MOStore, 4, 4); DebugLoc dl = MBB.findDebugLoc(InsertPt); + unsigned SP = HRI.getStackRegister(); if (NumBytes >= ALLOCFRAME_MAX) { // Emit allocframe(#0). BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe)) + .addDef(SP) + .addReg(SP) .addImm(0) .addMemOperand(MMO); @@ -723,6 +734,8 @@ void HexagonFrameLowering::insertAllocframe(MachineBasicBlock &MBB, .addImm(-int(NumBytes)); } else { BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe)) + .addDef(SP) + .addReg(SP) .addImm(NumBytes) .addMemOperand(MMO); } diff --git a/llvm/lib/Target/Hexagon/HexagonGatherPacketize.cpp b/llvm/lib/Target/Hexagon/HexagonGatherPacketize.cpp new file mode 100644 index 00000000000..dcffec7a3b1 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonGatherPacketize.cpp @@ -0,0 +1,103 @@ +//===- HexagonGatherPacketize.cpp -----------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// This pass ensures that producer and consumer of VTMP are paired in a bundle. +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "gather-packetize" + +#include "HexagonTargetMachine.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +using namespace llvm; + +cl::opt<bool> EnableGatherPacketize( + "hexagon-enable-gather-packetize", cl::Hidden, cl::init(true), + cl::desc("Generate gather packets before packetization")); + +namespace llvm { +FunctionPass *createHexagonGatherPacketize(); +void initializeHexagonGatherPacketizePass(PassRegistry &); +} + +namespace { +class HexagonGatherPacketize : public MachineFunctionPass { +public: + static char ID; + HexagonGatherPacketize() : MachineFunctionPass(ID) { + PassRegistry &Registry = *PassRegistry::getPassRegistry(); + initializeHexagonGatherPacketizePass(Registry); + } + + StringRef getPassName() const override { + return "Hexagon Gather Packetize Code"; + } + bool runOnMachineFunction(MachineFunction &Fn) override; +}; + +char HexagonGatherPacketize::ID = 0; + +static inline bool isVtmpDef(const MachineInstr &MI) { + for (const MachineOperand &MO : MI.operands()) + if (MO.isReg() && MO.isDef() && MO.isImplicit() && + (MO.getReg() == Hexagon::VTMP)) { + return true; + } + return false; +} + +static inline bool isVtmpUse(const MachineInstr &MI) { + return (MI.mayStore() && (MI.getOperand(2)).isReg() && + ((MI.getOperand(2)).getReg() == Hexagon::VTMP)); +} + +bool HexagonGatherPacketize::runOnMachineFunction(MachineFunction &Fn) { + if (!EnableGatherPacketize) + return false; + auto &ST = Fn.getSubtarget<HexagonSubtarget>(); + bool HasV65 = ST.hasV65TOps(); + bool UseHVX = ST.useHVXOps(); + if (!(HasV65 & UseHVX)) + return false; + + for (auto &MBB : Fn) { + bool VtmpDef = false; + MachineBasicBlock::iterator MII, MIE, DefMII; + for (MII = MBB.begin(), MIE = MBB.end(); MII != MIE; ++MII) { + MachineInstr &MI = *MII; + if (VtmpDef) { + if (!isVtmpUse(MI)) + continue; + MBB.splice(std::next(DefMII), &MBB, MII); + finalizeBundle(MBB, DefMII.getInstrIterator(), + std::next(MII).getInstrIterator()); + VtmpDef = false; + continue; + } + if (!(isVtmpDef(MI))) + continue; + VtmpDef = true; + DefMII = MII; + } + assert(!VtmpDef && "VTMP producer and consumer not in same block"); + } + return true; +} +} + +//===----------------------------------------------------------------------===// +// Public Constructor Functions +//===----------------------------------------------------------------------===// + +INITIALIZE_PASS(HexagonGatherPacketize, "hexagon-gather-packetize", + "Hexagon gather packetize Code", false, false) + +FunctionPass *llvm::createHexagonGatherPacketize() { + return new HexagonGatherPacketize(); +} diff --git a/llvm/lib/Target/Hexagon/HexagonIICHVX.td b/llvm/lib/Target/Hexagon/HexagonIICHVX.td index 1493d52f08e..a804c5a80d0 100644 --- a/llvm/lib/Target/Hexagon/HexagonIICHVX.td +++ b/llvm/lib/Target/Hexagon/HexagonIICHVX.td @@ -7,6 +7,7 @@ // //===----------------------------------------------------------------------===// +def CVI_GATHER_PSEUDO : InstrItinClass; def CVI_VA : InstrItinClass; class HVXItin { @@ -14,5 +15,14 @@ class HVXItin { InstrItinData<CVI_VA, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, InstrStage<1, [CVI_XLANE,CVI_SHIFT, CVI_MPY0, CVI_MPY1]>], - [9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>]; + [9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>, + + // Used by Gather Pseudo Instructions which are expanded into + // V6_vgather* and V6_vS32b_new_ai. Even though these instructions + // use CVI_ST resource, it's not included below to avoid having more than + // 4 InstrStages and thus changing 'MaxResTerms' to 5. + InstrItinData <CVI_GATHER_PSEUDO, + [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_LD], 0>, InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>]>]; } diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 76a7e77fc38..1101b232850 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -641,6 +641,27 @@ void HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) { CurDAG->RemoveDeadNode(N); return; } + + unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); + if (IntNo == Intrinsic::hexagon_V6_vgathermw || + IntNo == Intrinsic::hexagon_V6_vgathermw_128B || + IntNo == Intrinsic::hexagon_V6_vgathermh || + IntNo == Intrinsic::hexagon_V6_vgathermh_128B || + IntNo == Intrinsic::hexagon_V6_vgathermhw || + IntNo == Intrinsic::hexagon_V6_vgathermhw_128B) { + SelectV65Gather(N); + return; + } + if (IntNo == Intrinsic::hexagon_V6_vgathermwq || + IntNo == Intrinsic::hexagon_V6_vgathermwq_128B || + IntNo == Intrinsic::hexagon_V6_vgathermhq || + IntNo == Intrinsic::hexagon_V6_vgathermhq_128B || + IntNo == Intrinsic::hexagon_V6_vgathermhwq || + IntNo == Intrinsic::hexagon_V6_vgathermhwq_128B) { + SelectV65GatherPred(N); + return; + } + SelectCode(N); } @@ -654,6 +675,12 @@ void HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) { case Intrinsic::hexagon_S2_vsplatrh: Bits = 16; break; + case Intrinsic::hexagon_V6_vaddcarry: + case Intrinsic::hexagon_V6_vaddcarry_128B: + case Intrinsic::hexagon_V6_vsubcarry: + case Intrinsic::hexagon_V6_vsubcarry_128B: + SelectHVXDualOutput(N); + return; default: SelectCode(N); return; diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h index 0028c400786..fc66940ee52 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -101,6 +101,9 @@ public: void SelectConstant(SDNode *N); void SelectConstantFP(SDNode *N); void SelectBitcast(SDNode *N); + void SelectV65Gather(SDNode *N); + void SelectV65GatherPred(SDNode *N); + void SelectHVXDualOutput(SDNode *N); // Include the declarations autogenerated from the selection patterns. #define GET_DAGISEL_DECL diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp index 698d50542fc..17b3a5507d7 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -1971,3 +1971,124 @@ void HexagonDAGToDAGISel::SelectHvxRor(SDNode *N) { HvxSelector(*this, *CurDAG).selectRor(N); } +void HexagonDAGToDAGISel::SelectV65GatherPred(SDNode *N) { + const SDLoc &dl(N); + SDValue Chain = N->getOperand(0); + SDValue Address = N->getOperand(2); + SDValue Predicate = N->getOperand(3); + SDValue Base = N->getOperand(4); + SDValue Modifier = N->getOperand(5); + SDValue Offset = N->getOperand(6); + + unsigned Opcode; + unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); + switch (IntNo) { + default: + llvm_unreachable("Unexpected HVX gather intrinsic."); + case Intrinsic::hexagon_V6_vgathermhq: + case Intrinsic::hexagon_V6_vgathermhq_128B: + Opcode = Hexagon::V6_vgathermhq_pseudo; + break; + case Intrinsic::hexagon_V6_vgathermwq: + case Intrinsic::hexagon_V6_vgathermwq_128B: + Opcode = Hexagon::V6_vgathermwq_pseudo; + break; + case Intrinsic::hexagon_V6_vgathermhwq: + case Intrinsic::hexagon_V6_vgathermhwq_128B: + Opcode = Hexagon::V6_vgathermhwq_pseudo; + break; + } + + SDVTList VTs = CurDAG->getVTList(MVT::Other); + SDValue Ops[] = { Address, Predicate, Base, Modifier, Offset, Chain }; + SDNode *Result = CurDAG->getMachineNode(Opcode, dl, VTs, Ops); + + MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); + MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand(); + cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1); + + ReplaceUses(N, Result); + CurDAG->RemoveDeadNode(N); +} + +void HexagonDAGToDAGISel::SelectV65Gather(SDNode *N) { + const SDLoc &dl(N); + SDValue Chain = N->getOperand(0); + SDValue Address = N->getOperand(2); + SDValue Base = N->getOperand(3); + SDValue Modifier = N->getOperand(4); + SDValue Offset = N->getOperand(5); + + unsigned Opcode; + unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); + switch (IntNo) { + default: + llvm_unreachable("Unexpected HVX gather intrinsic."); + case Intrinsic::hexagon_V6_vgathermh: + case Intrinsic::hexagon_V6_vgathermh_128B: + Opcode = Hexagon::V6_vgathermh_pseudo; + break; + case Intrinsic::hexagon_V6_vgathermw: + case Intrinsic::hexagon_V6_vgathermw_128B: + Opcode = Hexagon::V6_vgathermw_pseudo; + break; + case Intrinsic::hexagon_V6_vgathermhw: + case Intrinsic::hexagon_V6_vgathermhw_128B: + Opcode = Hexagon::V6_vgathermhw_pseudo; + break; + } + + SDVTList VTs = CurDAG->getVTList(MVT::Other); + SDValue Ops[] = { Address, Base, Modifier, Offset, Chain }; + SDNode *Result = CurDAG->getMachineNode(Opcode, dl, VTs, Ops); + + MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); + MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand(); + cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1); + + ReplaceUses(N, Result); + CurDAG->RemoveDeadNode(N); +} + +void HexagonDAGToDAGISel::SelectHVXDualOutput(SDNode *N) { + unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); + SDNode *Result; + switch (IID) { + case Intrinsic::hexagon_V6_vaddcarry: { + SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2), + N->getOperand(3) }; + SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1); + Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops); + break; + } + case Intrinsic::hexagon_V6_vaddcarry_128B: { + SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2), + N->getOperand(3) }; + SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); + Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops); + break; + } + case Intrinsic::hexagon_V6_vsubcarry: { + SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2), + N->getOperand(3) }; + SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1); + Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs, Ops); + break; + } + case Intrinsic::hexagon_V6_vsubcarry_128B: { + SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2), + N->getOperand(3) }; + SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); + Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs, Ops); + break; + } + default: + llvm_unreachable("Unexpected HVX dual output intrinsic."); + } + ReplaceUses(N, Result); + ReplaceUses(SDValue(N, 0), SDValue(Result, 0)); + ReplaceUses(SDValue(N, 1), SDValue(Result, 1)); + CurDAG->RemoveDeadNode(N); +} + + diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index f6d0239e450..8a44a9ec51e 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2257,6 +2257,44 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { return nullptr; } +/// Given an intrinsic, checks if on the target the intrinsic will need to map +/// to a MemIntrinsicNode (touches memory). If this is the case, it returns +/// true and store the intrinsic information into the IntrinsicInfo that was +/// passed to the function. +bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, + const CallInst &I, + unsigned Intrinsic) const { + switch (Intrinsic) { + case Intrinsic::hexagon_V6_vgathermw: + case Intrinsic::hexagon_V6_vgathermw_128B: + case Intrinsic::hexagon_V6_vgathermh: + case Intrinsic::hexagon_V6_vgathermh_128B: + case Intrinsic::hexagon_V6_vgathermhw: + case Intrinsic::hexagon_V6_vgathermhw_128B: + case Intrinsic::hexagon_V6_vgathermwq: + case Intrinsic::hexagon_V6_vgathermwq_128B: + case Intrinsic::hexagon_V6_vgathermhq: + case Intrinsic::hexagon_V6_vgathermhq_128B: + case Intrinsic::hexagon_V6_vgathermhwq: + case Intrinsic::hexagon_V6_vgathermhwq_128B: { + const Module &M = *I.getParent()->getParent()->getParent(); + Info.opc = ISD::INTRINSIC_W_CHAIN; + Type *VecTy = I.getArgOperand(1)->getType(); + Info.memVT = MVT::getVT(VecTy); + Info.ptrVal = I.getArgOperand(0); + Info.offset = 0; + Info.align = M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8; + Info.vol = true; + Info.readMem = true; + Info.writeMem = true; + return true; + } + default: + break; + } + return false; +} + bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { EVT MTy1 = EVT::getEVT(Ty1); EVT MTy2 = EVT::getEVT(Ty2); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index 41fdd53714a..fca48d4cca6 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -102,6 +102,9 @@ namespace HexagonISD { const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const; + bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, + unsigned Intrinsic) const override; + bool isTruncateFree(Type *Ty1, Type *Ty2) const override; bool isTruncateFree(EVT VT1, EVT VT2) const override; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td index 4da2edc24f3..1bb3bc1ea31 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td @@ -77,9 +77,9 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, // Packed only with A or X-type instructions. bits<1> isSoloAX = 0; let TSFlags{7} = isSoloAX; - // Only A-type instruction in first slot or nothing. - bits<1> isSoloAin1 = 0; - let TSFlags{8} = isSoloAin1; + // Restricts slot 1 to ALU-only instructions. + bits<1> isRestrictSlot1AOK = 0; + let TSFlags{8} = isRestrictSlot1AOK; // Predicated instructions. bits<1> isPredicated = 0; @@ -121,6 +121,16 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, bits<2> opExtentAlign = 0; let TSFlags{34-33} = opExtentAlign; // Alignment exponent before extending. + bit cofMax1 = 0; + let TSFlags{35} = cofMax1; + bit cofRelax1 = 0; + let TSFlags{36} = cofRelax1; + bit cofRelax2 = 0; + let TSFlags{37} = cofRelax2; + + bit isRestrictNoSlot1Store = 0; + let TSFlags{38} = isRestrictNoSlot1Store; + // Addressing mode for load/store instructions. AddrModeType addrMode = NoAddrMode; let TSFlags{43-41} = addrMode.Value; @@ -135,6 +145,9 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, bits<1> isFP = 0; let TSFlags {49} = isFP; // Floating-point. + bits<1> isSomeOK = 0; + let TSFlags {50} = isSomeOK; // Relax some grouping constraints. + bits<1> hasNewValue2 = 0; let TSFlags{51} = hasNewValue2; // Second New-value producer insn. bits<3> opNewValue2 = 0; @@ -146,8 +159,8 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, bits<1> prefersSlot3 = 0; let TSFlags{56} = prefersSlot3; // Complex XU - bit cofMax1 = 0; - let TSFlags{60} = cofMax1; + bits<1> hasTmpDst = 0; + let TSFlags{59} = hasTmpDst; // v65 : 'fake" register VTMP is set bit CVINew = 0; let TSFlags{61} = CVINew; @@ -229,15 +242,8 @@ class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [], include "HexagonInstrFormatsV4.td" //===----------------------------------------------------------------------===// -// V55 Instruction Format Definitions + -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// V60 Instruction Format Definitions + +// V60+ Instruction Format Definitions + //===----------------------------------------------------------------------===// include "HexagonInstrFormatsV60.td" - -//===----------------------------------------------------------------------===// -// V62 Instruction Format Definitions + -//===----------------------------------------------------------------------===// +include "HexagonInstrFormatsV65.td" diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td new file mode 100644 index 00000000000..cddb8777b41 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td @@ -0,0 +1,32 @@ +//==- HexagonInstrFormatsV65.td - Hexagon Instruction Formats -*- tablegen -==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the Hexagon V60 instruction classes in TableGen format. +// +//===----------------------------------------------------------------------===// + +//----------------------------------------------------------------------------// +// Hexagon Intruction Flags + +// +// *** Must match BaseInfo.h *** +//----------------------------------------------------------------------------// + +//----------------------------------------------------------------------------// +// Intruction Classes Definitions + +//----------------------------------------------------------------------------// + +class CVI_VA_Resource_NoOpcode<dag outs, dag ins, string asmstr, + list<dag> pattern = [], string cstr = "", + InstrItinClass itin = CVI_VA> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>; + +class CVI_GATHER_TMP_LD_Resource_NoOpcode<dag outs, dag ins, string asmstr, + list<dag> pattern = [], string cstr = "", + InstrItinClass itin = CVI_GATHER_PSEUDO> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_GATHER>; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index eb643d0aeb2..b82a0157e81 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1242,6 +1242,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MBB.erase(MI); return true; } + case Hexagon::PS_tailcall_i: MI.setDesc(get(Hexagon::J2_jump)); return true; @@ -1267,6 +1268,82 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { case Hexagon::PS_jmpretfnew: MI.setDesc(get(Hexagon::J2_jumprfnew)); return true; + + case Hexagon::V6_vgathermh_pseudo: + BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh)) + .add(MI.getOperand(1)) + .add(MI.getOperand(2)) + .add(MI.getOperand(3)); + BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) + .add(MI.getOperand(0)) + .addImm(0) + .addReg(Hexagon::VTMP); + MBB.erase(MI); + return true; + + case Hexagon::V6_vgathermw_pseudo: + BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw)) + .add(MI.getOperand(1)) + .add(MI.getOperand(2)) + .add(MI.getOperand(3)); + BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) + .add(MI.getOperand(0)) + .addImm(0) + .addReg(Hexagon::VTMP); + MBB.erase(MI); + return true; + + case Hexagon::V6_vgathermhw_pseudo: + BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw)) + .add(MI.getOperand(1)) + .add(MI.getOperand(2)) + .add(MI.getOperand(3)); + BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) + .add(MI.getOperand(0)) + .addImm(0) + .addReg(Hexagon::VTMP); + MBB.erase(MI); + return true; + + case Hexagon::V6_vgathermhq_pseudo: + BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq)) + .add(MI.getOperand(1)) + .add(MI.getOperand(2)) + .add(MI.getOperand(3)) + .add(MI.getOperand(4)); + BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) + .add(MI.getOperand(0)) + .addImm(0) + .addReg(Hexagon::VTMP); + MBB.erase(MI); + return true; + + case Hexagon::V6_vgathermwq_pseudo: + BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq)) + .add(MI.getOperand(1)) + .add(MI.getOperand(2)) + .add(MI.getOperand(3)) + .add(MI.getOperand(4)); + BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) + .add(MI.getOperand(0)) + .addImm(0) + .addReg(Hexagon::VTMP); + MBB.erase(MI); + return true; + + case Hexagon::V6_vgathermhwq_pseudo: + BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq)) + .add(MI.getOperand(1)) + .add(MI.getOperand(2)) + .add(MI.getOperand(3)) + .add(MI.getOperand(4)); + BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) + .add(MI.getOperand(0)) + .addImm(0) + .addReg(Hexagon::VTMP); + MBB.erase(MI); + return true; + } return false; @@ -2051,6 +2128,8 @@ bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI, // TODO: Add all the compound branches here. Can we do this in Relation model? case Hexagon::J4_cmpeqi_tp0_jump_nt: case Hexagon::J4_cmpeqi_tp1_jump_nt: + case Hexagon::J4_cmpeqn1_tp0_jump_nt: + case Hexagon::J4_cmpeqn1_tp1_jump_nt: return isInt<11>(offset); } } @@ -2817,10 +2896,8 @@ bool HexagonInstrInfo::producesStall(const MachineInstr &MI, MachineBasicBlock::const_instr_iterator MII = BII; MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end(); - if (!(*MII).isBundle()) { - const MachineInstr &J = *MII; - return producesStall(J, MI); - } + if (!MII->isBundle()) + return producesStall(*MII, MI); for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) { const MachineInstr &J = *MII; @@ -2906,6 +2983,9 @@ unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI, /// Return the position of the base and offset operands for this instruction. bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const { + if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI)) + return false; + // Deal with memops first. if (isMemOp(MI)) { BasePos = 0; @@ -3097,15 +3177,24 @@ unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA, assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B); if ((GA.getOpcode() != Hexagon::C2_cmpeqi) || (GB.getOpcode() != Hexagon::J2_jumptnew)) - return -1; + return -1u; unsigned DestReg = GA.getOperand(0).getReg(); if (!GB.readsRegister(DestReg)) - return -1; - if (DestReg == Hexagon::P0) - return Hexagon::J4_cmpeqi_tp0_jump_nt; - if (DestReg == Hexagon::P1) - return Hexagon::J4_cmpeqi_tp1_jump_nt; - return -1; + return -1u; + if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1) + return -1u; + // The value compared against must be either u5 or -1. + const MachineOperand &CmpOp = GA.getOperand(2); + if (!CmpOp.isImm()) + return -1u; + int V = CmpOp.getImm(); + if (V == -1) + return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt + : Hexagon::J4_cmpeqn1_tp1_jump_nt; + if (!isUInt<5>(V)) + return -1u; + return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt + : Hexagon::J4_cmpeqi_tp1_jump_nt; } int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const { @@ -3514,6 +3603,7 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_L2; case Hexagon::EH_RETURN_JMPR: case Hexagon::PS_jmpret: + case Hexagon::SL2_jumpr31: // jumpr r31 // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0 DstReg = MI.getOperand(0).getReg(); @@ -3526,6 +3616,9 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( case Hexagon::PS_jmpretfnewpt: case Hexagon::PS_jmprettnew: case Hexagon::PS_jmpretfnew: + case Hexagon::SL2_jumpr31_t: + case Hexagon::SL2_jumpr31_f: + case Hexagon::SL2_jumpr31_tnew: DstReg = MI.getOperand(1).getReg(); SrcReg = MI.getOperand(0).getReg(); // [if ([!]p0[.new])] jumpr r31 @@ -3619,8 +3712,8 @@ HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup( return HexagonII::HSIG_S2; break; case Hexagon::S2_allocframe: - if (MI.getOperand(0).isImm() && - isShiftedUInt<5,3>(MI.getOperand(0).getImm())) + if (MI.getOperand(2).isImm() && + isShiftedUInt<5,3>(MI.getOperand(2).getImm())) return HexagonII::HSIG_S1; break; // @@ -3825,8 +3918,14 @@ int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, } } - return TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, - UseMI, UseIdx); + int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, + UseMI, UseIdx); + if (!Latency) + // We should never have 0 cycle latency between two instructions unless + // they can be packetized together. However, this decision can't be made + // here. + Latency = 1; + return Latency; } // inverts the predication logic. @@ -3865,6 +3964,35 @@ int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const { return ~(-1U << bits); } + +bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const { + switch (MI.getOpcode()) { + case Hexagon::L2_loadrbgp: + case Hexagon::L2_loadrdgp: + case Hexagon::L2_loadrhgp: + case Hexagon::L2_loadrigp: + case Hexagon::L2_loadrubgp: + case Hexagon::L2_loadruhgp: + case Hexagon::S2_storerbgp: + case Hexagon::S2_storerbnewgp: + case Hexagon::S2_storerhgp: + case Hexagon::S2_storerhnewgp: + case Hexagon::S2_storerigp: + case Hexagon::S2_storerinewgp: + case Hexagon::S2_storerdgp: + case Hexagon::S2_storerfgp: + return true; + } + const uint64_t F = MI.getDesc().TSFlags; + unsigned addrMode = + ((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask); + // Disallow any base+offset instruction. The assembler does not yet reorder + // based up any zero offset instruction. + return (addrMode == HexagonII::BaseRegOffset || + addrMode == HexagonII::BaseImmOffset || + addrMode == HexagonII::BaseLongOffset); +} + unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const { using namespace HexagonII; @@ -4094,6 +4222,22 @@ bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond) return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1)); } +void HexagonInstrInfo:: +setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const { + assert(MIB->isBundle()); + MachineOperand &Operand = MIB->getOperand(0); + if (Operand.isImm()) + Operand.setImm(Operand.getImm() | memShufDisabledMask); + else + MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask)); +} + +bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const { + assert(MIB.isBundle()); + const MachineOperand &Operand = MIB.getOperand(0); + return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0); +} + // Addressing mode relations. short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const { return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc; @@ -4103,10 +4247,18 @@ short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const { return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc; } +short HexagonInstrInfo::changeAddrMode_io_pi(short Opc) const { + return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc; +} + short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const { return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc; } +short HexagonInstrInfo::changeAddrMode_pi_io(short Opc) const { + return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc; +} + short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const { return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc; } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 1558c2e9850..4530d3b999c 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -38,6 +38,11 @@ class TargetRegisterInfo; class HexagonInstrInfo : public HexagonGenInstrInfo { const HexagonSubtarget &Subtarget; + + enum BundleAttribute { + memShufDisabledMask = 0x4 + }; + virtual void anchor(); public: @@ -326,10 +331,11 @@ public: /// HexagonInstrInfo specifics. - unsigned createVR(MachineFunction* MF, MVT VT) const; + unsigned createVR(MachineFunction *MF, MVT VT) const; bool isAbsoluteSet(const MachineInstr &MI) const; bool isAccumulator(const MachineInstr &MI) const; + bool isAddrModeWithOffset(const MachineInstr &MI) const; bool isComplex(const MachineInstr &MI) const; bool isCompoundBranchInstr(const MachineInstr &MI) const; bool isConstExtended(const MachineInstr &MI) const; @@ -432,7 +438,6 @@ public: HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const; short getEquivalentHWInstr(const MachineInstr &MI) const; - MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const; unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const; bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const; @@ -456,16 +461,20 @@ public: void immediateExtend(MachineInstr &MI) const; bool invertAndChangeJumpTarget(MachineInstr &MI, - MachineBasicBlock* NewTarget) const; + MachineBasicBlock *NewTarget) const; void genAllInsnTimingClasses(MachineFunction &MF) const; bool reversePredSense(MachineInstr &MI) const; unsigned reversePrediction(unsigned Opcode) const; bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const; + void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const; + bool getBundleNoShuf(const MachineInstr &MIB) const; // Addressing mode relations. short changeAddrMode_abs_io(short Opc) const; short changeAddrMode_io_abs(short Opc) const; + short changeAddrMode_io_pi(short Opc) const; short changeAddrMode_io_rr(short Opc) const; + short changeAddrMode_pi_io(short Opc) const; short changeAddrMode_rr_io(short Opc) const; short changeAddrMode_rr_ur(short Opc) const; short changeAddrMode_ur_rr(short Opc) const; diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td index 8a77b7760df..1df143de6e8 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td @@ -735,6 +735,28 @@ def : Pat <(int_hexagon_A2_not I32:$Rs), def : Pat <(int_hexagon_A2_neg I32:$Rs), (A2_subri 0, I32:$Rs)>; +// Make sure the patterns with zero immediate value has higher complexity +// otherwise, we need to updated the predicates for immediates to exclude zero +let AddedComplexity = 200 in { +def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, (i32 0)), + (A2_tfr I32:$Rs)>; +def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, (i32 0)), + (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>; +def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, (i32 0)), + (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>; +def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, (i32 0)), + (S2_vsathub I64:$Rs)>; +} + +def : Pat <(int_hexagon_S2_asr_i_r_rnd_goodsyntax I32:$Rs, u5_0ImmPred:$imm), + (S2_asr_i_r_rnd I32:$Rs, (UDEC1 u5_0ImmPred:$imm))>; +def : Pat <(int_hexagon_S2_asr_i_p_rnd_goodsyntax I64:$Rs, u6_0ImmPred:$imm), + (S2_asr_i_p_rnd I64:$Rs, (UDEC1 u6_0ImmPred:$imm))>; +def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, u4_0ImmPred:$imm), + (S5_vasrhrnd I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>; +def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, u4_0ImmPred:$imm), + (S5_asrhub_rnd_sat I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>; + // Transfer immediate def : Pat <(int_hexagon_A2_tfril I32:$Rs, u16_0ImmPred:$Is), (A2_tfril I32:$Rs, u16_0ImmPred:$Is)>; @@ -1360,6 +1382,11 @@ defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vmaskedstorenq>; defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vmaskedstorentq>; defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vmaskedstorentnq>; +defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vS32b_qpred_ai>; +defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vS32b_nqpred_ai>; +defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vS32b_nt_qpred_ai>; +defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vS32b_nt_nqpred_ai>; + //******************************************************************* // SYSTEM //******************************************************************* diff --git a/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td b/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td new file mode 100644 index 00000000000..718d3ac7d45 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV65.gen.td @@ -0,0 +1,86 @@ +//===--- HexagonMapAsm2IntrinV65.gen.td -----------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV65T]>; +def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2), (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2), (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vavguwrnd HvxVR:$src1, HvxVR:$src2), (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vavguwrnd_128B HvxVR:$src1, HvxVR:$src2), (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2), (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2), (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2), (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vavgbrnd_128B HvxVR:$src1, HvxVR:$src2), (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2), (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vnavgb HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vnavgb_128B HvxVR:$src1, HvxVR:$src2), (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpabuu_128B HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpabuu_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpahhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpauhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpsuhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyuhe HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyuhe_128B HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vmpyuhe_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqb HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqb_128B HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqh HvxQR:$src1), (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqh_128B HvxQR:$src1), (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqw HvxQR:$src1), (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vprefixqw_128B HvxQR:$src1), (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermw_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw_add_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vdd0), (V6_vdd0)>, Requires<[HasV65T, UseHVX]>; +def: Pat<(int_hexagon_V6_vdd0_128B), (V6_vdd0)>, Requires<[HasV65T, UseHVX]>; diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsV65.td b/llvm/lib/Target/Hexagon/HexagonPatternsV65.td new file mode 100644 index 00000000000..50b76847b56 --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonPatternsV65.td @@ -0,0 +1,70 @@ +//==- HexagonPatternsV65.td -------------------------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +multiclass vgathermh<RegisterClass RC> { + let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in + def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ), + (ins IntRegs:$_dst_, IntRegs:$Rt, + ModRegs:$Mu, RC:$Vv), + ".error \"should not emit\" ", + []>; +} + +multiclass vgathermw<RegisterClass RC> { + let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in + def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ), + (ins IntRegs:$_dst_, IntRegs:$Rt, + ModRegs:$Mu, RC:$Vv), + ".error \"should not emit\" ", + []>; +} + +multiclass vgathermhw<RegisterClass RC> { + let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in + def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ), + (ins IntRegs:$_dst_, IntRegs:$Rt, + ModRegs:$Mu, RC:$Vv), + ".error \"should not emit\" ", + []>; +} + +defm V6_vgathermh_pseudo : vgathermh<HvxVR>; +defm V6_vgathermw_pseudo : vgathermw<HvxVR>; +defm V6_vgathermhw_pseudo : vgathermhw<HvxWR>; + +multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> { + let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in + def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ), + (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt, + ModRegs:$Mu, RC1:$Vv), + ".error \"should not emit\" ", + []>; +} + +multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> { + let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in + def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ), + (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt, + ModRegs:$Mu, RC1:$Vv), + ".error \"should not emit\" ", + []>; +} + +multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> { + let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1, mayStore = 1 in + def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ), + (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt, + ModRegs:$Mu, RC1:$Vv), + ".error \"should not emit\" ", + []>; +} + +defm V6_vgathermhq_pseudo : vgathermhq<HvxVR, HvxQR>; +defm V6_vgathermwq_pseudo : vgathermwq<HvxVR, HvxQR>; +defm V6_vgathermhwq_pseudo : vgathermhwq<HvxWR, HvxQR>; diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp index f29f321214c..85d6a6b4089 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -123,6 +123,7 @@ HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { case Hexagon::ArchEnum::V55: case Hexagon::ArchEnum::V60: case Hexagon::ArchEnum::V62: + case Hexagon::ArchEnum::V65: return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3; } @@ -143,6 +144,7 @@ BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF) Reserved.set(Hexagon::R29); Reserved.set(Hexagon::R30); Reserved.set(Hexagon::R31); + Reserved.set(Hexagon::VTMP); // Control registers. Reserved.set(Hexagon::SA0); // C0 Reserved.set(Hexagon::LC0); // C1 diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td index afd63c69101..298b119e9fa 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -15,7 +15,6 @@ let Namespace = "Hexagon" in { class HexagonReg<bits<5> num, string n, list<string> alt = [], list<Register> alias = []> : Register<n, alt> { - field bits<5> Num; let Aliases = alias; let HWEncoding{4-0} = num; } @@ -23,8 +22,6 @@ let Namespace = "Hexagon" in { class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs, list<string> alt = []> : RegisterWithSubRegs<n, subregs> { - field bits<5> Num; - let AltNames = alt; let HWEncoding{4-0} = num; } @@ -32,28 +29,20 @@ let Namespace = "Hexagon" in { // Registers are identified with 5-bit ID numbers. // Ri - 32-bit integer registers. class Ri<bits<5> num, string n, list<string> alt = []> : - HexagonReg<num, n, alt> { - let Num = num; - } + HexagonReg<num, n, alt>; // Rf - 32-bit floating-point registers. - class Rf<bits<5> num, string n> : HexagonReg<num, n> { - let Num = num; - } - + class Rf<bits<5> num, string n> : HexagonReg<num, n>; // Rd - 64-bit registers. class Rd<bits<5> num, string n, list<Register> subregs, list<string> alt = []> : HexagonDoubleReg<num, n, subregs, alt> { - let Num = num; let SubRegs = subregs; } // Rp - predicate registers - class Rp<bits<5> num, string n> : HexagonReg<num, n> { - let Num = num; - } + class Rp<bits<5> num, string n> : HexagonReg<num, n>; // Rq - vector predicate registers @@ -64,21 +53,18 @@ let Namespace = "Hexagon" in { // Rc - control registers class Rc<bits<5> num, string n, list<string> alt = [], list<Register> alias = []> : - HexagonReg<num, n, alt, alias> { - let Num = num; - } + HexagonReg<num, n, alt, alias>; // Rcc - 64-bit control registers. class Rcc<bits<5> num, string n, list<Register> subregs, list<string> alt = []> : HexagonDoubleReg<num, n, subregs, alt> { - let Num = num; let SubRegs = subregs; } // Mx - address modifier registers - class Mx<bits<1> num, string n> : HexagonReg<{0b0000, num}, n> { - let Num = !cast<bits<5>>(num); + class Mx<bits<1> num, string n> : Register<n, []> { + let HWEncoding{0} = num; } def isub_lo : SubRegIndex<32>; @@ -167,25 +153,27 @@ let Namespace = "Hexagon" in { // Control registers pairs. let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { - def C1_0: Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; - def C3_2: Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; - def C5_4: Rcc<4, "c5:4", [P3_0, C5]>, DwarfRegNum<[71]>; - def C7_6: Rcc<6, "c7:6", [M0, M1], ["m1:0"]>, DwarfRegNum<[72]>; + def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; + def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; + def C5_4 : Rcc<4, "c5:4", [P3_0, C5]>, DwarfRegNum<[71]>; + def C7_6 : Rcc<6, "c7:6", [M0, M1], ["m1:0"]>, DwarfRegNum<[72]>; // Use C8 instead of USR as a subregister of C9_8. - def C9_8: Rcc<8, "c9:8", [C8, PC]>, DwarfRegNum<[74]>; - def C11_10: Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; - def CS: Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; - def UPCYCLE: Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI]>, DwarfRegNum<[80]>; - def C17_16: Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>, DwarfRegNum<[83]>; - def PKTCOUNT: Rcc<18, "c19:18", [PKTCOUNTLO, PKTCOUNTHI], ["pktcount"]>, + def C9_8 : Rcc<8, "c9:8", [C8, PC]>, DwarfRegNum<[74]>; + def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; + def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; + def UPCYCLE: Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI], ["upcycle"]>, + DwarfRegNum<[80]>; + def C17_16 : Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>, DwarfRegNum<[83]>; + def PKTCOUNT : Rcc<18, "c19:18", [PKTCOUNTLO, PKTCOUNTHI], ["pktcount"]>, DwarfRegNum<[85]>; - def UTIMER: Rcc<30, "c31:30", [UTIMERLO, UTIMERHI], ["utimer"]>, + def UTIMER : Rcc<30, "c31:30", [UTIMERLO, UTIMERHI], ["utimer"]>, DwarfRegNum<[97]>; } foreach i = 0-31 in { def V#i : Ri<i, "v"#i>, DwarfRegNum<[!add(i, 99)]>; } + def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>; // Aliases of the V* registers used to hold double vec values. let SubRegIndices = [vsub_lo, vsub_hi], CoveredBySubRegs = 1 in { @@ -244,6 +232,8 @@ def VecPI64 : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], [v16i64, v16i64, v32i64, v32i64, v16i64]>; +// HVX register classes + // Register classes. // // FIXME: the register order should be defined in terms of the preferred @@ -268,7 +258,7 @@ def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64, (add D11, D10, D9, D8, D3, D2, D1, D0)>; def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32, VecI64], 512, - (add (sequence "V%u", 0, 31))> { + (add (sequence "V%u", 0, 31), VTMP)> { let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; } @@ -313,6 +303,11 @@ def V62Regs : RegisterClass<"Hexagon", [i32], 32, (add FRAMELIMIT, FRAMEKEY, C17_16, PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT, UTIMERLO, UTIMERHI, UTIMER)>; +// These registers are new for v65 and onward. +let Size = 32, isAllocatable = 0 in +def V65Regs : RegisterClass<"Hexagon", [i32], 32, (add VTMP)>; + + def HexagonCSR : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23, diff --git a/llvm/lib/Target/Hexagon/HexagonSchedule.td b/llvm/lib/Target/Hexagon/HexagonSchedule.td index ffee03e7263..a1dfb66017a 100644 --- a/llvm/lib/Target/Hexagon/HexagonSchedule.td +++ b/llvm/lib/Target/Hexagon/HexagonSchedule.td @@ -79,3 +79,8 @@ include "HexagonScheduleV60.td" include "HexagonScheduleV62.td" +//===----------------------------------------------------------------------===// +// V65 Machine Info + +//===----------------------------------------------------------------------===// + +include "HexagonScheduleV65.td" diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV65.td b/llvm/lib/Target/Hexagon/HexagonScheduleV65.td new file mode 100644 index 00000000000..e3b1313923f --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonScheduleV65.td @@ -0,0 +1,40 @@ +//=-HexagonScheduleV65.td - HexagonV65 Scheduling Definitions *- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +// +// ScalarItin and HVXItin contain some old itineraries +// still used by a handful of instructions. Hopefully, we will be able +// to get rid of them soon. + +def HexagonV65ItinList : DepScalarItinV65, ScalarItin, + DepHVXItinV65, HVXItin, PseudoItin { + list<InstrItinData> ItinList = + !listconcat(DepScalarItinV65_list, ScalarItin_list, + DepHVXItinV65_list, HVXItin_list, PseudoItin_list); +} + +def HexagonItinerariesV65 : + ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, + CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, + CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, + CVI_ALL_NOMEM], + [Hex_FWD, HVX_FWD], + HexagonV65ItinList.ItinList>; + +def HexagonModelV65 : SchedMachineModel { + // Max issue per cycle == bundle width. + let IssueWidth = 4; + let Itineraries = HexagonItinerariesV65; + let LoadLatency = 1; + let CompleteModel = 0; +} + +//===----------------------------------------------------------------------===// +// Hexagon V65 Resource Definitions - +//===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 37f1e455b23..6f1f6c46a10 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -93,7 +93,7 @@ static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict", HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) : HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()), - CPUString(Hexagon_MC::selectHexagonCPU(TT, CPU)), + CPUString(Hexagon_MC::selectHexagonCPU(CPU)), InstrInfo(initializeSubtargetDependencies(CPU, FS)), RegInfo(getHwMode()), TLInfo(TM, *this), InstrItins(getInstrItineraryForCPU(CPUString)) { @@ -110,6 +110,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { {"hexagonv55", Hexagon::ArchEnum::V55}, {"hexagonv60", Hexagon::ArchEnum::V60}, {"hexagonv62", Hexagon::ArchEnum::V62}, + {"hexagonv65", Hexagon::ArchEnum::V65}, }; auto FoundIt = CpuTable.find(CPUString); @@ -131,6 +132,11 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { if (OverrideLongCalls.getPosition()) UseLongCalls = OverrideLongCalls; + FeatureBitset Features = getFeatureBits(); + if (HexagonDisableDuplex) + setFeatureBits(Features.set(Hexagon::FeatureDuplex, false)); + setFeatureBits(Hexagon_MC::completeHVXFeatures(Features)); + return *this; } diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index ea69bd34192..678ef210d0a 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -50,6 +50,8 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { bool UseLongCalls; bool ModeIEEERndNear; + bool HasMemNoShuf = false; + bool EnableDuplex = false; public: Hexagon::ArchEnum HexagonArchVersion; Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::V4; @@ -138,11 +140,18 @@ public: bool hasV62TOpsOnly() const { return getHexagonArchVersion() == Hexagon::ArchEnum::V62; } + bool hasV65TOps() const { + return getHexagonArchVersion() >= Hexagon::ArchEnum::V65; + } + bool hasV65TOpsOnly() const { + return getHexagonArchVersion() == Hexagon::ArchEnum::V65; + } bool modeIEEERndNear() const { return ModeIEEERndNear; } bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; } bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; } bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; } + bool hasMemNoShuf() const { return HasMemNoShuf; } bool useLongCalls() const { return UseLongCalls; } bool usePredicatedCalls() const; diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 683fdea6122..0c40a7b8f38 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -146,6 +146,7 @@ namespace llvm { FunctionPass *createHexagonCopyToCombine(); FunctionPass *createHexagonEarlyIfConversion(); FunctionPass *createHexagonFixupHwLoops(); + FunctionPass *createHexagonGatherPacketize(); FunctionPass *createHexagonGenExtract(); FunctionPass *createHexagonGenInsert(); FunctionPass *createHexagonGenMux(); @@ -396,9 +397,15 @@ void HexagonPassConfig::addPreEmitPass() { // Generate MUX from pairs of conditional transfers. if (EnableGenMux) addPass(createHexagonGenMux()); + } + + // Create packets for 2 instructions that consitute a gather instruction. + // Do this regardless of the opt level. + addPass(createHexagonGatherPacketize(), false); + if (!NoOpt) addPass(createHexagonPacketizer(), false); - } + if (EnableVectorPrint) addPass(createHexagonVectorPrint(), false); diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 0f5e297af4d..b6258907ca6 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -57,6 +57,10 @@ static cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon packetizer pass")); +cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden, + cl::ZeroOrMore, cl::init(true), + cl::desc("Allow slot1 store and slot0 load")); + static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references")); @@ -1050,6 +1054,10 @@ bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI, } bool HexagonPacketizerList::isSoloInstruction(const MachineInstr &MI) { + // Ensure any bundles created by gather packetize remain seperate. + if (MI.isBundle()) + return true; + if (MI.isEHLabel() || MI.isCFIInstruction()) return true; @@ -1099,11 +1107,12 @@ static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, MJ.isCall() || MJ.isTerminator(); switch (MI.getOpcode()) { - case (Hexagon::S2_storew_locked): - case (Hexagon::S4_stored_locked): - case (Hexagon::L2_loadw_locked): - case (Hexagon::L4_loadd_locked): - case (Hexagon::Y4_l2fetch): { + case Hexagon::S2_storew_locked: + case Hexagon::S4_stored_locked: + case Hexagon::L2_loadw_locked: + case Hexagon::L4_loadd_locked: + case Hexagon::Y4_l2fetch: + case Hexagon::Y5_l2fetch: { // These instructions can only be grouped with ALU32 or non-floating-point // XTYPE instructions. Since there is no convenient way of identifying fp // XTYPE instructions, only allow grouping with ALU32 for now. @@ -1166,6 +1175,8 @@ static bool isSystemInstr(const MachineInstr &MI) { switch (Opc) { case Hexagon::Y2_barrier: case Hexagon::Y2_dcfetchbo: + case Hexagon::Y4_l2fetch: + case Hexagon::Y5_l2fetch: return true; } return false; @@ -1496,19 +1507,33 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { // J is first, I is second. bool LoadJ = J.mayLoad(), StoreJ = J.mayStore(); bool LoadI = I.mayLoad(), StoreI = I.mayStore(); - if (StoreJ) { - // Two stores are only allowed on V4+. Load following store is never - // allowed. - if (LoadI && alias(J, I)) { + bool NVStoreJ = HII->isNewValueStore(J); + bool NVStoreI = HII->isNewValueStore(I); + bool IsVecJ = HII->isHVXVec(J); + bool IsVecI = HII->isHVXVec(I); + + if (Slot1Store && MF.getSubtarget<HexagonSubtarget>().hasV65TOps() && + ((LoadJ && StoreI && !NVStoreI) || + (StoreJ && LoadI && !NVStoreJ)) && + (J.getOpcode() != Hexagon::S2_allocframe && + I.getOpcode() != Hexagon::S2_allocframe) && + (J.getOpcode() != Hexagon::L2_deallocframe && + I.getOpcode() != Hexagon::L2_deallocframe) && + (!HII->isMemOp(J) && !HII->isMemOp(I)) && (!IsVecJ && !IsVecI)) + setmemShufDisabled(true); + else + if (StoreJ && LoadI && alias(J, I)) { + FoundSequentialDependence = true; + break; + } + + if (!StoreJ) + if (!LoadJ || (!LoadI && !StoreI)) { + // If J is neither load nor store, assume a dependency. + // If J is a load, but I is neither, also assume a dependency. FoundSequentialDependence = true; break; } - } else if (!LoadJ || (!LoadI && !StoreI)) { - // If J is neither load nor store, assume a dependency. - // If J is a load, but I is neither, also assume a dependency. - FoundSequentialDependence = true; - break; - } // Store followed by store: not OK on V2. // Store followed by load: not OK on all. // Load followed by store: OK on all. @@ -1628,6 +1653,26 @@ bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) { return false; } + +bool HexagonPacketizerList::foundLSInPacket() { + bool FoundLoad = false; + bool FoundStore = false; + + for (auto MJ : CurrentPacketMIs) { + unsigned Opc = MJ->getOpcode(); + if (Opc == Hexagon::S2_allocframe || Opc == Hexagon::L2_deallocframe) + continue; + if (HII->isMemOp(*MJ)) + continue; + if (MJ->mayLoad()) + FoundLoad = true; + if (MJ->mayStore() && !HII->isNewValueStore(*MJ)) + FoundStore = true; + } + return FoundLoad && FoundStore; +} + + MachineBasicBlock::iterator HexagonPacketizerList::addToPacket(MachineInstr &MI) { MachineBasicBlock::iterator MII = MI.getIterator(); @@ -1703,8 +1748,31 @@ HexagonPacketizerList::addToPacket(MachineInstr &MI) { void HexagonPacketizerList::endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) { + // Replace VLIWPacketizerList::endPacket(MBB, MI). + + bool memShufDisabled = getmemShufDisabled(); + if (memShufDisabled && !foundLSInPacket()) { + setmemShufDisabled(false); + DEBUG(dbgs() << " Not added to NoShufPacket\n"); + } + memShufDisabled = getmemShufDisabled(); + + if (CurrentPacketMIs.size() > 1) { + MachineBasicBlock::instr_iterator FirstMI(CurrentPacketMIs.front()); + MachineBasicBlock::instr_iterator LastMI(MI.getInstrIterator()); + finalizeBundle(*MBB, FirstMI, LastMI); + + auto BundleMII = std::prev(FirstMI); + if (memShufDisabled) + HII->setBundleNoShuf(BundleMII); + + setmemShufDisabled(false); + } OldPacketMIs = CurrentPacketMIs; - VLIWPacketizerList::endPacket(MBB, MI); + CurrentPacketMIs.clear(); + + ResourceTracker->clearResources(); + DEBUG(dbgs() << "End packet\n"); } bool HexagonPacketizerList::shouldAddToPacket(const MachineInstr &MI) { diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h index cbdd2367429..764d9ae9059 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h @@ -49,6 +49,8 @@ class HexagonPacketizerList : public VLIWPacketizerList { // schedule this instruction. bool FoundSequentialDependence; + bool MemShufDisabled = false; + // Track MIs with ignored dependence. std::vector<MachineInstr*> IgnoreDepMIs; @@ -89,6 +91,7 @@ public: // and SUJ. bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override; + bool foundLSInPacket(); MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override; void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override; @@ -97,6 +100,12 @@ public: void unpacketizeSoloInstrs(MachineFunction &MF); protected: + bool getmemShufDisabled() { + return MemShufDisabled; + }; + void setmemShufDisabled(bool val) { + MemShufDisabled = val; + }; bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg); bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index 31da9fa06d0..b3ab6763281 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -655,7 +655,8 @@ public: assert(HexagonMCInstrInfo::isBundle(Inst) && "Hexagon relaxInstruction only works on bundles"); - Res = HexagonMCInstrInfo::createBundle(); + Res.setOpcode(Hexagon::BUNDLE); + Res.addOperand(MCOperand::createImm(Inst.getOperand(0).getImm())); // Copy the results into the bundle. bool Update = false; for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) { @@ -769,6 +770,6 @@ MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T, const MCTargetOptions &Options) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); - StringRef CPUString = Hexagon_MC::selectHexagonCPU(TT, CPU); + StringRef CPUString = Hexagon_MC::selectHexagonCPU(CPU); return new HexagonAsmBackend(T, TT, OSABI, CPUString); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index d1a6d38797d..f5a37603375 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -68,8 +68,8 @@ namespace HexagonII { SoloAXPos = 7, SoloAXMask = 0x1, // Only A-type instruction in first slot or nothing. - SoloAin1Pos = 8, - SoloAin1Mask = 0x1, + RestrictSlot1AOKPos = 8, + RestrictSlot1AOKMask = 0x1, // Predicated instructions. PredicatedPos = 9, @@ -122,6 +122,16 @@ namespace HexagonII { ExtentAlignPos = 33, ExtentAlignMask = 0x3, + CofMax1Pos = 35, + CofMax1Mask = 0x1, + CofRelax1Pos = 36, + CofRelax1Mask = 0x1, + CofRelax2Pos = 37, + CofRelax2Mask = 0x1, + + RestrictNoSlot1StorePos = 38, + RestrictNoSlot1StoreMask = 0x1, + // Addressing mode for load/store instructions. AddrModePos = 41, AddrModeMask = 0x7, @@ -152,8 +162,9 @@ namespace HexagonII { PrefersSlot3Pos = 56, PrefersSlot3Mask = 0x1, - CofMax1Pos = 60, - CofMax1Mask = 0x1, + // v65 + HasTmpDstPos = 59, + HasTmpDstMask = 0x1, CVINewPos = 61, CVINewMask = 0x1 diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp index 142070ad73b..53f3cba052b 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp @@ -179,35 +179,6 @@ void HexagonMCChecker::init(MCInst const &MCI) { } } - // Figure out register definitions that produce new values. - if (HexagonMCInstrInfo::hasNewValue(MCII, MCI)) { - unsigned R = HexagonMCInstrInfo::getNewValueOperand(MCII, MCI).getReg(); - - if (HexagonMCInstrInfo::isCompound(MCII, MCI)) - compoundRegisterMap(R); // Compound insns have a limited register range. - - for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); - SRI.isValid(); ++SRI) - if (!MCSubRegIterator(*SRI, &RI).isValid()) - // No super-registers defined indirectly. - NewDefs[*SRI].push_back(NewSense::Def( - PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), - HexagonMCInstrInfo::isFloat(MCII, MCI))); - - // For fairly unique 2-dot-new producers, example: - // vdeal(V1, V9, R0) V1.new and V9.new can be used by consumers. - if (HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) { - unsigned R2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, MCI).getReg(); - - bool HasSubRegs = MCSubRegIterator(R2, &RI).isValid(); - for (MCRegAliasIterator SRI(R2, &RI, !HasSubRegs); SRI.isValid(); ++SRI) - if (!MCSubRegIterator(*SRI, &RI).isValid()) - NewDefs[*SRI].push_back(NewSense::Def( - PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), - HexagonMCInstrInfo::isFloat(MCII, MCI))); - } - } - // Figure out definitions of new predicate registers. if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) @@ -217,21 +188,6 @@ void HexagonMCChecker::init(MCInst const &MCI) { if (isPredicateRegister(P)) NewPreds.insert(P); } - - // Figure out uses of new values. - if (HexagonMCInstrInfo::isNewValue(MCII, MCI)) { - unsigned N = HexagonMCInstrInfo::getNewValueOperand(MCII, MCI).getReg(); - - if (!MCSubRegIterator(N, &RI).isValid()) { - // Super-registers cannot use new values. - if (MCID.isBranch()) - NewUses[N] = NewSense::Jmp( - HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNCJ); - else - NewUses[N] = NewSense::Use( - PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI)); - } - } } HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII, @@ -242,13 +198,17 @@ HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII, init(); } +HexagonMCChecker::HexagonMCChecker(HexagonMCChecker const &Other, + MCSubtargetInfo const &STI, + bool CopyReportErrors) + : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII), + STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false) {} + bool HexagonMCChecker::check(bool FullCheck) { - bool chkB = checkBranches(); bool chkP = checkPredicates(); bool chkNV = checkNewValues(); bool chkR = checkRegisters(); bool chkRRO = checkRegistersReadOnly(); - bool chkELB = checkEndloopBranches(); checkRegisterCurDefs(); bool chkS = checkSolo(); bool chkSh = true; @@ -258,30 +218,14 @@ bool HexagonMCChecker::check(bool FullCheck) { if (FullCheck) chkSl = checkSlots(); bool chkAXOK = checkAXOK(); - bool chk = chkB && chkP && chkNV && chkR && chkRRO && chkELB && chkS && - chkSh && chkSl && chkAXOK; + bool chkCofMax1 = checkCOFMax1(); + bool chkHWLoop = checkHWLoop(); + bool chk = chkP && chkNV && chkR && chkRRO && chkS && chkSh && chkSl && + chkAXOK && chkCofMax1 && chkHWLoop; return chk; } -bool HexagonMCChecker::checkEndloopBranches() { - for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) { - MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); - if (Desc.isBranch() || Desc.isCall()) { - auto Inner = HexagonMCInstrInfo::isInnerLoop(MCB); - if (Inner || HexagonMCInstrInfo::isOuterLoop(MCB)) { - reportError(I.getLoc(), - Twine("packet marked with `:endloop") + - (Inner ? "0" : "1") + "' " + - "cannot contain instructions that modify register " + "`" + - Twine(RI.getName(Hexagon::PC)) + "'"); - return false; - } - } - } - return true; -} - static bool isDuplexAGroup(unsigned Opcode) { switch (Opcode) { case Hexagon::SA1_addi: @@ -355,6 +299,65 @@ bool HexagonMCChecker::checkAXOK() { return true; } +void HexagonMCChecker::reportBranchErrors() { + for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) { + MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); + if (Desc.isBranch() || Desc.isCall() || Desc.isReturn()) + reportNote(I.getLoc(), "Branching instruction"); + } +} + +bool HexagonMCChecker::checkHWLoop() { + if (!HexagonMCInstrInfo::isInnerLoop(MCB) && + !HexagonMCInstrInfo::isOuterLoop(MCB)) + return true; + for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) { + MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); + if (Desc.isBranch() || Desc.isCall() || Desc.isReturn()) { + reportError(MCB.getLoc(), + "Branches cannot be in a packet with hardware loops"); + reportBranchErrors(); + return false; + } + } + return true; +} + +bool HexagonMCChecker::checkCOFMax1() { + SmallVector<MCInst const *, 2> BranchLocations; + for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) { + MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); + if (Desc.isBranch() || Desc.isCall() || Desc.isReturn()) + BranchLocations.push_back(&I); + } + for (unsigned J = 0, N = BranchLocations.size(); J < N; ++J) { + MCInst const &I = *BranchLocations[J]; + if (HexagonMCInstrInfo::isCofMax1(MCII, I)) { + bool Relax1 = HexagonMCInstrInfo::isCofRelax1(MCII, I); + bool Relax2 = HexagonMCInstrInfo::isCofRelax2(MCII, I); + if (N > 1 && !Relax1 && !Relax2) { + reportError(I.getLoc(), + "Instruction may not be in a packet with other branches"); + reportBranchErrors(); + return false; + } + if (N > 1 && J == 0 && !Relax1) { + reportError(I.getLoc(), + "Instruction may not be the first branch in packet"); + reportBranchErrors(); + return false; + } + if (N > 1 && J == 1 && !Relax2) { + reportError(I.getLoc(), + "Instruction may not be the second branch in packet"); + reportBranchErrors(); + return false; + } + } + } + return true; +} + bool HexagonMCChecker::checkSlots() { unsigned slotsUsed = 0; for (auto HMI : HexagonMCInstrInfo::bundleInstructions(MCB)) { @@ -374,45 +377,6 @@ bool HexagonMCChecker::checkSlots() { return true; } -// Check legal use of branches. -bool HexagonMCChecker::checkBranches() { - if (HexagonMCInstrInfo::isBundle(MCB)) { - bool hasConditional = false; - unsigned Branches = 0, Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE, - Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE; - - for (unsigned i = HexagonMCInstrInfo::bundleInstructionsOffset; - i < MCB.size(); ++i) { - MCInst const &MCI = *MCB.begin()[i].getInst(); - - if (HexagonMCInstrInfo::isImmext(MCI)) - continue; - if (HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch() || - HexagonMCInstrInfo::getDesc(MCII, MCI).isCall()) { - ++Branches; - if (HexagonMCInstrInfo::isPredicated(MCII, MCI) || - HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) { - hasConditional = true; - Conditional = i; // Record the position of the conditional branch. - } else { - Unconditional = i; // Record the position of the unconditional branch. - } - } - } - - if (Branches > 1) - if (!hasConditional || Conditional > Unconditional) { - // Error out if more than one unconditional branch or - // the conditional branch appears after the unconditional one. - reportError( - "unconditional branch cannot precede another branch in packet"); - return false; - } - } - - return true; -} - // Check legal use of predicate registers. bool HexagonMCChecker::checkPredicates() { // Check for proper use of new predicate registers. @@ -446,16 +410,85 @@ bool HexagonMCChecker::checkPredicates() { // Check legal use of new values. bool HexagonMCChecker::checkNewValues() { - for (auto &I : NewUses) { - unsigned R = I.first; - NewSense &US = I.second; - - if (!hasValidNewValueDef(US, NewDefs[R])) { - reportErrorNewValue(R); + for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) { + if (!HexagonMCInstrInfo::isNewValue(MCII, I)) + continue; + auto Consumer = HexagonMCInstrInfo::predicateInfo(MCII, I); + bool Branch = HexagonMCInstrInfo::getDesc(MCII, I).isBranch(); + MCOperand const &Op = HexagonMCInstrInfo::getNewValueOperand(MCII, I); + assert(Op.isReg()); + auto Producer = registerProducer(Op.getReg(), Consumer); + if (std::get<0>(Producer) == nullptr) { + reportError(I.getLoc(), "New value register consumer has no producer"); + return false; + } + if (!RelaxNVChecks) { + // Checks that statically prove correct new value consumption + if (std::get<2>(Producer).isPredicated() && + (!Consumer.isPredicated() || + llvm::HexagonMCInstrInfo::getType(MCII, I) == HexagonII::TypeNCJ)) { + reportNote( + std::get<0>(Producer)->getLoc(), + "Register producer is predicated and consumer is unconditional"); + reportError(I.getLoc(), + "Instruction does not have a valid new register producer"); + return false; + } + if (std::get<2>(Producer).Register != Hexagon::NoRegister && + std::get<2>(Producer).Register != Consumer.Register) { + reportNote(std::get<0>(Producer)->getLoc(), + "Register producer does not use the same predicate " + "register as the consumer"); + reportError(I.getLoc(), + "Instruction does not have a valid new register producer"); + return false; + } + } + if (std::get<2>(Producer).Register == Consumer.Register && + Consumer.PredicatedTrue != std::get<2>(Producer).PredicatedTrue) { + reportNote( + std::get<0>(Producer)->getLoc(), + "Register producer has the opposite predicate sense as consumer"); + reportError(I.getLoc(), + "Instruction does not have a valid new register producer"); + return false; + } + MCInstrDesc const &Desc = + HexagonMCInstrInfo::getDesc(MCII, *std::get<0>(Producer)); + if (Desc.OpInfo[std::get<1>(Producer)].RegClass == + Hexagon::DoubleRegsRegClassID) { + reportNote(std::get<0>(Producer)->getLoc(), + "Double registers cannot be new-value producers"); + reportError(I.getLoc(), + "Instruction does not have a valid new register producer"); + return false; + } + if ((Desc.mayLoad() && std::get<1>(Producer) == 1) || + (Desc.mayStore() && std::get<1>(Producer) == 0)) { + unsigned Mode = + HexagonMCInstrInfo::getAddrMode(MCII, *std::get<0>(Producer)); + StringRef ModeError; + if (Mode == HexagonII::AbsoluteSet) + ModeError = "Absolute-set"; + if (Mode == HexagonII::PostInc) + ModeError = "Auto-increment"; + if (!ModeError.empty()) { + reportNote(std::get<0>(Producer)->getLoc(), + ModeError + " registers cannot be a new-value " + "producer"); + reportError(I.getLoc(), + "Instruction does not have a valid new register producer"); + return false; + } + } + if (Branch && HexagonMCInstrInfo::isFloat(MCII, *std::get<0>(Producer))) { + reportNote(std::get<0>(Producer)->getLoc(), + "FPU instructions cannot be new-value producers for jumps"); + reportError(I.getLoc(), + "Instruction does not have a valid new register producer"); return false; } } - return true; } @@ -489,6 +522,34 @@ bool HexagonMCChecker::registerUsed(unsigned Register) { return false; } +std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo> +HexagonMCChecker::registerProducer( + unsigned Register, HexagonMCInstrInfo::PredicateInfo ConsumerPredicate) { + std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo> + WrongSense; + for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) { + MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); + auto ProducerPredicate = HexagonMCInstrInfo::predicateInfo(MCII, I); + for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J) + for (auto K = MCRegAliasIterator(I.getOperand(J).getReg(), &RI, true); + K.isValid(); ++K) + if (*K == Register) { + if (RelaxNVChecks || + (ProducerPredicate.Register == ConsumerPredicate.Register && + (ProducerPredicate.Register == Hexagon::NoRegister || + ProducerPredicate.PredicatedTrue == + ConsumerPredicate.PredicatedTrue))) + return std::make_tuple(&I, J, ProducerPredicate); + std::get<0>(WrongSense) = &I; + std::get<1>(WrongSense) = J; + std::get<2>(WrongSense) = ProducerPredicate; + } + if (Register == Hexagon::VTMP && HexagonMCInstrInfo::hasTmpDst(MCII, I)) + return std::make_tuple(&I, 0, HexagonMCInstrInfo::PredicateInfo()); + } + return WrongSense; +} + void HexagonMCChecker::checkRegisterCurDefs() { for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCB)) { if (HexagonMCInstrInfo::isCVINew(MCII, I) && @@ -638,35 +699,6 @@ void HexagonMCChecker::compoundRegisterMap(unsigned &Register) { } } -bool HexagonMCChecker::hasValidNewValueDef(const NewSense &Use, - const NewSenseList &Defs) const { - bool Strict = !RelaxNVChecks; - - for (unsigned i = 0, n = Defs.size(); i < n; ++i) { - const NewSense &Def = Defs[i]; - // NVJ cannot use a new FP value [7.6.1] - if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0)) - continue; - // If the definition was not predicated, then it does not matter if - // the use is. - if (Def.PredReg == 0) - return true; - // With the strict checks, both the definition and the use must be - // predicated on the same register and condition. - if (Strict) { - if (Def.PredReg == Use.PredReg && Def.Cond == Use.Cond) - return true; - } else { - // With the relaxed checks, if the definition was predicated, the only - // detectable violation is if the use is predicated on the opposing - // condition, otherwise, it's ok. - if (Def.PredReg != Use.PredReg || Def.Cond == Use.Cond) - return true; - } - } - return false; -} - void HexagonMCChecker::reportErrorRegisters(unsigned Register) { reportError("register `" + Twine(RI.getName(Register)) + "' modified more than once"); @@ -687,6 +719,14 @@ void HexagonMCChecker::reportError(SMLoc Loc, Twine const &Msg) { Context.reportError(Loc, Msg); } +void HexagonMCChecker::reportNote(SMLoc Loc, llvm::Twine const &Msg) { + if (ReportErrors) { + auto SM = Context.getSourceManager(); + if (SM) + SM->PrintMessage(Loc, SourceMgr::DK_Note, Msg); + } +} + void HexagonMCChecker::reportWarning(Twine const &Msg) { if (ReportErrors) { auto SM = Context.getSourceManager(); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h index 957950156e8..7577baace20 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h @@ -15,6 +15,7 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H +#include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" @@ -48,40 +49,6 @@ class HexagonMCChecker { using DefsIterator = DenseMap<unsigned, PredSet>::iterator; DenseMap<unsigned, PredSet> Defs; - /// Information about how a new-value register is defined or used: - /// PredReg = predicate register, 0 if use/def not predicated, - /// Cond = true/false for if(PredReg)/if(!PredReg) respectively, - /// IsFloat = true if definition produces a floating point value - /// (not valid for uses), - /// IsNVJ = true if the use is a new-value branch (not valid for - /// definitions). - struct NewSense { - unsigned PredReg; - bool IsFloat, IsNVJ, Cond; - - // The special-case "constructors": - static NewSense Jmp(bool isNVJ) { - NewSense NS = {/*PredReg=*/0, /*IsFloat=*/false, /*IsNVJ=*/isNVJ, - /*Cond=*/false}; - return NS; - } - static NewSense Use(unsigned PR, bool True) { - NewSense NS = {/*PredReg=*/PR, /*IsFloat=*/false, /*IsNVJ=*/false, - /*Cond=*/True}; - return NS; - } - static NewSense Def(unsigned PR, bool True, bool Float) { - NewSense NS = {/*PredReg=*/PR, /*IsFloat=*/Float, /*IsNVJ=*/false, - /*Cond=*/True}; - return NS; - } - }; - - /// Set of definitions that produce new register: - using NewSenseList = SmallVector<NewSense, 2>; - using NewDefsIterator = DenseMap<unsigned, NewSenseList>::iterator; - DenseMap<unsigned, NewSenseList> NewDefs; - /// Set of weak definitions whose clashes should be enforced selectively. using SoftDefsIterator = std::set<unsigned>::iterator; std::set<unsigned> SoftDefs; @@ -102,10 +69,6 @@ class HexagonMCChecker { using UsesIterator = std::set<unsigned>::iterator; std::set<unsigned> Uses; - /// Set of new values used: new register, if new-value jump. - using NewUsesIterator = DenseMap<unsigned, NewSense>::iterator; - DenseMap<unsigned, NewSense> NewUses; - /// Pre-defined set of read-only registers. using ReadOnlyIterator = std::set<unsigned>::iterator; std::set<unsigned> ReadOnly; @@ -115,6 +78,9 @@ class HexagonMCChecker { void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue); bool registerUsed(unsigned Register); + std::tuple<MCInst const *, unsigned, HexagonMCInstrInfo::PredicateInfo> + registerProducer(unsigned Register, + HexagonMCInstrInfo::PredicateInfo Predicated); // Checks performed. bool checkBranches(); @@ -122,12 +88,13 @@ class HexagonMCChecker { bool checkNewValues(); bool checkRegisters(); bool checkRegistersReadOnly(); - bool checkEndloopBranches(); void checkRegisterCurDefs(); bool checkSolo(); bool checkShuffle(); bool checkSlots(); bool checkAXOK(); + bool checkHWLoop(); + bool checkCOFMax1(); static void compoundRegisterMap(unsigned &); @@ -141,19 +108,21 @@ class HexagonMCChecker { Hexagon::LC1 == R); } - bool hasValidNewValueDef(const NewSense &Use, const NewSenseList &Defs) const; - public: explicit HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &mcb, const MCRegisterInfo &ri, bool ReportErrors = true); + explicit HexagonMCChecker(HexagonMCChecker const &Check, + MCSubtargetInfo const &STI, bool CopyReportErrors); bool check(bool FullCheck = true); void reportErrorRegisters(unsigned Register); void reportErrorNewValue(unsigned Register); void reportError(SMLoc Loc, Twine const &Msg); + void reportNote(SMLoc Loc, Twine const &Msg); void reportError(Twine const &Msg); void reportWarning(Twine const &Msg); + void reportBranchErrors(); }; } // end namespace llvm diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp index c5f3d434759..4c18af60efd 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp @@ -305,7 +305,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) { case Hexagon::L4_return_tnew_pt: case Hexagon::L4_return_fnew_pt: // [if ([!]p0[.new])] dealloc_return - SrcReg = MCI.getOperand(0).getReg(); + SrcReg = MCI.getOperand(1).getReg(); if (Hexagon::P0 == SrcReg) { return HexagonII::HSIG_L2; } @@ -388,7 +388,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) { } break; case Hexagon::S2_allocframe: - if (inRange<5, 3>(MCI, 0)) + if (inRange<5, 3>(MCI, 2)) return HexagonII::HSIG_S2; break; // @@ -742,7 +742,7 @@ MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) { break; // 1,2,3 SUBInst $Rx = add($_src_, $Rs) case Hexagon::S2_allocframe: Result.setOpcode(Hexagon::SS2_allocframe); - addOps(Result, Inst, 0); + addOps(Result, Inst, 2); break; // 1 SUBInst allocframe(#$u5_3) case Hexagon::A2_andir: if (minConstant(Inst, 2) == 255) { diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp index 94919b1e486..19308cd425e 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp @@ -33,6 +33,10 @@ using namespace llvm; +bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const { + return Register != Hexagon::NoRegister; +} + Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst) : MCII(MCII), BundleCurrent(Inst.begin() + @@ -50,6 +54,7 @@ Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() { if (DuplexCurrent == DuplexEnd) { DuplexCurrent = BundleEnd; DuplexEnd = BundleEnd; + ++BundleCurrent; } return *this; } @@ -90,6 +95,7 @@ void HexagonMCInstrInfo::addConstExtender(MCContext &Context, // Create the extender. MCInst *XMCI = new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp)); + XMCI->setLoc(MCI.getLoc()); MCB.addOperand(MCOperand::createInst(XMCI)); } @@ -131,7 +137,7 @@ bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII, // Examine the packet and convert pairs of instructions to duplex // instructions when possible. MCInst InstBundlePreDuplex = MCInst(MCB); - if (!HexagonDisableDuplex) { + if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) { SmallVector<DuplexCandidate, 8> possibleDuplexes; possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(MCII, STI, MCB); @@ -169,13 +175,6 @@ void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII, } } -MCInst HexagonMCInstrInfo::createBundle() { - MCInst Result; - Result.setOpcode(Hexagon::BUNDLE); - Result.addOperand(MCOperand::createImm(0)); - return Result; -} - MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO) { @@ -233,6 +232,13 @@ unsigned HexagonMCInstrInfo::getMemAccessSize(MCInstrInfo const &MCII, return HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(S)); } +unsigned HexagonMCInstrInfo::getAddrMode(MCInstrInfo const &MCII, + MCInst const &MCI) { + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return static_cast<unsigned>((F >> HexagonII::AddrModePos) & + HexagonII::AddrModeMask); +} + MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, MCInst const &MCI) { return MCII.get(MCI.getOpcode()); @@ -365,13 +371,20 @@ unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII, MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI) { - unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI); - MCOperand const &MCO = MCI.getOperand(O); - - assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) || - HexagonMCInstrInfo::hasNewValue(MCII, MCI)) && - MCO.isReg()); - return (MCO); + if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) { + // VTMP doesn't actually exist in the encodings for these 184 + // 3 instructions so go ahead and create it here. + static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP); + return (MCO); + } else { + unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI); + MCOperand const &MCO = MCI.getOperand(O); + + assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) || + HexagonMCInstrInfo::hasNewValue(MCII, MCI)) && + MCO.isReg()); + return (MCO); + } } /// Return the new value or the newly produced value. @@ -439,8 +452,8 @@ bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) { if (!HexagonMCInstrInfo::isBundle(MCI)) return false; - for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCI)) { - if (HexagonMCInstrInfo::isDuplex(MCII, I)) + for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) { + if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst())) return true; } @@ -451,7 +464,7 @@ bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) { return extenderForIndex(MCB, Index) != nullptr; } -bool HexagonMCInstrInfo::hasImmExt( MCInst const &MCI) { +bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) { if (!HexagonMCInstrInfo::isBundle(MCI)) return false; @@ -540,6 +553,18 @@ bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) { return ((F >> HexagonII::CofMax1Pos) & HexagonII::CofMax1Mask); } +bool HexagonMCInstrInfo::isCofRelax1(MCInstrInfo const &MCII, + MCInst const &MCI) { + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return ((F >> HexagonII::CofRelax1Pos) & HexagonII::CofRelax1Mask); +} + +bool HexagonMCInstrInfo::isCofRelax2(MCInstrInfo const &MCII, + MCInst const &MCI) { + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return ((F >> HexagonII::CofRelax2Pos) & HexagonII::CofRelax2Mask); +} + bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII, MCInst const &MCI) { return (getType(MCII, MCI) == HexagonII::TypeCJ); @@ -576,6 +601,11 @@ bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) { return ((F >> HexagonII::FPPos) & HexagonII::FPMask); } +bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) { + const uint64_t V = getType(MCII, MCI); + return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST; +} + bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) { return MCI.getOpcode() == Hexagon::A4_ext; } @@ -655,10 +685,18 @@ bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) { } /// Return whether the insn can be packaged only with an A-type insn in slot #1. -bool HexagonMCInstrInfo::isSoloAin1(MCInstrInfo const &MCII, - MCInst const &MCI) { +bool HexagonMCInstrInfo::isRestrictSlot1AOK(MCInstrInfo const &MCII, + MCInst const &MCI) { const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - return ((F >> HexagonII::SoloAin1Pos) & HexagonII::SoloAin1Mask); + return ((F >> HexagonII::RestrictSlot1AOKPos) & + HexagonII::RestrictSlot1AOKMask); +} + +bool HexagonMCInstrInfo::isRestrictNoSlot1Store(MCInstrInfo const &MCII, + MCInst const &MCI) { + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return ((F >> HexagonII::RestrictNoSlot1StorePos) & + HexagonII::RestrictNoSlot1StoreMask); } /// Return whether the insn is solo, i.e., cannot be in a packet. @@ -673,12 +711,6 @@ bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) { return (Flags & memReorderDisabledMask) != 0; } -bool HexagonMCInstrInfo::isMemStoreReorderEnabled(MCInst const &MCI) { - assert(isBundle(MCI)); - auto Flags = MCI.getOperand(0).getImm(); - return (Flags & memStoreReorderEnabledMask) != 0; -} - bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) { switch (MCI.getOpcode()) { default: @@ -800,12 +832,29 @@ void HexagonMCInstrInfo::padEndloop(MCInst &MCB, MCContext &Context) { MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop))); } +HexagonMCInstrInfo::PredicateInfo +HexagonMCInstrInfo::predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI) { + if (!isPredicated(MCII, MCI)) + return {0, 0, false}; + MCInstrDesc const &Desc = getDesc(MCII, MCI); + for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I) + if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID) + return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)}; + return {0, 0, false}; +} + bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI) { const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; return (F >> HexagonII::PrefersSlot3Pos) & HexagonII::PrefersSlot3Mask; } +/// return true if instruction has hasTmpDst attribute. +bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) { + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return (F >> HexagonII::HasTmpDstPos) & HexagonII::HasTmpDstMask; +} + void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB, DuplexCandidate Candidate) { assert(Candidate.packetIndexI < MCB.size()); @@ -833,13 +882,6 @@ void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) { assert(isMemReorderDisabled(MCI)); } -void HexagonMCInstrInfo::setMemStoreReorderEnabled(MCInst &MCI) { - assert(isBundle(MCI)); - MCOperand &Operand = MCI.getOperand(0); - Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask); - assert(isMemStoreReorderEnabled(MCI)); -} - void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) { assert(isBundle(MCI)); MCOperand &Operand = MCI.getOperand(0); @@ -854,7 +896,7 @@ unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer, if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31) return (Consumer - Hexagon::V0) & 0x1; - if (Consumer == Producer2) - return 0x1; + if (Producer2 != Hexagon::NoRegister) + return Consumer == Producer; return 0; } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h index b6b01709a6c..28d89429266 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h @@ -75,10 +75,6 @@ int64_t const outerLoopMask = 1 << outerLoopOffset; size_t const memReorderDisabledOffset = 2; int64_t const memReorderDisabledMask = 1 << memReorderDisabledOffset; -// allow re-ordering of memory stores by default stores cannot be re-ordered -size_t const memStoreReorderEnabledOffset = 3; -int64_t const memStoreReorderEnabledMask = 1 << memStoreReorderEnabledOffset; - size_t const bundleInstructionsOffset = 1; void addConstant(MCInst &MI, uint64_t Value, MCContext &Context); @@ -110,8 +106,6 @@ MCInst deriveSubInst(MCInst const &Inst); // Clamp off upper 26 bits of extendable operand for emission void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI); -MCInst createBundle(); - // Return the extender for instruction at Index or nullptr if none MCInst const *extenderForIndex(MCInst const &MCB, size_t Index); void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, @@ -120,6 +114,9 @@ void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, // Return memory access size in bytes unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI); +// Return memory access size +unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI); + MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI); // Return which duplex group this instruction belongs to @@ -184,6 +181,7 @@ bool hasImmExt(MCInst const &MCI); // Return whether the instruction is a legal new-value producer. bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI); bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI); +bool hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI); unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb); int64_t minConstant(MCInst const &MCI, size_t Index); @@ -209,6 +207,8 @@ bool isBundle(MCInst const &MCI); // Return whether the insn is an actual insn. bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI); bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI); +bool isCofRelax1(MCInstrInfo const &MCII, MCInst const &MCI); +bool isCofRelax2(MCInstrInfo const &MCII, MCInst const &MCI); bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI); // Return whether the instruction needs to be constant extended. @@ -236,6 +236,8 @@ bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI); /// Return whether it is a floating-point insn. bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI); +bool isHVX(MCInstrInfo const &MCII, MCInst const &MCI); + // Returns whether this instruction is an immediate extender bool isImmext(MCInst const &MCI); @@ -248,7 +250,6 @@ bool isIntReg(unsigned Reg); // Is this register suitable for use in a duplex subinst bool isIntRegForSubInst(unsigned Reg); bool isMemReorderDisabled(MCInst const &MCI); -bool isMemStoreReorderEnabled(MCInst const &MCI); // Return whether the insn is a new-value consumer. bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI); @@ -283,7 +284,8 @@ bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI); bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI); /// Return whether the insn can be packaged only with an A-type insn in slot #1. -bool isSoloAin1(MCInstrInfo const &MCII, MCInst const &MCI); +bool isRestrictSlot1AOK(MCInstrInfo const &MCII, MCInst const &MCI); +bool isRestrictNoSlot1Store(MCInstrInfo const &MCII, MCInst const &MCI); bool isSubInstruction(MCInst const &MCI); bool isVector(MCInstrInfo const &MCII, MCInst const &MCI); bool mustExtend(MCExpr const &Expr); @@ -291,6 +293,17 @@ bool mustNotExtend(MCExpr const &Expr); // Pad the bundle with nops to satisfy endloop requirements void padEndloop(MCInst &MCI, MCContext &Context); +class PredicateInfo { +public: + PredicateInfo() : Register(0), Operand(0), PredicatedTrue(false) {} + PredicateInfo(unsigned Register, unsigned Operand, bool PredicatedTrue) + : Register(Register), Operand(Operand), PredicatedTrue(PredicatedTrue) {} + bool isPredicated() const; + unsigned Register; + unsigned Operand; + bool PredicatedTrue; +}; +PredicateInfo predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI); bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI); // Replace the instructions inside MCB, represented by Candidate @@ -300,7 +313,6 @@ bool s27_2_reloc(MCExpr const &Expr); // Marks a bundle as endloop0 void setInnerLoop(MCInst &MCI); void setMemReorderDisabled(MCInst &MCI); -void setMemStoreReorderEnabled(MCInst &MCI); void setMustExtend(MCExpr const &Expr, bool Val = true); void setMustNotExtend(MCExpr const &Expr, bool Val = true); void setS27_2_reloc(MCExpr const &Expr, bool Val = true); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 6f48169be8c..c6f67d64b22 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -13,11 +13,13 @@ #include "MCTargetDesc/HexagonMCTargetDesc.h" #include "Hexagon.h" +#include "HexagonDepArch.h" #include "HexagonTargetStreamer.h" #include "MCTargetDesc/HexagonInstPrinter.h" #include "MCTargetDesc/HexagonMCAsmInfo.h" #include "MCTargetDesc/HexagonMCELFStreamer.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCAsmBackend.h" @@ -57,41 +59,55 @@ cl::opt<bool> llvm::HexagonDisableDuplex ("mno-pairing", cl::desc("Disable looking for duplex instructions for Hexagon")); -static cl::opt<bool> HexagonV4ArchVariant("mv4", cl::Hidden, cl::init(false), - cl::desc("Build for Hexagon V4")); +namespace { // These flags are to be deprecated +cl::opt<bool> MV4("mv4", cl::Hidden, cl::desc("Build for Hexagon V4"), + cl::init(false)); +cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"), + cl::init(false)); +cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"), + cl::init(false)); +cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"), + cl::init(false)); +cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"), + cl::init(false)); +cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"), + cl::init(false)); +} // namespace + +cl::opt<Hexagon::ArchEnum> + EnableHVX("mhvx", + cl::desc("Enable Hexagon Vector eXtensions"), + cl::values( + clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"), + clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"), + clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"), + // Sentinal for no value specified + clEnumValN(Hexagon::ArchEnum::V5, "", "")), + // Sentinal for flag not present + cl::init(Hexagon::ArchEnum::V4), cl::ValueOptional); +static cl::opt<bool> + DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions")); -static cl::opt<bool> HexagonV5ArchVariant("mv5", cl::Hidden, cl::init(false), - cl::desc("Build for Hexagon V5")); - -static cl::opt<bool> HexagonV55ArchVariant("mv55", cl::Hidden, cl::init(false), - cl::desc("Build for Hexagon V55")); - -static cl::opt<bool> HexagonV60ArchVariant("mv60", cl::Hidden, cl::init(false), - cl::desc("Build for Hexagon V60")); - -static cl::opt<bool> HexagonV62ArchVariant("mv62", cl::Hidden, cl::init(false), - cl::desc("Build for Hexagon V62")); - -static cl::opt<bool> EnableHVX("mhvx", cl::Hidden, cl::init(false), - cl::desc("Enable Hexagon Vector Extension (HVX)")); static StringRef DefaultArch = "hexagonv60"; static StringRef HexagonGetArchVariant() { - if (HexagonV4ArchVariant) + if (MV4) return "hexagonv4"; - if (HexagonV5ArchVariant) + if (MV5) return "hexagonv5"; - if (HexagonV55ArchVariant) + if (MV55) return "hexagonv55"; - if (HexagonV60ArchVariant) + if (MV60) return "hexagonv60"; - if (HexagonV62ArchVariant) + if (MV62) return "hexagonv62"; + if (MV65) + return "hexagonv65"; return ""; } -StringRef Hexagon_MC::selectHexagonCPU(const Triple &TT, StringRef CPU) { +StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) { StringRef ArchV = HexagonGetArchVariant(); if (!ArchV.empty() && !CPU.empty()) { if (ArchV != CPU) @@ -146,7 +162,11 @@ public: OS << Indent << InstTxt << Separator; HeadTail = HeadTail.second.split('\n'); } - OS << "\t}" << PacketBundle.second; + + if (HexagonMCInstrInfo::isMemReorderDisabled(Inst)) + OS << "\n\t}:mem_noshuf" << PacketBundle.second; + else + OS << "\t}" << PacketBundle.second; } }; @@ -251,15 +271,37 @@ static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo* STI, uint64_t F) return (FB & (1ULL << F)) != 0; } -StringRef Hexagon_MC::ParseHexagonTriple(const Triple &TT, StringRef CPU) { - StringRef CPUName = Hexagon_MC::selectHexagonCPU(TT, CPU); - StringRef FS = ""; - if (EnableHVX) { - if (CPUName.equals_lower("hexagonv60") || - CPUName.equals_lower("hexagonv62")) - FS = "+hvx"; +namespace { +std::string selectHexagonFS(StringRef CPU, StringRef FS) { + SmallVector<StringRef, 3> Result; + if (!FS.empty()) + Result.push_back(FS); + + switch (EnableHVX) { + case Hexagon::ArchEnum::V55: + break; + case Hexagon::ArchEnum::V60: + Result.push_back("+hvxv60"); + break; + case Hexagon::ArchEnum::V62: + Result.push_back("+hvxv62"); + break; + case Hexagon::ArchEnum::V65: + Result.push_back("+hvxv65"); + break; + case Hexagon::ArchEnum::V5:{ + Result.push_back(StringSwitch<StringRef>(CPU) + .Case("hexagonv60", "+hvxv60") + .Case("hexagonv62", "+hvxv62") + .Case("hexagonv65", "+hvxv65")); + break; } - return FS; + case Hexagon::ArchEnum::V4: + // Sentinal if -mhvx isn't specified + break; + } + return join(Result.begin(), Result.end(), ","); +} } static bool isCPUValid(std::string CPU) @@ -271,16 +313,76 @@ static bool isCPUValid(std::string CPU) "hexagonv55", "hexagonv60", "hexagonv62", + "hexagonv65", }; return std::find(table.begin(), table.end(), CPU) != table.end(); } +namespace { +std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU, + StringRef FS) { + std::pair<std::string, std::string> Result; + Result.first = Hexagon_MC::selectHexagonCPU(CPU); + Result.second = selectHexagonFS(Result.first, FS); + return Result; +} +} + +FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { + using namespace Hexagon; + // Make sure that +hvx-length turns hvx on, and that "hvx" alone + // turns on hvxvNN, corresponding to the existing ArchVNN. + FeatureBitset FB = S; + unsigned CpuArch = ArchV4; + for (unsigned F : {ArchV65, ArchV62, ArchV60, ArchV55, ArchV5, ArchV4}) { + if (!FB.test(F)) + continue; + CpuArch = F; + break; + } + bool UseHvx = false; + for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B, + ExtensionHVXDbl}) { + if (!FB.test(F)) + continue; + UseHvx = true; + break; + } + bool HasHvxVer = false; + for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65}) { + if (!FB.test(F)) + continue; + HasHvxVer = true; + UseHvx = true; + break; + } + + if (!UseHvx || HasHvxVer) + return FB; + + // HasHvxVer is false, and UseHvx is true. + switch (CpuArch) { + case ArchV60: + FB.set(ExtensionHVXV60); + break; + case ArchV62: + FB.set(ExtensionHVXV62); + break; + case ArchV65: + FB.set(ExtensionHVXV65); + break; + } + return FB; +} + MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { - StringRef ArchFS = (FS.size()) ? FS : Hexagon_MC::ParseHexagonTriple(TT, CPU); - StringRef CPUName = Hexagon_MC::selectHexagonCPU(TT, CPU); + std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS); + StringRef CPUName = Features.first; + StringRef ArchFS = Features.second; + if (!isCPUValid(CPUName.str())) { errs() << "error: invalid CPU \"" << CPUName.str().c_str() << "\" specified\n"; @@ -288,10 +390,12 @@ MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT, } MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS); - if (X->getFeatureBits()[Hexagon::ExtensionHVX128B]) { + if (HexagonDisableDuplex) { llvm::FeatureBitset Features = X->getFeatureBits(); - X->setFeatureBits(Features.set(Hexagon::ExtensionHVX)); + X->setFeatureBits(Features.set(Hexagon::FeatureDuplex, false)); } + + X->setFeatureBits(completeHVXFeatures(X->getFeatureBits())); return X; } @@ -302,6 +406,7 @@ unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { {"hexagonv55", ELF::EF_HEXAGON_MACH_V55}, {"hexagonv60", ELF::EF_HEXAGON_MACH_V60}, {"hexagonv62", ELF::EF_HEXAGON_MACH_V62}, + {"hexagonv65", ELF::EF_HEXAGON_MACH_V65}, }; auto F = ElfFlags.find(STI.getCPU()); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h index 30d75dbc84e..e53208fffee 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -16,11 +16,13 @@ #include "llvm/Support/CommandLine.h" #include <cstdint> +#include <string> namespace llvm { struct InstrItinerary; struct InstrStage; +class FeatureBitset; class MCAsmBackend; class MCCodeEmitter; class MCContext; @@ -44,9 +46,9 @@ MCInstrInfo *createHexagonMCInstrInfo(); MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT); namespace Hexagon_MC { - StringRef ParseHexagonTriple(const Triple &TT, StringRef CPU); - StringRef selectHexagonCPU(const Triple &TT, StringRef CPU); + StringRef selectHexagonCPU(StringRef CPU); + FeatureBitset completeHVXFeatures(const FeatureBitset &FB); /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser, /// etc. do not need to go through TargetRegistry. MCSubtargetInfo *createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index 375a0bde32c..7709a0f6162 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -27,6 +27,7 @@ #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" #include <algorithm> #include <cassert> @@ -115,6 +116,7 @@ void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) { (*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1); (*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2); (*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1); + (*TUL)[HexagonII::TypeCVI_VS_VX] = UnitsAndLanes(CVI_XLANE | CVI_SHIFT, 1); (*TUL)[HexagonII::TypeCVI_VINLANESAT] = (CPU == "hexagonv60") ? UnitsAndLanes(CVI_SHIFT, 1) @@ -128,6 +130,14 @@ void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) { (*TUL)[HexagonII::TypeCVI_VM_NEW_ST] = UnitsAndLanes(CVI_NONE, 0); (*TUL)[HexagonII::TypeCVI_VM_STU] = UnitsAndLanes(CVI_XLANE, 1); (*TUL)[HexagonII::TypeCVI_HIST] = UnitsAndLanes(CVI_XLANE, 4); + (*TUL)[HexagonII::TypeCVI_GATHER] = + UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); + (*TUL)[HexagonII::TypeCVI_SCATTER] = + UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); + (*TUL)[HexagonII::TypeCVI_SCATTER_DV] = + UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2); + (*TUL)[HexagonII::TypeCVI_SCATTER_NEW_ST] = + UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); } HexagonCVIResource::HexagonCVIResource(TypeUnitsAndLanes *TUL, @@ -211,30 +221,89 @@ static struct { } jumpSlots[] = {{8, 4}, {8, 2}, {8, 1}, {4, 2}, {4, 1}, {2, 1}}; #define MAX_JUMP_SLOTS (sizeof(jumpSlots) / sizeof(jumpSlots[0])) +void HexagonShuffler::restrictSlot1AOK() { + bool HasRestrictSlot1AOK = false; + SMLoc RestrictLoc; + for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { + MCInst const &Inst = ISJ->getDesc(); + if (HexagonMCInstrInfo::isRestrictSlot1AOK(MCII, Inst)) { + HasRestrictSlot1AOK = true; + RestrictLoc = Inst.getLoc(); + } + } + if (HasRestrictSlot1AOK) + for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { + MCInst const &Inst = ISJ->getDesc(); + unsigned Type = HexagonMCInstrInfo::getType(MCII, Inst); + if (Type != HexagonII::TypeALU32_2op && + Type != HexagonII::TypeALU32_3op && + Type != HexagonII::TypeALU32_ADDI) { + unsigned Units = ISJ->Core.getUnits(); + if (Units & 2U) { + AppliedRestrictions.push_back(std::make_pair( + Inst.getLoc(), + "Instruction was restricted from being in slot 1")); + AppliedRestrictions.push_back( + std::make_pair(RestrictLoc, "Instruction can only be combine " + "with an ALU instruction in slot 1")); + ISJ->Core.setUnits(Units & ~2U); + } + } + } +} + +void HexagonShuffler::restrictNoSlot1Store() { + bool HasRestrictNoSlot1Store = false; + SMLoc RestrictLoc; + for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { + MCInst const &Inst = ISJ->getDesc(); + if (HexagonMCInstrInfo::isRestrictNoSlot1Store(MCII, Inst)) { + HasRestrictNoSlot1Store = true; + RestrictLoc = Inst.getLoc(); + } + } + if (HasRestrictNoSlot1Store) { + bool AppliedRestriction = false; + for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { + MCInst const &Inst = ISJ->getDesc(); + if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { + unsigned Units = ISJ->Core.getUnits(); + if (Units & 2U) { + AppliedRestriction = true; + AppliedRestrictions.push_back(std::make_pair( + Inst.getLoc(), + "Instruction was restricted from being in slot 1")); + ISJ->Core.setUnits(Units & ~2U); + } + } + } + if (AppliedRestriction) + AppliedRestrictions.push_back(std::make_pair( + RestrictLoc, "Instruction does not allow a store in slot 1")); + } +} + +void HexagonShuffler::applySlotRestrictions() { + restrictSlot1AOK(); + restrictNoSlot1Store(); +} + /// Check that the packet is legal and enforce relative insn order. bool HexagonShuffler::check() { // Descriptive slot masks. - const unsigned slotSingleLoad = 0x1, slotSingleStore = 0x1, slotOne = 0x2, + const unsigned slotSingleLoad = 0x1, slotSingleStore = 0x1, slotThree = 0x8, // slotFirstJump = 0x8, slotFirstLoadStore = 0x2, slotLastLoadStore = 0x1; // Highest slots for branches and stores used to keep their original order. // unsigned slotJump = slotFirstJump; unsigned slotLoadStore = slotFirstLoadStore; - // Number of branches, solo branches, indirect branches. - unsigned jumps = 0, jump1 = 0; // Number of memory operations, loads, solo loads, stores, solo stores, single // stores. unsigned memory = 0, loads = 0, load0 = 0, stores = 0, store0 = 0, store1 = 0; // Number of duplex insns unsigned duplex = 0; - // Number of insns restricting other insns in slot #1 to A type. - unsigned onlyAin1 = 0; - // Number of insns restricting any insn in slot #1, except A2_nop. - unsigned onlyNo1 = 0; unsigned pSlot3Cnt = 0; - unsigned nvstores = 0; unsigned memops = 0; - unsigned deallocs = 0; iterator slot3ISJ = end(); std::vector<iterator> foundBranches; unsigned reservedSlots = 0; @@ -243,15 +312,11 @@ bool HexagonShuffler::check() { for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { MCInst const &ID = ISJ->getDesc(); - if (HexagonMCInstrInfo::isSoloAin1(MCII, ID)) - ++onlyAin1; if (HexagonMCInstrInfo::prefersSlot3(MCII, ID)) { ++pSlot3Cnt; slot3ISJ = ISJ; } reservedSlots |= HexagonMCInstrInfo::getOtherReservedSlots(MCII, STI, ID); - if (HexagonMCInstrInfo::isCofMax1(MCII, ID)) - ++jump1; switch (HexagonMCInstrInfo::getType(MCII, ID)) { case HexagonII::TypeS_2op: @@ -259,30 +324,30 @@ bool HexagonShuffler::check() { case HexagonII::TypeALU64: break; case HexagonII::TypeJ: - ++jumps; foundBranches.push_back(ISJ); break; case HexagonII::TypeCVI_VM_VP_LDU: - ++onlyNo1; - LLVM_FALLTHROUGH; case HexagonII::TypeCVI_VM_LD: case HexagonII::TypeCVI_VM_TMP_LD: + case HexagonII::TypeCVI_GATHER: + case HexagonII::TypeCVI_GATHER_RST: case HexagonII::TypeLD: ++loads; ++memory; if (ISJ->Core.getUnits() == slotSingleLoad || HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_VP_LDU) ++load0; - if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) { - ++deallocs, ++jumps, ++jump1; // DEALLOC_RETURN is of type LD. + if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) foundBranches.push_back(ISJ); - } break; case HexagonII::TypeCVI_VM_STU: - ++onlyNo1; - LLVM_FALLTHROUGH; case HexagonII::TypeCVI_VM_ST: case HexagonII::TypeCVI_VM_NEW_ST: + case HexagonII::TypeCVI_SCATTER: + case HexagonII::TypeCVI_SCATTER_DV: + case HexagonII::TypeCVI_SCATTER_RST: + case HexagonII::TypeCVI_SCATTER_NEW_RST: + case HexagonII::TypeCVI_SCATTER_NEW_ST: case HexagonII::TypeST: ++stores; ++memory; @@ -299,7 +364,6 @@ bool HexagonShuffler::check() { break; case HexagonII::TypeNCJ: ++memory; // NV insns are memory-like. - ++jumps, ++jump1; foundBranches.push_back(ISJ); break; case HexagonII::TypeV2LDST: @@ -314,65 +378,35 @@ bool HexagonShuffler::check() { assert(HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()); ++memory; ++stores; - if (HexagonMCInstrInfo::isNewValue(MCII, ID)) - ++nvstores; } break; case HexagonII::TypeCR: // Legacy conditional branch predicated on a register. case HexagonII::TypeCJ: - if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) { - ++jumps; + if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) foundBranches.push_back(ISJ); - } break; case HexagonII::TypeDUPLEX: { ++duplex; MCInst const &Inst0 = *ID.getOperand(0).getInst(); MCInst const &Inst1 = *ID.getOperand(1).getInst(); - if (HexagonMCInstrInfo::isCofMax1(MCII, Inst0)) - ++jump1; - if (HexagonMCInstrInfo::isCofMax1(MCII, Inst1)) - ++jump1; - if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isBranch()) { - ++jumps; + if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isBranch()) foundBranches.push_back(ISJ); - } - if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isBranch()) { - ++jumps; + if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isBranch()) foundBranches.push_back(ISJ); - } - if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isReturn()) { - ++deallocs, ++jumps, ++jump1; // DEALLOC_RETURN is of type LD. + if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isReturn()) foundBranches.push_back(ISJ); - } - if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isReturn()) { - ++deallocs, ++jumps, ++jump1; // DEALLOC_RETURN is of type LD. + if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isReturn()) foundBranches.push_back(ISJ); - } break; } } } + applySlotRestrictions(); // Check if the packet is legal. - if ((load0 > 1 || store0 > 1) || - (duplex > 1 || (duplex && memory))) { - reportError(Twine("invalid instruction packet")); - return false; - } - - if (jump1 && jumps > 1) { - // Error if single branch with another branch. - reportError(Twine("too many branches in packet")); - return false; - } - if ((nvstores || memops) && stores > 1) { - reportError(Twine("slot 0 instruction does not allow slot 1 store")); - return false; - } - if (deallocs && stores) { - reportError(Twine("slot 0 instruction does not allow slot 1 store")); + if ((load0 > 1 || store0 > 1) || (duplex > 1 || (duplex && memory))) { + reportError(llvm::Twine("invalid instruction packet")); return false; } @@ -387,31 +421,46 @@ bool HexagonShuffler::check() { return false; } - // Exclude from slot #1 any insn but A2_nop. - if (HexagonMCInstrInfo::getDesc(MCII, ID).getOpcode() != Hexagon::A2_nop) - if (onlyNo1) - ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne); - - // Exclude from slot #1 any insn but A-type. - if (HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_2op && - HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_3op && - HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_ADDI) - if (onlyAin1) - ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne); - // A single load must use slot #0. if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { if (loads == 1 && loads == memory && memops == 0) // Pin the load to slot #0. - ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad); + switch (ID.getOpcode()) { + case Hexagon::V6_vgathermw: + case Hexagon::V6_vgathermh: + case Hexagon::V6_vgathermhw: + case Hexagon::V6_vgathermwq: + case Hexagon::V6_vgathermhq: + case Hexagon::V6_vgathermhwq: + // Slot1 only loads + break; + default: + ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad); + break; + } + else if (loads >= 1 && isMemReorderDisabled()) { // }:mem_noshuf + // Loads must keep the original order ONLY if + // isMemReorderDisabled() == true + if (slotLoadStore < slotLastLoadStore) { + // Error if no more slots available for loads. + reportError( + llvm::Twine("invalid instruction packet: too many loads")); + return false; + } + // Pin the load to the highest slot available to it. + ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore); + // Update the next highest slot available to loads. + slotLoadStore >>= 1; + } } // A single store must use slot #0. if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { if (!store0) { - if (stores == 1) + if (stores == 1 && (loads == 0 || !isMemReorderDisabled())) + // Pin the store to slot #0 only if isMemReorderDisabled() == false ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleStore); - else if (stores > 1) { + else if (stores >= 1) { if (slotLoadStore < slotLastLoadStore) { // Error if no more slots available for stores. reportError(Twine("invalid instruction packet: too many stores")); @@ -443,7 +492,7 @@ bool HexagonShuffler::check() { // preserve branch order bool validateSlots = true; - if (jumps > 1) { + if (foundBranches.size() > 1) { if (foundBranches.size() > 2) { reportError(Twine("too many branches in packet")); return false; @@ -487,7 +536,8 @@ bool HexagonShuffler::check() { } } - if (jumps <= 1 && !bOnlySlot3 && pSlot3Cnt == 1 && slot3ISJ != end()) { + if (foundBranches.size() <= 1 && bOnlySlot3 == false && pSlot3Cnt == 1 && + slot3ISJ != end()) { validateSlots = true; // save off slot mask of instruction marked with A_PREFER_SLOT3 // and then pin it to slot #3 @@ -604,6 +654,12 @@ bool HexagonShuffler::shuffle() { } void HexagonShuffler::reportError(Twine const &Msg) { - if (ReportErrors) + if (ReportErrors) { + for (auto const &I : AppliedRestrictions) { + auto SM = Context.getSourceManager(); + if (SM) + SM->PrintMessage(I.first, SourceMgr::DK_Note, I.second); + } Context.reportError(Loc, Msg); + } } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h index df3fb0a1efb..37f90bc46ac 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h @@ -16,6 +16,7 @@ #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H #include "Hexagon.h" +#include "MCTargetDesc/HexagonMCInstrInfo.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" @@ -152,6 +153,10 @@ protected: MCSubtargetInfo const &STI; SMLoc Loc; bool ReportErrors; + std::vector<std::pair<SMLoc, std::string>> AppliedRestrictions; + void applySlotRestrictions(); + void restrictSlot1AOK(); + void restrictNoSlot1Store(); public: using iterator = HexagonPacket::iterator; @@ -168,6 +173,10 @@ public: unsigned size() const { return (Packet.size()); } + bool isMemReorderDisabled() const { + return (BundleFlags & HexagonMCInstrInfo::memReorderDisabledMask) != 0; + } + iterator begin() { return (Packet.begin()); } iterator end() { return (Packet.end()); } diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll new file mode 100644 index 00000000000..453f690f89f --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather-double.ll @@ -0,0 +1,60 @@ +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s + +; CHECK-LABEL: V6_vgathermw_128B +; CHECK: vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new +; CHECK-LABEL: V6_vgathermh_128B +; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new +; CHECK-LABEL: V6_vgathermhw_128B +; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new +; CHECK-LABEL: V6_vgathermwq_128B +; CHECK: if (q{{[0-3]+}}) vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new +; CHECK-LABEL: V6_vgathermhq_128B +; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new +; CHECK-LABEL: V6_vgathermhwq_128B +; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new + +declare void @llvm.hexagon.V6.vgathermw.128B(i8*, i32, i32, <32 x i32>) +define void @V6_vgathermw_128B(i8* %a, i32 %b, i32 %c, <32 x i32> %d) { + call void @llvm.hexagon.V6.vgathermw.128B(i8* %a, i32 %b, i32 %c, <32 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vgathermh.128B(i8*, i32, i32, <32 x i32>) +define void @V6_vgathermh_128B(i8* %a, i32 %b, i32 %c, <32 x i32> %d) { + call void @llvm.hexagon.V6.vgathermh.128B(i8* %a, i32 %b, i32 %c, <32 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vgathermhw.128B(i8*, i32, i32, <64 x i32>) +define void @V6_vgathermhw_128B(i8* %a, i32 %b, i32 %c, <64 x i32> %d) { + call void @llvm.hexagon.V6.vgathermhw.128B(i8* %a, i32 %b, i32 %c, <64 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vgathermwq.128B(i8*, <1024 x i1>, i32, i32, <32 x i32>) +define void @V6_vgathermwq_128B(i8* %a, <32 x i32> %b, i32 %c, i32 %d, <32 x i32> %e) { + %1 = bitcast <32 x i32> %b to <1024 x i1> + call void @llvm.hexagon.V6.vgathermwq.128B(i8* %a, <1024 x i1> %1, i32 %c, i32 %d, <32 x i32> %e) + ret void +} + +declare void @llvm.hexagon.V6.vgathermhq.128B(i8*, <1024 x i1>, i32, i32, <32 x i32>) +define void @V6_vgathermhq_128B(i8* %a, <32 x i32> %b, i32 %c, i32 %d, <32 x i32> %e) { + %1 = bitcast <32 x i32> %b to <1024 x i1> + call void @llvm.hexagon.V6.vgathermhq.128B(i8* %a, <1024 x i1> %1, i32 %c, i32 %d, <32 x i32> %e) + ret void +} + +declare void @llvm.hexagon.V6.vgathermhwq.128B(i8*, <1024 x i1>, i32, i32, <64 x i32>) +define void @V6_vgathermhwq_128B(i8* %a, <32 x i32> %b, i32 %c, i32 %d, <64 x i32> %e) { + %1 = bitcast <32 x i32> %b to <1024 x i1> + call void @llvm.hexagon.V6.vgathermhwq.128B(i8* %a, <1024 x i1> %1, i32 %c, i32 %d, <64 x i32> %e) + ret void +} + diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll new file mode 100644 index 00000000000..bc8591527c0 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-gather.ll @@ -0,0 +1,59 @@ +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s + +; CHECK-LABEL: V6_vgathermw +; CHECK: vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new +; CHECK-LABEL: V6_vgathermh +; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new +; CHECK-LABEL: V6_vgathermhw +; CHECK: vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new +; CHECK-LABEL: V6_vgathermwq +; CHECK: if (q{{[0-3]+}}) vtmp.w = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.w).w +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new +; CHECK-LABEL: V6_vgathermhq +; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}.h).h +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new +; CHECK-LABEL: V6_vgathermhwq +; CHECK: if (q{{[0-3]+}}) vtmp.h = vgather(r1,m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h +; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new + +declare void @llvm.hexagon.V6.vgathermw(i8*, i32, i32, <16 x i32>) +define void @V6_vgathermw(i8* %a, i32 %b, i32 %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vgathermw(i8* %a, i32 %b, i32 %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vgathermh(i8*, i32, i32, <16 x i32>) +define void @V6_vgathermh(i8* %a, i32 %b, i32 %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vgathermh(i8* %a, i32 %b, i32 %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vgathermhw(i8*, i32, i32, <32 x i32>) +define void @V6_vgathermhw(i8* %a, i32 %b, i32 %c, <32 x i32> %d) { + call void @llvm.hexagon.V6.vgathermhw(i8* %a, i32 %b, i32 %c, <32 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vgathermwq(i8*, <512 x i1>, i32, i32, <16 x i32>) +define void @V6_vgathermwq(i8* %a, <16 x i32> %b, i32 %c, i32 %d, <16 x i32> %e) { + %1 = bitcast <16 x i32> %b to <512 x i1> + call void @llvm.hexagon.V6.vgathermwq(i8* %a, <512 x i1> %1, i32 %c, i32 %d, <16 x i32> %e) + ret void +} + +declare void @llvm.hexagon.V6.vgathermhq(i8*, <512 x i1>, i32, i32, <16 x i32>) +define void @V6_vgathermhq(i8* %a, <16 x i32> %b, i32 %c, i32 %d, <16 x i32> %e) { + %1 = bitcast <16 x i32> %b to <512 x i1> + call void @llvm.hexagon.V6.vgathermhq(i8* %a, <512 x i1> %1, i32 %c, i32 %d, <16 x i32> %e) + ret void +} + +declare void @llvm.hexagon.V6.vgathermhwq(i8*, <512 x i1>, i32, i32, <32 x i32>) +define void @V6_vgathermhwq(i8* %a, <16 x i32> %b, i32 %c, i32 %d, <32 x i32> %e) { + %1 = bitcast <16 x i32> %b to <512 x i1> + call void @llvm.hexagon.V6.vgathermhwq(i8* %a, <512 x i1> %1, i32 %c, i32 %d, <32 x i32> %e) + ret void +} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll new file mode 100644 index 00000000000..40366fa3af1 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-double.ll @@ -0,0 +1,78 @@ +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s + +; CHECK-LABEL: V6_vscattermw_128B +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermh_128B +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermw_add_128B +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w += v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermh_add_128B +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h += v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermwq_128B +; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhq_128B +; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhw_128B +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhw_add_128B +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h += v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhwq_128B +; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h = v{{[0-9]+}} + + +declare void @llvm.hexagon.V6.vscattermw.128B(i32, i32, <32 x i32>, <32 x i32>) +define void @V6_vscattermw_128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) { + call void @llvm.hexagon.V6.vscattermw.128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermh.128B(i32, i32, <32 x i32>, <32 x i32>) +define void @V6_vscattermh_128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) { + call void @llvm.hexagon.V6.vscattermh.128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermw.add.128B(i32, i32, <32 x i32>, <32 x i32>) +define void @V6_vscattermw_add_128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) { + call void @llvm.hexagon.V6.vscattermw.add.128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermh.add.128B(i32, i32, <32 x i32>, <32 x i32>) +define void @V6_vscattermh_add_128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) { + call void @llvm.hexagon.V6.vscattermh.add.128B(i32 %a, i32 %b, <32 x i32> %c, <32 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermwq.128B(<1024 x i1>, i32, i32, <32 x i32>, <32 x i32>) +define void @V6_vscattermwq_128B(<32 x i32> %a, i32 %b, i32 %c, <32 x i32> %d, <32 x i32> %e) { + %1 = bitcast <32 x i32> %a to <1024 x i1> + call void @llvm.hexagon.V6.vscattermwq.128B(<1024 x i1> %1, i32 %b, i32 %c, <32 x i32> %d, <32 x i32> %e) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhq.128B(<1024 x i1>, i32, i32, <32 x i32>, <32 x i32>) +define void @V6_vscattermhq_128B(<32 x i32> %a, i32 %b, i32 %c, <32 x i32> %d, <32 x i32> %e) { + %1 = bitcast <32 x i32> %a to <1024 x i1> + call void @llvm.hexagon.V6.vscattermhq.128B(<1024 x i1> %1, i32 %b, i32 %c, <32 x i32> %d, <32 x i32> %e) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhw.128B(i32, i32, <64 x i32>, <32 x i32>) +define void @V6_vscattermhw_128B(i32 %a, i32 %b, <64 x i32> %c, <32 x i32> %d) { + call void @llvm.hexagon.V6.vscattermhw.128B(i32 %a, i32 %b, <64 x i32> %c, <32 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhw.add.128B(i32, i32, <64 x i32>, <32 x i32>) +define void @V6_vscattermhw_add_128B(i32 %a, i32 %b, <64 x i32> %c, <32 x i32> %d) { + call void @llvm.hexagon.V6.vscattermhw.add.128B(i32 %a, i32 %b, <64 x i32> %c, <32 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhwq.128B(<1024 x i1>, i32, i32, <64 x i32>, <32 x i32>) +define void @V6_vscattermhwq_128B(<32 x i32> %a, i32 %b, i32 %c, <64 x i32> %d, <32 x i32> %e) { + %1 = bitcast <32 x i32> %a to <1024 x i1> + call void @llvm.hexagon.V6.vscattermhwq.128B(<1024 x i1> %1, i32 %b, i32 %c, <64 x i32> %d, <32 x i32> %e) + ret void +} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll new file mode 100644 index 00000000000..2ebd22bdfb4 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter-gather.ll @@ -0,0 +1,32 @@ +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 -disable-packetizer < %s | FileCheck %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O0 < %s | FileCheck %s + +; CHECK: vtmp.h = vgather(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h +; CHECK-NEXT: vmem(r{{[0-9]+}}+#0) = vtmp.new +; CHECK-NEXT: } + +declare i32 @add_translation_extended(i32, i8*, i64, i32, i32, i32, i32, i32, i32) local_unnamed_addr + +; Function Attrs: nounwind +define i32 @main() local_unnamed_addr { +entry: + %hvx_vector = alloca <16 x i32>, align 64 + %0 = bitcast <16 x i32>* %hvx_vector to i8* + %call.i = tail call i32 @add_translation_extended(i32 1, i8* inttoptr (i32 -668991488 to i8*), i64 3625975808, i32 16, i32 15, i32 0, i32 0, i32 0, i32 3) + %1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) + %2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2) + tail call void @llvm.hexagon.V6.vscattermh.add(i32 -668991488, i32 1023, <16 x i32> %1, <16 x i32> %2) + call void @llvm.hexagon.V6.vgathermh(i8* %0, i32 -668991488, i32 1023, <16 x i32> %1) + ret i32 0 +} + +; Function Attrs: nounwind writeonly +declare void @llvm.hexagon.V6.vscattermh.add(i32, i32, <16 x i32>, <16 x i32>) + +; Function Attrs: nounwind readnone +declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) + +; Function Attrs: argmemonly nounwind +declare void @llvm.hexagon.V6.vgathermh(i8*, i32, i32, <16 x i32>) + diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll new file mode 100644 index 00000000000..405211c5dfa --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65-scatter.ll @@ -0,0 +1,78 @@ +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s + +; CHECK-LABEL: V6_vscattermw +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermh +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermw_add +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w += v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermh_add +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h += v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermwq +; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.w).w = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhq +; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}.h).h = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhw +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h = v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhw_add +; CHECK: vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h += v{{[0-9]+}} +; CHECK-LABEL: V6_vscattermhwq +; CHECK: if (q{{[0-3]}}) vscatter(r{{[0-9]+}},m{{[0-9]+}},v{{[0-9]+}}:{{[0-9]+}}.w).h = v{{[0-9]+}} + + +declare void @llvm.hexagon.V6.vscattermw(i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermw(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermw(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermh(i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermh(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermh(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermw.add(i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermw_add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermw.add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermh.add(i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermh_add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermh.add(i32 %a, i32 %b, <16 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermwq(<512 x i1>, i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermwq(<16 x i32> %a, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e) { + %1 = bitcast <16 x i32> %a to <512 x i1> + call void @llvm.hexagon.V6.vscattermwq(<512 x i1> %1, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhq(<512 x i1>, i32, i32, <16 x i32>, <16 x i32>) +define void @V6_vscattermhq(<16 x i32> %a, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e) { + %1 = bitcast <16 x i32> %a to <512 x i1> + call void @llvm.hexagon.V6.vscattermhq(<512 x i1> %1, i32 %b, i32 %c, <16 x i32> %d, <16 x i32> %e) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhw(i32, i32, <32 x i32>, <16 x i32>) +define void @V6_vscattermhw(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermhw(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhw.add(i32, i32, <32 x i32>, <16 x i32>) +define void @V6_vscattermhw_add(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d) { + call void @llvm.hexagon.V6.vscattermhw.add(i32 %a, i32 %b, <32 x i32> %c, <16 x i32> %d) + ret void +} + +declare void @llvm.hexagon.V6.vscattermhwq(<512 x i1>, i32, i32, <32 x i32>, <16 x i32>) +define void @V6_vscattermhwq(<16 x i32> %a, i32 %b, i32 %c, <32 x i32> %d, <16 x i32> %e) { + %1 = bitcast <16 x i32> %a to <512 x i1> + call void @llvm.hexagon.V6.vscattermhwq(<512 x i1> %1, i32 %b, i32 %c, <32 x i32> %d, <16 x i32> %e) + ret void +} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/v65.ll b/llvm/test/CodeGen/Hexagon/intrinsics/v65.ll new file mode 100644 index 00000000000..8d503f11800 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/intrinsics/v65.ll @@ -0,0 +1,156 @@ +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -mv65 -mattr=+hvxv65,hvx-length64b -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s + +; CHECK-CALL-NOT: call + +declare i32 @llvm.hexagon.A6.vcmpbeq.notany(i64, i64) +define i32 @A6_vcmpbeq_notany(i64 %a, i64 %b) { + %c = call i32 @llvm.hexagon.A6.vcmpbeq.notany(i64 %a, i64 %b) + ret i32 %c +} +; CHECK = !any8(vcmpb.eq(r1:0,r3:2)) + +declare <16 x i32> @llvm.hexagon.V6.vabsb(<16 x i32>) +define <16 x i32> @V6_vabsb(<16 x i32> %a) { + %b = call <16 x i32> @llvm.hexagon.V6.vabsb(<16 x i32> %a) + ret <16 x i32> %b +} +; CHECK: = vabs(v0.b) + +declare <16 x i32> @llvm.hexagon.V6.vabsb.sat(<16 x i32>) +define <16 x i32> @V6_vabsb_sat(<16 x i32> %a) { + %b = call <16 x i32> @llvm.hexagon.V6.vabsb.sat(<16 x i32> %a) + ret <16 x i32> %b +} +; CHECK: = vabs(v0.b):sat + +declare <16 x i32> @llvm.hexagon.V6.vaslh.acc(<16 x i32>, <16 x i32>, i32) +define <16 x i32> @V6_vaslh_acc(<16 x i32> %a, <16 x i32> %b, i32 %c) { + %d = call <16 x i32> @llvm.hexagon.V6.vaslh.acc(<16 x i32> %a, <16 x i32> %b, i32 %c) + ret <16 x i32> %d +} +; CHECK: += vasl(v1.h,r0) + +declare <16 x i32> @llvm.hexagon.V6.vasrh.acc(<16 x i32>, <16 x i32>, i32) +define <16 x i32> @V6_vasrh_acc(<16 x i32> %a, <16 x i32> %b, i32 %c) { + %d = call <16 x i32> @llvm.hexagon.V6.vasrh.acc(<16 x i32> %a, <16 x i32> %b, i32 %c) + ret <16 x i32> %d +} +; CHECK: += vasr(v1.h,r0) + +declare <16 x i32> @llvm.hexagon.V6.vasruwuhsat(<16 x i32>, <16 x i32>, i32) +define <16 x i32> @V6_vasruwuhsat(<16 x i32> %a, <16 x i32> %b, i32 %c) { + %d = call <16 x i32> @llvm.hexagon.V6.vasruwuhsat(<16 x i32> %a, <16 x i32> %b, i32 %c) + ret <16 x i32> %d +} +; CHECK: = vasr(v0.uw,v1.uw,r0):sat + +declare <16 x i32> @llvm.hexagon.V6.vasruhubsat(<16 x i32>, <16 x i32>, i32) +define <16 x i32> @V6_vasruhubsat(<16 x i32> %a, <16 x i32> %b, i32 %c) { + %d = call <16 x i32> @llvm.hexagon.V6.vasruhubsat(<16 x i32> %a, <16 x i32> %b, i32 %c) + ret <16 x i32> %d +} +; CHECK: = vasr(v0.uh,v1.uh,r0):sat + +declare <16 x i32> @llvm.hexagon.V6.vasruhubrndsat(<16 x i32>, <16 x i32>, i32) +define <16 x i32> @V6_vasruhubrndsat(<16 x i32> %a, <16 x i32> %b, i32 %c) { + %d = call <16 x i32> @llvm.hexagon.V6.vasruhubrndsat(<16 x i32> %a, <16 x i32> %b, i32 %c) + ret <16 x i32> %d +} +; CHECK: = vasr(v0.uh,v1.uh,r0):rnd:sat + +declare <16 x i32> @llvm.hexagon.V6.vavguw(<16 x i32>, <16 x i32>) +define <16 x i32> @V6_vavguw(<16 x i32> %a, <16 x i32> %b) { + %c = call <16 x i32> @llvm.hexagon.V6.vavguw(<16 x i32> %a, <16 x i32> %b) + ret <16 x i32> %c +} +; CHECK: = vavg(v0.uw,v1.uw) + +declare <16 x i32> @llvm.hexagon.V6.vavguwrnd(<16 x i32>, <16 x i32>) +define <16 x i32> @V6_vavguwrnd(<16 x i32> %a, <16 x i32> %b) { + %c = call <16 x i32> @llvm.hexagon.V6.vavguwrnd(<16 x i32> %a, <16 x i32> %b) + ret <16 x i32> %c +} +; CHECK: = vavg(v0.uw,v1.uw):rnd + +declare <16 x i32> @llvm.hexagon.V6.vavgb(<16 x i32>, <16 x i32>) +define <16 x i32> @V6_vavgb(<16 x i32> %a, <16 x i32> %b) { + %c = call <16 x i32> @llvm.hexagon.V6.vavgb(<16 x i32> %a, <16 x i32> %b) + ret <16 x i32> %c +} +; CHECK: = vavg(v0.b,v1.b) + +declare <16 x i32> @llvm.hexagon.V6.vavgbrnd(<16 x i32>, <16 x i32>) +define <16 x i32> @V6_vavgbrnd(<16 x i32> %a, <16 x i32> %b) { + %c = call <16 x i32> @llvm.hexagon.V6.vavgbrnd(<16 x i32> %a, <16 x i32> %b) + ret <16 x i32> %c +} +; CHECK: = vavg(v0.b,v1.b):rnd + +declare <16 x i32> @llvm.hexagon.V6.vnavgb(<16 x i32>, <16 x i32>) +define <16 x i32> @V6_vnavgb(<16 x i32> %a, <16 x i32> %b) { + %c = call <16 x i32> @llvm.hexagon.V6.vnavgb(<16 x i32> %a, <16 x i32> %b) + ret <16 x i32> %c +} +; CHECK: = vnavg(v0.b,v1.b) + +declare <32 x i32> @llvm.hexagon.V6.vmpabuu(<32 x i32>, i32) +define <32 x i32> @V6_vmpabuu(<32 x i32> %a, i32 %b) { + %c = call <32 x i32> @llvm.hexagon.V6.vmpabuu(<32 x i32> %a, i32 %b) + ret <32 x i32> %c +} +; CHECK: = vmpa(v1:0.ub,r0.ub) + +declare <32 x i32> @llvm.hexagon.V6.vmpabuu.acc(<32 x i32>, <32 x i32>, i32) +define <32 x i32> @V6_vmpabuu_acc(<32 x i32> %a, <32 x i32> %b, i32 %c) { + %d = call <32 x i32> @llvm.hexagon.V6.vmpabuu.acc(<32 x i32> %a, <32 x i32> %b, i32 %c) + ret <32 x i32> %d +} +; CHECK: += vmpa(v3:2.ub,r0.ub) + +declare <16 x i32> @llvm.hexagon.V6.vmpauhuhsat(<16 x i32>, <16 x i32>, i64) +define <16 x i32> @V6_vmpauhuhsat(<16 x i32> %a, <16 x i32> %b, i64 %c) { + %d = call <16 x i32> @llvm.hexagon.V6.vmpauhuhsat(<16 x i32> %a, <16 x i32> %b, i64 %c) + ret <16 x i32> %d +} +; CHECK: = vmpa(v0.h,v1.uh,r1:0.uh):sat + +declare <16 x i32> @llvm.hexagon.V6.vmpsuhuhsat(<16 x i32>, <16 x i32>, i64) +define <16 x i32> @V6_vmpsuhuhsat(<16 x i32> %a, <16 x i32> %b, i64 %c) { + %d = call <16 x i32> @llvm.hexagon.V6.vmpsuhuhsat(<16 x i32> %a, <16 x i32> %b, i64 %c) + ret <16 x i32> %d +} +; CHECK: = vmps(v0.h,v1.uh,r1:0.uh):sat + +declare <32 x i32> @llvm.hexagon.V6.vmpyh.acc(<32 x i32>, <16 x i32>, i32) +define <32 x i32> @V6_vmpyh_acc(<32 x i32> %a, <16 x i32> %b, i32 %c) { + %d = call <32 x i32> @llvm.hexagon.V6.vmpyh.acc(<32 x i32> %a, <16 x i32> %b, i32 %c) + ret <32 x i32> %d +} +; CHECK: += vmpy(v2.h,r0.h) + +declare <16 x i32> @llvm.hexagon.V6.vmpyuhe(<16 x i32>, i32) +define <16 x i32> @V6_vmpyuhe(<16 x i32> %a, i32 %b) { + %c = call <16 x i32> @llvm.hexagon.V6.vmpyuhe(<16 x i32> %a, i32 %b) + ret <16 x i32> %c +} +; CHECK: = vmpye(v0.uh,r0.uh) + +;declare <16 x i32> @llvm.hexagon.V6.vprefixqb(<512 x i1>) +;define <16 x i32> @V6_vprefixqb(<512 x i1> %a) { +; %b = call <16 x i32> @llvm.hexagon.V6.vprefixqb(<512 x i1> %a) +; ret <16 x i32> %b +;} + +;declare <16 x i32> @llvm.hexagon.V6.vprefixqh(<512 x i1>) +;define <16 x i32> @V6_vprefixqh(<512 x i1> %a) { +; %b = call <16 x i32> @llvm.hexagon.V6.vprefixqh(<512 x i1> %a) +; ret <16 x i32> %b +;} + +;declare <16 x i32> @llvm.hexagon.V6.vprefixqw(<512 x i1>) +;define <16 x i32> @V6_vprefixqw(<512 x i1> %a) { +; %b = call <16 x i32> @llvm.hexagon.V6.vprefixqw(<512 x i1> %a) +; ret <16 x i32> %b +;} + diff --git a/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir b/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir index b2e1968bb59..82be6b21d5e 100644 --- a/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir +++ b/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir @@ -36,5 +36,5 @@ body: | bb.2: liveins: %r0 %d8 = L2_loadrd_io %r29, 8 - L4_return implicit-def %r29, implicit-def %r30, implicit-def %r31, implicit-def %pc, implicit %r30 + %d15 = L4_return %r29, implicit-def %r29, implicit-def %pc, implicit %r30, implicit %framekey diff --git a/llvm/test/MC/Hexagon/PacketRules/endloop_branches.s b/llvm/test/MC/Hexagon/PacketRules/endloop_branches.s index fbaa246c068..46d984189b5 100644 --- a/llvm/test/MC/Hexagon/PacketRules/endloop_branches.s +++ b/llvm/test/MC/Hexagon/PacketRules/endloop_branches.s @@ -1,12 +1,17 @@ # RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>&1 | FileCheck %s -# Check that a branch in an end-loop packet is caught. - { jump unknown }:endloop0 -# CHECK: 5:3: error: packet marked with `:endloop0' cannot contain instructions that modify register +# CHECK: 4:1: error: Branches cannot be in a packet with hardware loops { jump unknown }:endloop1 +# CHECK: 8:1: error: Branches cannot be in a packet with hardware loops + +{ call unknown +}:endloop0 +# CHECK: 12:1: error: Branches cannot be in a packet with hardware loops -# CHECK: 9:3: error: packet marked with `:endloop1' cannot contain instructions that modify register +{ dealloc_return +}:endloop0 +# CHECK: 16:1: error: Branches cannot be in a packet with hardware loops diff --git a/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s b/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s new file mode 100644 index 00000000000..8719281067d --- /dev/null +++ b/llvm/test/MC/Hexagon/hvx-double-implies-hvx.s @@ -0,0 +1,4 @@ +# RUN: llvm-mc -filetype=obj -arch=hexagon -mv65 -mattr=+hvxv65,+hvx-length128b %s | llvm-objdump -d -mhvx - | FileCheck %s + +# CHECK: vhist +vhist diff --git a/llvm/test/MC/Hexagon/new-value-check.s b/llvm/test/MC/Hexagon/new-value-check.s index 978d6f15148..4c0674d7e2f 100644 --- a/llvm/test/MC/Hexagon/new-value-check.s +++ b/llvm/test/MC/Hexagon/new-value-check.s @@ -3,36 +3,33 @@ # RUN: not llvm-mc -triple=hexagon -relax-nv-checks < %s 2>&1 | \ # RUN: FileCheck %s --check-prefix=CHECK-RELAXED -# CHECK-STRICT: :12:1: error: register `R0' used with `.new' but not validly modified in the same packet -# CHECK-RELAXED: :12:1: error: register `R0' used with `.new' but not validly modified in the same packet +# CHECK-STRICT: :10:3: note: Register producer has the opposite predicate sense as consumer +# CHECK-RELAXED: :10:3: note: Register producer has the opposite predicate sense as consumer { # invalid: r0 definition predicated on the opposite condition if (p3) r0 = add(r1, r2) if (!p3) memb(r20) = r0.new } -# CHECK-STRICT: :20:1: error: register `R0' used with `.new' but not validly modified in the same packet -# CHECK-RELAXED: :20:1: error: register `R0' used with `.new' but not validly modified in the same packet -{ - # invalid: new-value compare-and-jump cannot use floating point value +# CHECK-STRICT: :18:3: note: FPU instructions cannot be new-value producers for jumps +# CHECK-RELAXED: :18:3: note: FPU instructions cannot be new-value producers for jumps +# CHECK-RELAXED: :19:3: error: Instruction does not have a valid new register producer +{ # invalid: new-value compare-and-jump cannot use floating point value r0 = sfadd(r1, r2) if (cmp.eq(r0.new, #0)) jump:nt . } -# CHECK-STRICT: :29:1: error: register `R0' used with `.new' but not validly modified in the same packet -# CHECK-RELAXED: :29:1: error: register `R0' used with `.new' but not validly modified in the same packet +# No errors from this point on with the relaxed checks. +# CHECK-RELAXED-NOT: error + +# CHECK-STRICT: :28:3: note: Register producer is predicated and consumer is unconditional { - # invalid: definition of r0 should be unconditional (not explicitly docu- - # mented) + # valid in relaxed, p0 could always be true if (p0) r0 = r1 if (cmp.eq(r0.new, #0)) jump:nt . } - -# No errors from this point on with the relaxed checks. -# CHECK-RELAXED-NOT: error - -# CHECK-STRICT: :41:1: error: register `R0' used with `.new' but not validly modified in the same packet +# CHECK-STRICT: :36:3: note: Register producer does not use the same predicate register as the consumer { # valid (relaxed): p2 and p3 cannot be proven to violate the new-value # requirements @@ -40,7 +37,7 @@ if (p2) memb(r20) = r0.new } -# CHECK-STRICT: :48:1: error: register `R0' used with `.new' but not validly modified in the same packet +# CHECK-STRICT: :43:3: note: Register producer is predicated and consumer is unconditional { # valid (relaxed): p3 could be always true if (p3) r0 = add(r1, r2) diff --git a/llvm/test/MC/Hexagon/v60-misc.s b/llvm/test/MC/Hexagon/v60-misc.s index 53872d64dcf..a7ec36cfa95 100644 --- a/llvm/test/MC/Hexagon/v60-misc.s +++ b/llvm/test/MC/Hexagon/v60-misc.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mhvx -d - | FileCheck %s +# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mhvx -d - | FileCheck %s .L0: diff --git a/llvm/test/MC/Hexagon/v65_all.s b/llvm/test/MC/Hexagon/v65_all.s new file mode 100644 index 00000000000..4f52a063a34 --- /dev/null +++ b/llvm/test/MC/Hexagon/v65_all.s @@ -0,0 +1,184 @@ +# RUN: llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj %s | llvm-objdump -mv65 -mhvx -d - | FileCheck %s + +// Warning: This file is auto generated by mktest.py. Do not edit! +// Created on: 2016-06-01 @ 17:33:01 +// Created using: +// /usr2/mlambert/Tags/iset.py.v65_20160513 + + +// V6_vmpyuhe_acc +// Vx32.uw+=vmpye(Vu32.uh,Rt32.uh) + V0.uw+=vmpye(V0.uh,R0.uh) +# CHECK: 1980e060 { v0.uw += vmpye(v0.uh,r0.uh) } + +// V6_vgathermwq +// if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w + if (Q0) vtmp.w=vgather(R0,M0,V0.w).w +# CHECK: 2f00c400 { if (q0) vtmp.w = vgather(r0,m0,v0.w).w } + +// V6_vscattermw +// vscatter(Rt32,Mu2,Vv32.w).w=Vw32 + vscatter(R0,M0,V0.w).w=V0 +# CHECK: 2f20c000 { vscatter(r0,m0,v0.w).w = v0 } + +// V6_vscattermh +// vscatter(Rt32,Mu2,Vv32.h).h=Vw32 + vscatter(R0,M0,V0.h).h=V0 +# CHECK: 2f20c020 { vscatter(r0,m0,v0.h).h = v0 } + +// V6_vlut4 +// Vd32.h=vlut4(Vu32.uh,Rtt32.h) + V0.h=vlut4(V0.uh,R1:0.h) +# CHECK: 1960c080 { v0.h = vlut4(v0.uh,r1:0.h) } + +// V6_vgathermhwq +// if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h + if (Q0) vtmp.h=vgather(R0,M0,V1:0.w).h +# CHECK: 2f00c600 { if (q0) vtmp.h = vgather(r0,m0,v1:0.w).h } + +// V6_vS32b_srls_ai +// vmem(Rt32+#s4):scatter_release + vmem(R0+#0):scatter_release +# CHECK: 2820c028 { vmem(r0+#0):scatter_release } + +// V6_vgathermh +// vtmp.h=vgather(Rt32,Mu2,Vv32.h).h + vtmp.h=vgather(R0,M0,V0.h).h +# CHECK: 2f00c100 { vtmp.h = vgather(r0,m0,v0.h).h } + +// V6_vscattermhw +// vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 + vscatter(R0,M0,V1:0.w).h=V0 +# CHECK: 2f20c040 { vscatter(r0,m0,v1:0.w).h = v0 } + +// V6_vS32b_srls_ppu +// vmem(Rx32++Mu2):scatter_release + vmem(R0++M0):scatter_release +# CHECK: 2b20c028 { vmem(r0++m0):scatter_release } + +// V6_vscattermhw_add +// vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32 + vscatter(R0,M0,V1:0.w).h+=V0 +# CHECK: 2f20c0c0 { vscatter(r0,m0,v1:0.w).h += v0 } + +// V6_vmpabuu +// Vdd32.h=vmpa(Vuu32.ub,Rt32.ub) + V1:0.h=vmpa(V1:0.ub,R0.ub) +# CHECK: 1960c060 { v1:0.h = vmpa(v1:0.ub,r0.ub) } + +// V6_vasruhubrndsat +// Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat + V0.ub=vasr(V0.uh,V0.uh,R0):rnd:sat +# CHECK: 1800c0e0 { v0.ub = vasr(v0.uh,v0.uh,r0):rnd:sat } + +// V6_vscattermh_add +// vscatter(Rt32,Mu2,Vv32.h).h+=Vw32 + vscatter(R0,M0,V0.h).h+=V0 +# CHECK: 2f20c0a0 { vscatter(r0,m0,v0.h).h += v0 } + +// V6_vgathermw +// vtmp.w=vgather(Rt32,Mu2,Vv32.w).w + vtmp.w=vgather(R0,M0,V0.w).w +# CHECK: 2f00c000 { vtmp.w = vgather(r0,m0,v0.w).w } + +// V6_vasruhubsat +// Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat + V0.ub=vasr(V0.uh,V0.uh,R0):sat +# CHECK: 1800e0a0 { v0.ub = vasr(v0.uh,v0.uh,r0):sat } + +// V6_vscattermhwq +// if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 + if (Q0) vscatter(R0,M0,V1:0.w).h=V0 +# CHECK: 2fa0c000 { if (q0) vscatter(r0,m0,v1:0.w).h = v0 } + +// V6_vgathermhq +// if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h + if (Q0) vtmp.h=vgather(R0,M0,V0.h).h +# CHECK: 2f00c500 { if (q0) vtmp.h = vgather(r0,m0,v0.h).h } + +// V6_vmpsuhuhsat +// Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat + V0.h=vmps(V0.h,V0.uh,R1:0.uh):sat +# CHECK: 1980e0c0 { v0.h = vmps(v0.h,v0.uh,r1:0.uh):sat } + +// V6_vS32b_srls_pi +// vmem(Rx32++#s3):scatter_release + vmem(R0++#0):scatter_release +# CHECK: 2920c028 { vmem(r0++#0):scatter_release } + +// V6_vgathermhw +// vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h + vtmp.h=vgather(R0,M0,V1:0.w).h +# CHECK: 2f00c200 { vtmp.h = vgather(r0,m0,v1:0.w).h } + +// V6_vmpyuhe +// Vd32.uw=vmpye(Vu32.uh,Rt32.uh) + V0.uw=vmpye(V0.uh,R0.uh) +# CHECK: 1960c040 { v0.uw = vmpye(v0.uh,r0.uh) } + +// V6_vscattermwq +// if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32 + if (Q0) vscatter(R0,M0,V0.w).w=V0 +# CHECK: 2f80c000 { if (q0) vscatter(r0,m0,v0.w).w = v0 } + +// V6_vasruwuhsat +// Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat + V0.uh=vasr(V0.uw,V0.uw,R0):sat +# CHECK: 1800e080 { v0.uh = vasr(v0.uw,v0.uw,r0):sat } + +// V6_vprefixqh +// Vd32.h=prefixsum(Qv4) + V0.h=prefixsum(Q0) +# CHECK: 1e03e140 { v0.h = prefixsum(q0) } + +// V6_vmpabuu_acc +// Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub) + V1:0.h+=vmpa(V1:0.ub,R0.ub) +# CHECK: 19a0e080 { v1:0.h += vmpa(v1:0.ub,r0.ub) } + +// V6_vprefixqw +// Vd32.w=prefixsum(Qv4) + V0.w=prefixsum(Q0) +# CHECK: 1e03e240 { v0.w = prefixsum(q0) } + +// V6_vprefixqb +// Vd32.b=prefixsum(Qv4) + V0.b=prefixsum(Q0) +# CHECK: 1e03e040 { v0.b = prefixsum(q0) } + +// V6_vabsb +// Vd32.b=vabs(Vu32.b) + V0.b=vabs(V0.b) +# CHECK: 1e01c080 { v0.b = vabs(v0.b) } + +// V6_vscattermw_add +// vscatter(Rt32,Mu2,Vv32.w).w+=Vw32 + vscatter(R0,M0,V0.w).w+=V0 +# CHECK: 2f20c080 { vscatter(r0,m0,v0.w).w += v0 } + +// V6_vscattermhq +// if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32 + if (Q0) vscatter(R0,M0,V0.h).h=V0 +# CHECK: 2f80c080 { if (q0) vscatter(r0,m0,v0.h).h = v0 } + +// V6_vmpauhuhsat +// Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat + V0.h=vmpa(V0.h,V0.uh,R1:0.uh):sat +# CHECK: 1980e0a0 { v0.h = vmpa(v0.h,v0.uh,r1:0.uh):sat } + +// V6_vabsb_sat +// Vd32.b=vabs(Vu32.b):sat + V0.b=vabs(V0.b):sat +# CHECK: 1e01c0a0 { v0.b = vabs(v0.b):sat } + +v1:0.w+=vrmpy(v0.b, r1:0.ub) +# CHECK: 19a0e000 { v1:0.w += vrmpy(v0.b,r1:0.ub) } + +V1:0.uw+=vrmpy(v0.ub,r1:0.ub) +# CHECK: 19a0e0e0 { v1:0.uw += vrmpy(v0.ub,r1:0.ub) } + +v1:0.uw=vrmpy(v1.ub,r1:0.ub) +# CHECK: 19c0c180 { v1:0.uw = vrmpy(v1.ub,r1:0.ub) } + +v1:0.w=vrmpy(v1.b,r1:0.ub) +# CHECK: 19c0c1a0 { v1:0.w = vrmpy(v1.b,r1:0.ub) } diff --git a/llvm/test/MC/Hexagon/vpred_defs.s b/llvm/test/MC/Hexagon/vpred_defs.s new file mode 100644 index 00000000000..92c15a3e575 --- /dev/null +++ b/llvm/test/MC/Hexagon/vpred_defs.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -arch=hexagon -mv65 -filetype=asm -mhvx %s | FileCheck %s + +# CHECK-NOT: error: register `{{.+}}' modified more than once + +{ Q0 = VCMP.EQ(V0.h,V4.h) + Q1 = VCMP.EQ(V1.h,V6.h) + IF (Q3) VTMP.h = VGATHER(R0,M0,V3.h).h + VMEM(R4++#1) = VTMP.new +} diff --git a/llvm/test/MC/Hexagon/vscatter-slot.s b/llvm/test/MC/Hexagon/vscatter-slot.s new file mode 100644 index 00000000000..6c806de2f98 --- /dev/null +++ b/llvm/test/MC/Hexagon/vscatter-slot.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -arch=hexagon -mv65 -mhvx -filetype=asm < %s | FileCheck %s + +# Test that a slot error is not reported for a packet with a load and a +# vscatter. + +# CHECK: vscatter(r0,m0,v0.h).h = v1 +{ + v1=vmem(r1+#0) + vscatter(r0,m0,v0.h).h=v1 +} +# CHECK: vscatter(r2,m0,v1:0.w).h += v2 +{ + v1=vmem(r3+#0) + vscatter(r2,m0,v1:0.w).h+=v2 +} +# CHECK: vmem(r4+#0):scatter_release +{ + v1=vmem(r5+#0) + vmem(r4+#0):scatter_release +} +# CHECK: vmem(r4+#0):scatter_release +{ + v1=vmem(r5+#0) + vmem(r4+#0):scatter_release +} diff --git a/llvm/test/MC/Hexagon/vtmp_def.s b/llvm/test/MC/Hexagon/vtmp_def.s new file mode 100644 index 00000000000..26d257efadd --- /dev/null +++ b/llvm/test/MC/Hexagon/vtmp_def.s @@ -0,0 +1,5 @@ +# RUN: not llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj %s 2>&1 | FileCheck %s + +# CHECK: register `VTMP' modified more than once +{ vtmp.h=vgather(r0, m0, v1:0.w).h + vtmp.h=vgather(r0, m0, v1:0.w).h } |
