diff options
10 files changed, 338 insertions, 5 deletions
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/ARM/AsmParser/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/AsmParser/BUILD.gn new file mode 100644 index 00000000000..9b6dd6401dd --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/AsmParser/BUILD.gn @@ -0,0 +1,24 @@ +import("//llvm/utils/TableGen/tablegen.gni") + +tablegen("ARMGenAsmMatcher") { + visibility = [ ":AsmParser" ] + args = [ "-gen-asm-matcher" ] + td_file = "../ARM.td" +} + +static_library("AsmParser") { + output_name = "LLVMARMAsmParser" + deps = [ + ":ARMGenAsmMatcher", + "//llvm/lib/MC", + "//llvm/lib/MC/MCParser", + "//llvm/lib/Support", + "//llvm/lib/Target/ARM/MCTargetDesc", + "//llvm/lib/Target/ARM/TargetInfo", + "//llvm/lib/Target/ARM/Utils", + ] + include_dirs = [ ".." ] + sources = [ + "ARMAsmParser.cpp", + ] +} diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn new file mode 100644 index 00000000000..416d4da9935 --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/BUILD.gn @@ -0,0 +1,121 @@ +import("//llvm/utils/TableGen/tablegen.gni") + +tablegen("ARMGenCallingConv") { + visibility = [ ":LLVMARMCodeGen" ] + args = [ "-gen-callingconv" ] + td_file = "ARM.td" +} + +tablegen("ARMGenDAGISel") { + visibility = [ ":LLVMARMCodeGen" ] + args = [ "-gen-dag-isel" ] + td_file = "ARM.td" +} + +tablegen("ARMGenFastISel") { + visibility = [ ":LLVMARMCodeGen" ] + args = [ "-gen-fast-isel" ] + td_file = "ARM.td" +} + +tablegen("ARMGenGlobalISel") { + visibility = [ ":LLVMARMCodeGen" ] + args = [ "-gen-global-isel" ] + td_file = "ARM.td" +} + +tablegen("ARMGenMCPseudoLowering") { + visibility = [ ":LLVMARMCodeGen" ] + args = [ "-gen-pseudo-lowering" ] + td_file = "ARM.td" +} + +tablegen("ARMGenRegisterBank") { + visibility = [ ":LLVMARMCodeGen" ] + args = [ "-gen-register-bank" ] + td_file = "ARM.td" +} + +static_library("LLVMARMCodeGen") { + deps = [ + ":ARMGenCallingConv", + ":ARMGenDAGISel", + ":ARMGenFastISel", + ":ARMGenGlobalISel", + ":ARMGenMCPseudoLowering", + ":ARMGenRegisterBank", + "InstPrinter", + "MCTargetDesc", + "TargetInfo", + "Utils", + "//llvm/include/llvm/Config:llvm-config", + "//llvm/lib/Analysis", + "//llvm/lib/CodeGen", + "//llvm/lib/CodeGen/AsmPrinter", + "//llvm/lib/CodeGen/GlobalISel", + "//llvm/lib/CodeGen/SelectionDAG", + "//llvm/lib/IR", + "//llvm/lib/MC", + "//llvm/lib/Support", + "//llvm/lib/Target", + ] + include_dirs = [ "." ] + sources = [ + "A15SDOptimizer.cpp", + "ARMAsmPrinter.cpp", + "ARMBaseInstrInfo.cpp", + "ARMBaseRegisterInfo.cpp", + "ARMCallLowering.cpp", + "ARMCodeGenPrepare.cpp", + "ARMComputeBlockSize.cpp", + "ARMConstantIslandPass.cpp", + "ARMConstantPoolValue.cpp", + "ARMExpandPseudoInsts.cpp", + "ARMFastISel.cpp", + "ARMFrameLowering.cpp", + "ARMHazardRecognizer.cpp", + "ARMISelDAGToDAG.cpp", + "ARMISelLowering.cpp", + "ARMInstrInfo.cpp", + "ARMInstructionSelector.cpp", + "ARMLegalizerInfo.cpp", + "ARMLoadStoreOptimizer.cpp", + "ARMMCInstLower.cpp", + "ARMMachineFunctionInfo.cpp", + "ARMMacroFusion.cpp", + "ARMOptimizeBarriersPass.cpp", + "ARMParallelDSP.cpp", + "ARMRegisterBankInfo.cpp", + "ARMRegisterInfo.cpp", + "ARMSelectionDAGInfo.cpp", + "ARMSubtarget.cpp", + "ARMTargetMachine.cpp", + "ARMTargetObjectFile.cpp", + "ARMTargetTransformInfo.cpp", + "MLxExpansionPass.cpp", + "Thumb1FrameLowering.cpp", + "Thumb1InstrInfo.cpp", + "Thumb2ITBlockPass.cpp", + "Thumb2InstrInfo.cpp", + "Thumb2SizeReduction.cpp", + "ThumbRegisterInfo.cpp", + ] +} + +# This is a bit different from most build files: Due to this group +# having the directory's name, "//llvm/lib/Target/AArch64" will refer to this +# target, which pulls in the code in this directory *and all subdirectories*. +# For most other directories, "//llvm/lib/Foo" only pulls in the code directly +# in "llvm/lib/Foo". The forwarding targets in //llvm/lib/Target expect this +# different behavior. +group("ARM") { + deps = [ + ":LLVMARMCodeGen", + "AsmParser", + "Disassembler", + "InstPrinter", + "MCTargetDesc", + "TargetInfo", + "Utils", + ] +} diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/ARM/Disassembler/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/Disassembler/BUILD.gn new file mode 100644 index 00000000000..bfe5e50c594 --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/Disassembler/BUILD.gn @@ -0,0 +1,23 @@ +import("//llvm/utils/TableGen/tablegen.gni") + +tablegen("ARMGenDisassemblerTables") { + visibility = [ ":Disassembler" ] + args = [ "-gen-disassembler" ] + td_file = "../ARM.td" +} + +static_library("Disassembler") { + output_name = "LLVMARMDisassembler" + deps = [ + ":ARMGenDisassemblerTables", + "//llvm/lib/MC", + "//llvm/lib/MC/MCDisassembler", + "//llvm/lib/Support", + "//llvm/lib/Target/ARM/MCTargetDesc", + "//llvm/lib/Target/ARM/Utils", + ] + include_dirs = [ ".." ] + sources = [ + "ARMDisassembler.cpp", + ] +} diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/ARM/InstPrinter/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/InstPrinter/BUILD.gn new file mode 100644 index 00000000000..6cac44291fd --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/InstPrinter/BUILD.gn @@ -0,0 +1,25 @@ +import("//llvm/utils/TableGen/tablegen.gni") + +tablegen("ARMGenAsmWriter") { + visibility = [ ":InstPrinter" ] + args = [ "-gen-asm-writer" ] + td_file = "../ARM.td" +} + +static_library("InstPrinter") { + output_name = "LLVMARMAsmPrinter" + deps = [ + ":ARMGenAsmWriter", + "//llvm/lib/MC", + "//llvm/lib/Support", + + # MCTargetDesc depends on InstPrinter, so we can't depend on the full + # MCTargetDesc target here: it would form a cycle. + "//llvm/lib/Target/ARM/MCTargetDesc:tablegen", + "//llvm/lib/Target/ARM/Utils", + ] + include_dirs = [ ".." ] + sources = [ + "ARMInstPrinter.cpp", + ] +} diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/ARM/MCTargetDesc/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/MCTargetDesc/BUILD.gn new file mode 100644 index 00000000000..3ef2f435df5 --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/MCTargetDesc/BUILD.gn @@ -0,0 +1,70 @@ +import("//llvm/utils/TableGen/tablegen.gni") + +tablegen("ARMGenInstrInfo") { + visibility = [ ":tablegen" ] + args = [ "-gen-instr-info" ] + td_file = "../ARM.td" +} + +tablegen("ARMGenMCCodeEmitter") { + visibility = [ ":tablegen" ] + args = [ "-gen-emitter" ] + td_file = "../ARM.td" +} + +tablegen("ARMGenRegisterInfo") { + visibility = [ ":tablegen" ] + args = [ "-gen-register-info" ] + td_file = "../ARM.td" +} + +tablegen("ARMGenSubtargetInfo") { + visibility = [ ":tablegen" ] + args = [ "-gen-subtarget" ] + td_file = "../ARM.td" +} + +group("tablegen") { + visibility = [ + ":MCTargetDesc", + "../InstPrinter", + "../TargetInfo", + "../Utils", + ] + public_deps = [ + ":ARMGenInstrInfo", + ":ARMGenMCCodeEmitter", + ":ARMGenRegisterInfo", + ":ARMGenSubtargetInfo", + ] +} +static_library("MCTargetDesc") { + output_name = "LLVMARMDesc" + public_deps = [ + ":tablegen", + ] + deps = [ + "//llvm/lib/MC", + "//llvm/lib/MC/MCDisassembler", + "//llvm/lib/Support", + "//llvm/lib/Target/ARM/InstPrinter", + "//llvm/lib/Target/ARM/TargetInfo", + "//llvm/lib/Target/ARM/Utils", + ] + include_dirs = [ ".." ] + sources = [ + "ARMAsmBackend.cpp", + "ARMELFObjectWriter.cpp", + "ARMELFStreamer.cpp", + "ARMMCAsmInfo.cpp", + "ARMMCCodeEmitter.cpp", + "ARMMCExpr.cpp", + "ARMMCTargetDesc.cpp", + "ARMMachORelocationInfo.cpp", + "ARMMachObjectWriter.cpp", + "ARMTargetStreamer.cpp", + "ARMUnwindOpAsm.cpp", + "ARMWinCOFFObjectWriter.cpp", + "ARMWinCOFFStreamer.cpp", + ] +} diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/ARM/TargetInfo/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/TargetInfo/BUILD.gn new file mode 100644 index 00000000000..521367c4f42 --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/TargetInfo/BUILD.gn @@ -0,0 +1,14 @@ +static_library("TargetInfo") { + output_name = "LLVMARMInfo" + deps = [ + "//llvm/lib/Support", + + # MCTargetDesc depends on TargetInfo, so we can't depend on the full + # MCTargetDesc target here: it would form a cycle. + "//llvm/lib/Target/ARM/MCTargetDesc:tablegen", + ] + include_dirs = [ ".." ] + sources = [ + "ARMTargetInfo.cpp", + ] +} diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/ARM/Utils/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/Utils/BUILD.gn new file mode 100644 index 00000000000..e0ddc22f90b --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/lib/Target/ARM/Utils/BUILD.gn @@ -0,0 +1,25 @@ +import("//llvm/utils/TableGen/tablegen.gni") + +tablegen("ARMGenSystemRegister") { + visibility = [ ":Utils" ] + args = [ "-gen-searchable-tables" ] + td_file = "../ARM.td" +} + +static_library("Utils") { + output_name = "LLVMARMUtils" + public_deps = [ + ":ARMGenSystemRegister", + ] + deps = [ + "//llvm/lib/Support", + "//llvm/lib/Target/ARM/MCTargetDesc:tablegen", + ] + + # ARMBaseInfo.h includes a header from MCTargetDesc, + # https://reviews.llvm.org/D35209#1075113 :-/ + include_dirs = [ ".." ] + sources = [ + "ARMBaseInfo.cpp", + ] +} diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/targets.gni b/llvm/utils/gn/secondary/llvm/lib/Target/targets.gni index 95befc0684b..01252d0c4d0 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/targets.gni +++ b/llvm/utils/gn/secondary/llvm/lib/Target/targets.gni @@ -8,6 +8,8 @@ declare_args() { if (llvm_targets_to_build == "host") { if (host_cpu == "arm64") { llvm_targets_to_build = [ "AArch64" ] + } else if (host_cpu == "arm") { + llvm_targets_to_build = [ "ARM" ] } else if (host_cpu == "x86" || host_cpu == "x64") { llvm_targets_to_build = [ "X86" ] } else { @@ -17,6 +19,7 @@ if (llvm_targets_to_build == "host") { # FIXME: Port the remaining targets. llvm_targets_to_build = [ "AArch64", + "ARM", "X86", ] } @@ -24,10 +27,13 @@ if (llvm_targets_to_build == "host") { # Validate that llvm_targets_to_build is set to a list of valid targets, # and remember which targets are built. llvm_build_AArch64 = false +llvm_build_ARM = false llvm_build_X86 = false foreach(target, llvm_targets_to_build) { if (target == "AArch64") { llvm_build_AArch64 = true + } else if (target == "ARM") { + llvm_build_ARM = true } else if (target == "X86") { llvm_build_X86 = true } else { @@ -39,6 +45,8 @@ foreach(target, llvm_targets_to_build) { # FIXME: This should be based off target_cpu once cross compiles work. if (host_cpu == "arm64") { native_target = "AArch64" +} else if (host_cpu == "arm") { + native_target = "ARM" } else if (host_cpu == "x86" || host_cpu == "x64") { native_target = "X86" } else { diff --git a/llvm/utils/gn/secondary/llvm/unittests/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/BUILD.gn index 3b8f5f270fc..89cb9b6724b 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/BUILD.gn @@ -51,11 +51,9 @@ group("unittests") { "tools/llvm-exegesis/AArch64:LLVMExegesisAArch64Tests", ] } - - # FIXME: Add ARM once the Targets exists. - #if (llvm_build_ARM) { - #deps += [ "tools/llvm-exegesis/ARM:LLVMExegesisARMTests" ] - #} + if (llvm_build_ARM) { + deps += [ "tools/llvm-exegesis/ARM:LLVMExegesisARMTests" ] + } if (llvm_build_X86) { deps += [ "tools/llvm-exegesis/X86:LLVMExegesisX86Tests" ] } diff --git a/llvm/utils/gn/secondary/llvm/unittests/tools/llvm-exegesis/ARM/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/tools/llvm-exegesis/ARM/BUILD.gn new file mode 100644 index 00000000000..6c4f768b730 --- /dev/null +++ b/llvm/utils/gn/secondary/llvm/unittests/tools/llvm-exegesis/ARM/BUILD.gn @@ -0,0 +1,25 @@ +import("//llvm/utils/unittest/unittest.gni") + +unittest("LLVMExegesisARMTests") { + deps = [ + "//llvm/lib/DebugInfo/Symbolize", + "//llvm/lib/MC", + "//llvm/lib/MC/MCParser", + "//llvm/lib/Object", + "//llvm/lib/Support", + "//llvm/lib/Target/ARM", + + # Exegesis reaches inside the Target/ARM tablegen internals and must + # depend on these Target/ARM-internal build targets. + "//llvm/lib/Target/ARM/MCTargetDesc", + "//llvm/lib/Target/ARM/Utils", + "//llvm/tools/llvm-exegesis/lib", + ] + include_dirs = [ + "//llvm/lib/Target/ARM", + "//llvm/tools/llvm-exegesis/lib", + ] + sources = [ + "AssemblerTest.cpp", + ] +} |
