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-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp4
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h1
-rw-r--r--llvm/lib/Target/Mips/MipsISelLowering.cpp16
-rw-r--r--llvm/test/CodeGen/Mips/atomic.ll157
4 files changed, 105 insertions, 73 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index cdcc3923b81..5fda05a5b4e 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -118,6 +118,10 @@ unsigned MipsABIInfo::GetPtrAddiuOp() const {
return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
}
+unsigned MipsABIInfo::GetPtrAndOp() const {
+ return ArePtrs64bit() ? Mips::AND64 : Mips::AND;
+}
+
unsigned MipsABIInfo::GetGPRMoveOp() const {
return ArePtrs64bit() ? Mips::OR64 : Mips::OR;
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
index ac09a4bef8c..31e6a3ed5ac 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
@@ -70,6 +70,7 @@ public:
unsigned GetZeroReg() const;
unsigned GetPtrAdduOp() const;
unsigned GetPtrAddiuOp() const;
+ unsigned GetPtrAndOp() const;
unsigned GetGPRMoveOp() const;
inline bool ArePtrs64bit() const { return IsN64(); }
inline bool AreGprs64bit() const { return IsN32() || IsN64(); }
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index fe072911490..818bb68d959 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -1225,6 +1225,9 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &RegInfo = MF->getRegInfo();
const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
+ bool ArePtrs64bit = ABI.ArePtrs64bit();
+ const TargetRegisterClass *RCp =
+ getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
DebugLoc DL = MI->getDebugLoc();
@@ -1232,14 +1235,14 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
unsigned Ptr = MI->getOperand(1).getReg();
unsigned Incr = MI->getOperand(2).getReg();
- unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
+ unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
unsigned Mask = RegInfo.createVirtualRegister(RC);
unsigned Mask2 = RegInfo.createVirtualRegister(RC);
unsigned NewVal = RegInfo.createVirtualRegister(RC);
unsigned OldVal = RegInfo.createVirtualRegister(RC);
unsigned Incr2 = RegInfo.createVirtualRegister(RC);
- unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
+ unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
unsigned AndRes = RegInfo.createVirtualRegister(RC);
@@ -1281,11 +1284,12 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
// sll incr2,incr,shiftamt
int64_t MaskImm = (Size == 1) ? 255 : 65535;
- BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
- .addReg(Mips::ZERO).addImm(-4);
- BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
+ BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
+ .addReg(ABI.GetNullPtr()).addImm(-4);
+ BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
.addReg(Ptr).addReg(MaskLSB2);
- BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
+ BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
+ .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
if (Subtarget.isLittle()) {
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
} else {
diff --git a/llvm/test/CodeGen/Mips/atomic.ll b/llvm/test/CodeGen/Mips/atomic.ll
index 82002d0e635..91a71721ec9 100644
--- a/llvm/test/CodeGen/Mips/atomic.ll
+++ b/llvm/test/CodeGen/Mips/atomic.ll
@@ -5,7 +5,8 @@
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MIPSR6
-; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS
+; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL-LABEL -check-prefix=MIPS64-ANY -check-prefix=O0
+;; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips -relocation-model=pic < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS
; Keep one big-endian check so that we don't reduce testing, but don't add more
; since endianness doesn't affect the body of the atomic operations.
@@ -23,13 +24,17 @@ entry:
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
+; O0: $[[BB0:[A-Z_0-9]+]]:
+; O0: ld $[[R1:[0-9]+]]
+; O0-NEXT: ll $[[R2:[0-9]+]], 0($[[R1]])
+
; ALL: $[[BB0:[A-Z_0-9]+]]:
-; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])
-; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4
-; ALL: sc $[[R2]], 0($[[R0]])
-; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
-; MICROMIPS: beqzc $[[R2]], $[[BB0]]
-; MIPSR6: beqzc $[[R2]], $[[BB0]]
+; ALL: ll $[[R3:[0-9]+]], 0($[[R0]])
+; ALL: addu $[[R4:[0-9]+]], $[[R3]], $4
+; ALL: sc $[[R4]], 0($[[R0]])
+; NOT-MICROMIPS: beqz $[[R4]], $[[BB0]]
+; MICROMIPS: beqzc $[[R4]], $[[BB0]]
+; MIPSR6: beqzc $[[R4]], $[[BB0]]
}
define i32 @AtomicLoadNand32(i32 signext %incr) nounwind {
@@ -42,6 +47,8 @@ entry:
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
+
+
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])
; ALL: and $[[R3:[0-9]+]], $[[R1]], $4
@@ -124,24 +131,28 @@ entry:
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
+; O0: $[[BB0:[A-Z_0-9]+]]:
+; O0: ld $[[R10:[0-9]+]]
+; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
+
; ALL: $[[BB0:[A-Z_0-9]+]]:
-; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
-; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
-; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
-; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
-; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
-; ALL: sc $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
-; MICROMIPS: beqzc $[[R14]], $[[BB0]]
-; MIPSR6: beqzc $[[R14]], $[[BB0]]
+; ALL: ll $[[R12:[0-9]+]], 0($[[R2]])
+; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
+; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
+; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
+; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
+; ALL: sc $[[R16]], 0($[[R2]])
+; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
+; MICROMIPS: beqzc $[[R16]], $[[BB0]]
+; MIPSR6: beqzc $[[R16]], $[[BB0]]
-; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
-; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]]
+; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
-; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
-; NO-SEB-SEH: sra $2, $[[R17]], 24
+; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24
+; NO-SEB-SEH: sra $2, $[[R19]], 24
-; HAS-SEB-SEH: seb $2, $[[R16]]
+; HAS-SEB-SEH: seb $2, $[[R18]]
}
define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
@@ -165,24 +176,28 @@ entry:
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
+; O0: $[[BB0:[A-Z_0-9]+]]:
+; O0: ld $[[R10:[0-9]+]]
+; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
+
; ALL: $[[BB0:[A-Z_0-9]+]]:
-; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
-; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
-; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
-; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
-; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
-; ALL: sc $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
-; MICROMIPS: beqzc $[[R14]], $[[BB0]]
-; MIPSR6: beqzc $[[R14]], $[[BB0]]
+; ALL: ll $[[R12:[0-9]+]], 0($[[R2]])
+; ALL: subu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
+; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
+; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
+; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
+; ALL: sc $[[R16]], 0($[[R2]])
+; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
+; MICROMIPS: beqzc $[[R16]], $[[BB0]]
+; MIPSR6: beqzc $[[R16]], $[[BB0]]
-; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
-; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]]
+; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
-; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
-; NO-SEB-SEH: sra $2, $[[R17]], 24
+; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24
+; NO-SEB-SEH: sra $2, $[[R19]], 24
-; HAS-SEB-SEH:seb $2, $[[R16]]
+; HAS-SEB-SEH:seb $2, $[[R18]]
}
define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
@@ -206,25 +221,29 @@ entry:
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
-; ALL: $[[BB0:[A-Z_0-9]+]]:
-; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
-; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
-; ALL: nor $[[R11:[0-9]+]], $zero, $[[R18]]
-; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
-; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
-; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
-; ALL: sc $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
-; MICROMIPS: beqzc $[[R14]], $[[BB0]]
-; MIPSR6: beqzc $[[R14]], $[[BB0]]
+; O0: $[[BB0:[A-Z_0-9]+]]:
+; O0: ld $[[R10:[0-9]+]]
+; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
-; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
-; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
-
-; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24
-; NO-SEB-SEH: sra $2, $[[R17]], 24
-
-; HAS-SEB-SEH: seb $2, $[[R16]]
+; ALL: $[[BB0:[A-Z_0-9]+]]:
+; ALL: ll $[[R12:[0-9]+]], 0($[[R2]])
+; ALL: and $[[R13:[0-9]+]], $[[R12]], $[[R9]]
+; ALL: nor $[[R14:[0-9]+]], $zero, $[[R13]]
+; ALL: and $[[R15:[0-9]+]], $[[R14]], $[[R7]]
+; ALL: and $[[R16:[0-9]+]], $[[R12]], $[[R8]]
+; ALL: or $[[R17:[0-9]+]], $[[R16]], $[[R15]]
+; ALL: sc $[[R17]], 0($[[R2]])
+; NOT-MICROMIPS: beqz $[[R17]], $[[BB0]]
+; MICROMIPS: beqzc $[[R17]], $[[BB0]]
+; MIPSR6: beqzc $[[R17]], $[[BB0]]
+
+; ALL: and $[[R18:[0-9]+]], $[[R12]], $[[R7]]
+; ALL: srlv $[[R19:[0-9]+]], $[[R18]], $[[R5]]
+
+; NO-SEB-SEH: sll $[[R20:[0-9]+]], $[[R19]], 24
+; NO-SEB-SEH: sra $2, $[[R20]], 24
+
+; HAS-SEB-SEH: seb $2, $[[R19]]
}
define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
@@ -394,24 +413,28 @@ entry:
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
+; O0: $[[BB0:[A-Z_0-9]+]]:
+; O0: ld $[[R10:[0-9]+]]
+; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]])
+
; ALL: $[[BB0:[A-Z_0-9]+]]:
-; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
-; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
-; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
-; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
-; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
-; ALL: sc $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
-; MICROMIPS: beqzc $[[R14]], $[[BB0]]
-; MIPSR6: beqzc $[[R14]], $[[BB0]]
+; ALL: ll $[[R12:[0-9]+]], 0($[[R2]])
+; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]]
+; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
+; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]]
+; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]]
+; ALL: sc $[[R16]], 0($[[R2]])
+; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
+; MICROMIPS: beqzc $[[R16]], $[[BB0]]
+; MIPSR6: beqzc $[[R16]], $[[BB0]]
-; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
-; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]]
+; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]]
-; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 16
-; NO-SEB-SEH: sra $2, $[[R17]], 16
+; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 16
+; NO-SEB-SEH: sra $2, $[[R19]], 16
-; MIPS32R2: seh $2, $[[R16]]
+; MIPS32R2: seh $2, $[[R18]]
}
; Test that the i16 return value from cmpxchg is recognised as signed,
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