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-rw-r--r--llvm/lib/Target/ARM/ARMBaseInstrInfo.h18
-rw-r--r--llvm/lib/Target/ARM/ARMFastISel.cpp8
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp30
-rw-r--r--llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp27
-rw-r--r--llvm/lib/Target/ARM/Thumb2SizeReduction.cpp16
-rw-r--r--llvm/lib/Target/ARM/ThumbRegisterInfo.cpp15
6 files changed, 55 insertions, 59 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 0e1cb5c87b7..a02c66ee9e2 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -416,17 +416,13 @@ static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
return MachineOperand::CreateReg(CCReg, 0);
}
-// FIXME: Replace with something that returns a MachineOperand directly.
-static inline
-const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
- bool isDead = false) {
- return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
-}
-
-// FIXME: Replace with something that returns a MachineOperand
-static inline
-const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
- return MIB.addReg(0);
+/// Get the operand corresponding to the conditional code result for Thumb1.
+/// This operand will always refer to CPSR and it will have the Define flag set.
+/// You can optionally set the Dead flag by means of \p isDead.
+static inline MachineOperand t1CondCodeOp(bool isDead = false) {
+ return MachineOperand::CreateReg(ARM::CPSR,
+ /*Define*/ true, /*Implicit*/ false,
+ /*Kill*/ false, isDead);
}
static inline
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index f27591f5a39..b4d5eccef81 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -261,12 +261,8 @@ ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
// Do we optionally set a predicate? Preds is size > 0 iff the predicate
// defines CPSR. All other OptionalDefines in ARM are the CCR register.
bool CPSR = false;
- if (DefinesOptionalPredicate(MI, &CPSR)) {
- if (CPSR)
- AddDefaultT1CC(MIB);
- else
- MIB.add(condCodeOp());
- }
+ if (DefinesOptionalPredicate(MI, &CPSR))
+ MIB.add(CPSR ? t1CondCodeOp() : condCodeOp());
return MIB;
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index fc18fbd85b2..88755589d43 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -8413,11 +8413,11 @@ static void emitPostLd(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos,
.addReg(AddrIn)
.addImm(0)
.add(predOps(ARMCC::AL));
- MachineInstrBuilder MIB =
- BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
- MIB = AddDefaultT1CC(MIB);
- MIB.addReg(AddrIn).addImm(LdSize);
- MIB.add(predOps(ARMCC::AL));
+ BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut)
+ .add(t1CondCodeOp())
+ .addReg(AddrIn)
+ .addImm(LdSize)
+ .add(predOps(ARMCC::AL));
} else if (IsThumb2) {
BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
.addReg(AddrOut, RegState::Define)
@@ -8455,11 +8455,11 @@ static void emitPostSt(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos,
.addReg(AddrIn)
.addImm(0)
.add(predOps(ARMCC::AL));
- MachineInstrBuilder MIB =
- BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
- MIB = AddDefaultT1CC(MIB);
- MIB.addReg(AddrIn).addImm(StSize);
- MIB.add(predOps(ARMCC::AL));
+ BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut)
+ .add(t1CondCodeOp())
+ .addReg(AddrIn)
+ .addImm(StSize)
+ .add(predOps(ARMCC::AL));
} else if (IsThumb2) {
BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
.addReg(Data)
@@ -8670,11 +8670,11 @@ ARMTargetLowering::EmitStructByval(MachineInstr &MI,
// Decrement loop variable by UnitSize.
if (IsThumb1) {
- MachineInstrBuilder MIB =
- BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
- MIB = AddDefaultT1CC(MIB);
- MIB.addReg(varPhi).addImm(UnitSize);
- MIB.add(predOps(ARMCC::AL));
+ BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop)
+ .add(t1CondCodeOp())
+ .addReg(varPhi)
+ .addImm(UnitSize)
+ .add(predOps(ARMCC::AL));
} else {
MachineInstrBuilder MIB =
BuildMI(*BB, BB->end(), dl,
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 1bfcb720167..1dd4c9e6598 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -517,8 +517,12 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
if (InsertSub) {
// An instruction above couldn't be updated, so insert a sub.
- AddDefaultT1CC(BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base), true)
- .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
+ BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
+ .add(t1CondCodeOp(true))
+ .addReg(Base)
+ .addImm(WordOffset * 4)
+ .addImm(Pred)
+ .addReg(PredReg);
return;
}
@@ -534,9 +538,12 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
// information and *always* have to reset at the end of a block.
// See PR21029.
if (MBBI != MBB.end()) --MBBI;
- AddDefaultT1CC(
- BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base), true)
- .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
+ BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
+ .add(t1CondCodeOp(true))
+ .addReg(Base)
+ .addImm(WordOffset * 4)
+ .addImm(Pred)
+ .addReg(PredReg);
}
}
@@ -713,10 +720,12 @@ MachineInstr *ARMLoadStoreOpt::CreateLoadStoreMulti(
.addReg(Base, getKillRegState(KillOldBase)).addImm(Offset/4)
.addImm(Pred).addReg(PredReg);
} else
- AddDefaultT1CC(
- BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase), true)
- .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset)
- .addImm(Pred).addReg(PredReg);
+ BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
+ .add(t1CondCodeOp(true))
+ .addReg(Base, getKillRegState(KillOldBase))
+ .addImm(Offset)
+ .addImm(Pred)
+ .addReg(PredReg);
} else {
BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
.addReg(Base, getKillRegState(KillOldBase)).addImm(Offset)
diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
index 109c1f55c9b..6b7f2e775ba 100644
--- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -787,12 +787,8 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
DebugLoc dl = MI->getDebugLoc();
MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
MIB.add(MI->getOperand(0));
- if (NewMCID.hasOptionalDef()) {
- if (HasCC)
- AddDefaultT1CC(MIB, CCDead);
- else
- AddNoT1CC(MIB);
- }
+ if (NewMCID.hasOptionalDef())
+ MIB.add(HasCC ? t1CondCodeOp(CCDead) : condCodeOp());
// Transfer the rest of operands.
unsigned NumOps = MCID.getNumOperands();
@@ -882,12 +878,8 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
DebugLoc dl = MI->getDebugLoc();
MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
MIB.add(MI->getOperand(0));
- if (NewMCID.hasOptionalDef()) {
- if (HasCC)
- AddDefaultT1CC(MIB, CCDead);
- else
- AddNoT1CC(MIB);
- }
+ if (NewMCID.hasOptionalDef())
+ MIB.add(HasCC ? t1CondCodeOp(CCDead) : condCodeOp());
// Transfer the rest of operands.
unsigned NumOps = MCID.getNumOperands();
diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
index d8c6fce9830..92025bbb992 100644
--- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
@@ -145,14 +145,17 @@ static void emitThumbRegPlusImmInReg(
LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
if (NumBytes <= 255 && NumBytes >= 0 && CanChangeCC) {
- AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
+ .add(t1CondCodeOp())
.addImm(NumBytes)
.setMIFlags(MIFlags);
} else if (NumBytes < 0 && NumBytes >= -255 && CanChangeCC) {
- AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
+ .add(t1CondCodeOp())
.addImm(NumBytes)
.setMIFlags(MIFlags);
- AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)
+ .add(t1CondCodeOp())
.addReg(LdReg, RegState::Kill)
.setMIFlags(MIFlags);
} else if (ST.genExecuteOnly()) {
@@ -167,7 +170,7 @@ static void emitThumbRegPlusImmInReg(
: ((isHigh || !CanChangeCC) ? ARM::tADDhirr : ARM::tADDrr);
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
if (Opc != ARM::tADDhirr)
- MIB = AddDefaultT1CC(MIB);
+ MIB = MIB.add(t1CondCodeOp());
if (DestReg == ARM::SP || isSub)
MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
else
@@ -307,7 +310,7 @@ void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
if (CopyNeedsCC)
- MIB = AddDefaultT1CC(MIB);
+ MIB = MIB.add(t1CondCodeOp());
MIB.addReg(BaseReg, RegState::Kill);
if (CopyOpc != ARM::tMOVr) {
MIB.addImm(CopyImm);
@@ -324,7 +327,7 @@ void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg);
if (ExtraNeedsCC)
- MIB = AddDefaultT1CC(MIB);
+ MIB = MIB.add(t1CondCodeOp());
MIB.addReg(BaseReg)
.addImm(ExtraImm)
.add(predOps(ARMCC::AL))
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