diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86RegisterInfo.td | 2 |
2 files changed, 1 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index c1da3db7cec..5d2d072507b 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -174,8 +174,7 @@ X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, case 2: // NOREX GPRs. if (Subtarget.isTarget64BitLP64()) return &X86::GR64_NOREXRegClass; - return Is64Bit ? &X86::X32_NOREX_ADDR_ACCESSRegClass - : &X86::GR32_NOREXRegClass; + return &X86::GR32_NOREXRegClass; case 3: // NOREX GPRs except the stack pointer (for encoding reasons). if (Subtarget.isTarget64BitLP64()) return &X86::GR64_NOREX_NOSPRegClass; diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td index ef02914ae27..207182f0aaa 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.td +++ b/llvm/lib/Target/X86/X86RegisterInfo.td @@ -423,8 +423,6 @@ def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, // FIXME: We could allow all 64bit registers, but we would need // something to check that the 32 high bits are not set. def X32_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, (add GR32, RIP)>; -def X32_NOREX_ADDR_ACCESS : RegisterClass<"X86", [i32], 64, - (add GR32_NOREX, RIP)>; // A class to support the 'A' assembler constraint: EAX then EDX. def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; |
