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-rw-r--r--llvm/lib/Target/PowerPC/P9InstrResources.td1
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.cpp1
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td4
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrVSX.td42
-rw-r--r--llvm/test/CodeGen/PowerPC/build-vector-allones.ll20
-rw-r--r--llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll4
-rw-r--r--llvm/test/CodeGen/PowerPC/sat-add.ll68
-rw-r--r--llvm/test/CodeGen/PowerPC/setcc-logic.ll8
-rw-r--r--llvm/test/CodeGen/PowerPC/signbit-shift.ll4
-rw-r--r--llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll2
-rw-r--r--llvm/test/CodeGen/PowerPC/vselect-constants.ll4
11 files changed, 88 insertions, 70 deletions
diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td
index 3e2547882a6..48c04996fb0 100644
--- a/llvm/lib/Target/PowerPC/P9InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -64,6 +64,7 @@ def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
XXLAND,
XXLANDC,
XXLEQV,
+ XXLEQVOnes,
XXLNAND,
XXLNOR,
XXLOR,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 7ffbab72d95..f65eeebc517 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -335,6 +335,7 @@ bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
case PPC::XXLXORz:
case PPC::XXLXORspz:
case PPC::XXLXORdpz:
+ case PPC::XXLEQVOnes:
case PPC::V_SET0B:
case PPC::V_SET0H:
case PPC::V_SET0:
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index a9b0ce2f800..188c36f233d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -386,7 +386,9 @@ def immZExt16 : PatLeaf<(imm), [{
// field. Used by instructions like 'ori'.
return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
}], LO16>;
-def immAnyExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm) || isUInt<8>(Imm); }]>;
+def immNonAllOneAnyExt8 : ImmLeaf<i32, [{
+ return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF));
+}]>;
def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>;
// imm16Shifted* - These match immediates where the low 16-bits are zero. There
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index c144a28d553..787545c7d55 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1310,6 +1310,13 @@ let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
def : Pat<(int_ppc_vsx_xxleqv v4i32:$A, v4i32:$B),
(XXLEQV $A, $B)>;
+ let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
+ isReMaterializable = 1 in {
+ def XXLEQVOnes : XX3Form_SameOp<60, 186, (outs vsrc:$XT), (ins),
+ "xxleqv $XT, $XT, $XT", IIC_VecGeneral,
+ [(set v4i32:$XT, (v4i32 immAllOnesV))]>;
+ }
+
def XXLORC : XX3Form<60, 170,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xxlorc $XT, $XA, $XB", IIC_VecGeneral,
@@ -4095,27 +4102,34 @@ let AddedComplexity = 400 in {
(XXSPLTW (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 1)>;
}
+ let Predicates = [HasP8Vector] in {
+ def : Pat<(v4i32 (bitconvert (v16i8 immAllOnesV))),
+ (XXLEQVOnes)>;
+ def : Pat<(v1i128 (bitconvert (v16i8 immAllOnesV))),
+ (v1i128 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+ def : Pat<(v2i64 (bitconvert (v16i8 immAllOnesV))),
+ (v2i64 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+ def : Pat<(v8i16 (bitconvert (v16i8 immAllOnesV))),
+ (v8i16 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+ def : Pat<(v16i8 (bitconvert (v16i8 immAllOnesV))),
+ (v16i8 (COPY_TO_REGCLASS(XXLEQVOnes), VSRC))>;
+ }
+
let Predicates = [HasP9Vector] in {
// Endianness-neutral patterns for const splats with ISA 3.0 instructions.
def : Pat<(v4i32 (scalar_to_vector i32:$A)),
(v4i32 (MTVSRWS $A))>;
def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
(v4i32 (MTVSRWS $A))>;
- def : Pat<(v16i8 (build_vector immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
- immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
- immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
- immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
- immAnyExt8:$A, immAnyExt8:$A, immAnyExt8:$A,
- immAnyExt8:$A)),
+ def : Pat<(v16i8 (build_vector immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
+ immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
+ immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
+ immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
+ immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
+ immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
+ immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A,
+ immNonAllOneAnyExt8:$A, immNonAllOneAnyExt8:$A)),
(v16i8 (COPY_TO_REGCLASS (XXSPLTIB imm:$A), VSRC))>;
- def : Pat<(v16i8 immAllOnesV),
- (v16i8 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
- def : Pat<(v8i16 immAllOnesV),
- (v8i16 (COPY_TO_REGCLASS (XXSPLTIB 255), VSRC))>;
- def : Pat<(v4i32 immAllOnesV),
- (v4i32 (XXSPLTIB 255))>;
- def : Pat<(v2i64 immAllOnesV),
- (v2i64 (XXSPLTIB 255))>;
def : Pat<(v4i32 (scalar_to_vector FltToIntLoad.A)),
(v4i32 (XVCVSPSXWS (LXVWSX xoaddr:$A)))>;
def : Pat<(v4i32 (scalar_to_vector FltToUIntLoad.A)),
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-allones.ll b/llvm/test/CodeGen/PowerPC/build-vector-allones.ll
index 1a4ad1e1235..fcec36703cb 100644
--- a/llvm/test/CodeGen/PowerPC/build-vector-allones.ll
+++ b/llvm/test/CodeGen/PowerPC/build-vector-allones.ll
@@ -19,12 +19,12 @@ define <1 x i128> @One1i128() {
;
; P8LE-LABEL: One1i128:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: vspltisb v2, -1
+; P8LE-NEXT: xxleqv vs34, vs34, vs34
; P8LE-NEXT: blr
;
; P9LE-LABEL: One1i128:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: xxspltib vs34, 255
+; P9LE-NEXT: xxleqv vs34, vs34, vs34
; P9LE-NEXT: blr
entry:
ret <1 x i128> <i128 -1>
@@ -40,12 +40,12 @@ define <2 x i64> @One2i64() {
;
; P8LE-LABEL: One2i64:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: vspltisb v2, -1
+; P8LE-NEXT: xxleqv vs34, vs34, vs34
; P8LE-NEXT: blr
;
; P9LE-LABEL: One2i64:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: xxspltib vs34, 255
+; P9LE-NEXT: xxleqv vs34, vs34, vs34
; P9LE-NEXT: blr
entry:
ret <2 x i64> <i64 -1, i64 -1>
@@ -59,12 +59,12 @@ define <4 x i32> @One4i32() {
;
; P8LE-LABEL: One4i32:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: vspltisb v2, -1
+; P8LE-NEXT: xxleqv vs34, vs34, vs34
; P8LE-NEXT: blr
;
; P9LE-LABEL: One4i32:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: xxspltib vs34, 255
+; P9LE-NEXT: xxleqv vs34, vs34, vs34
; P9LE-NEXT: blr
entry:
ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -78,12 +78,12 @@ define <8 x i16> @One8i16() {
;
; P8LE-LABEL: One8i16:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: vspltisb v2, -1
+; P8LE-NEXT: xxleqv vs34, vs34, vs34
; P8LE-NEXT: blr
;
; P9LE-LABEL: One8i16:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: xxspltib vs34, 255
+; P9LE-NEXT: xxleqv vs34, vs34, vs34
; P9LE-NEXT: blr
entry:
ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
@@ -97,12 +97,12 @@ define <16 x i8> @One16i8() {
;
; P8LE-LABEL: One16i8:
; P8LE: # %bb.0: # %entry
-; P8LE-NEXT: vspltisb v2, -1
+; P8LE-NEXT: xxleqv vs34, vs34, vs34
; P8LE-NEXT: blr
;
; P9LE-LABEL: One16i8:
; P9LE: # %bb.0: # %entry
-; P9LE-NEXT: xxspltib vs34, 255
+; P9LE-NEXT: xxleqv vs34, vs34, vs34
; P9LE-NEXT: blr
entry:
ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
diff --git a/llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll b/llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll
index d5468902b6b..cf970928fdb 100644
--- a/llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll
+++ b/llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll
@@ -217,12 +217,12 @@ entry:
define <16 x i8> @test12() {
; CHECK-LABEL: test12:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xxspltib v2, 255
+; CHECK-NEXT: xxleqv v2, v2, v2
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: test12:
; CHECK-BE: # %bb.0: # %entry
-; CHECK-BE-NEXT: xxspltib v2, 255
+; CHECK-BE-NEXT: xxleqv v2, v2, v2
; CHECK-BE-NEXT: blr
entry:
diff --git a/llvm/test/CodeGen/PowerPC/sat-add.ll b/llvm/test/CodeGen/PowerPC/sat-add.ll
index 2ebbc62465a..932a3f786a1 100644
--- a/llvm/test/CodeGen/PowerPC/sat-add.ll
+++ b/llvm/test/CodeGen/PowerPC/sat-add.ll
@@ -396,12 +396,12 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI25_0@toc@ha
-; CHECK-NEXT: vspltisb 4, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: addi 3, 3, .LCPI25_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3
; CHECK-NEXT: vaddubm 3, 2, 3
; CHECK-NEXT: vcmpgtub 2, 2, 3
-; CHECK-NEXT: xxsel 34, 35, 36, 34
+; CHECK-NEXT: xxsel 34, 35, 0, 34
; CHECK-NEXT: blr
%a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
%c = icmp ugt <16 x i8> %x, %a
@@ -413,7 +413,7 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
; CHECK-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI26_1@toc@ha
-; CHECK-NEXT: vspltisb 5, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: addi 3, 3, .LCPI26_1@toc@l
; CHECK-NEXT: lvx 3, 0, 3
; CHECK-NEXT: addis 3, 2, .LCPI26_0@toc@ha
@@ -421,7 +421,7 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
; CHECK-NEXT: vcmpgtub 3, 2, 3
; CHECK-NEXT: lvx 4, 0, 3
; CHECK-NEXT: vaddubm 2, 2, 4
-; CHECK-NEXT: xxsel 34, 34, 37, 35
+; CHECK-NEXT: xxsel 34, 34, 0, 35
; CHECK-NEXT: blr
%a = add <16 x i8> %x, <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>
%c = icmp ugt <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
@@ -451,12 +451,12 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_sum(<8 x i16> %x) {
; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI28_0@toc@ha
-; CHECK-NEXT: vspltisb 4, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: addi 3, 3, .LCPI28_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3
; CHECK-NEXT: vadduhm 3, 2, 3
; CHECK-NEXT: vcmpgtuh 2, 2, 3
-; CHECK-NEXT: xxsel 34, 35, 36, 34
+; CHECK-NEXT: xxsel 34, 35, 0, 34
; CHECK-NEXT: blr
%a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
%c = icmp ugt <8 x i16> %x, %a
@@ -468,7 +468,7 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {
; CHECK-LABEL: unsigned_sat_constant_v8i16_using_cmp_notval:
; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI29_1@toc@ha
-; CHECK-NEXT: vspltisb 5, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: addi 3, 3, .LCPI29_1@toc@l
; CHECK-NEXT: lvx 3, 0, 3
; CHECK-NEXT: addis 3, 2, .LCPI29_0@toc@ha
@@ -476,7 +476,7 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_cmp_notval(<8 x i16> %x) {
; CHECK-NEXT: vcmpgtuh 3, 2, 3
; CHECK-NEXT: lvx 4, 0, 3
; CHECK-NEXT: vadduhm 2, 2, 4
-; CHECK-NEXT: xxsel 34, 34, 37, 35
+; CHECK-NEXT: xxsel 34, 34, 0, 35
; CHECK-NEXT: blr
%a = add <8 x i16> %x, <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>
%c = icmp ugt <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
@@ -506,12 +506,12 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI31_0@toc@ha
-; CHECK-NEXT: vspltisb 4, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: addi 3, 3, .LCPI31_0@toc@l
; CHECK-NEXT: lvx 3, 0, 3
; CHECK-NEXT: vadduwm 3, 2, 3
; CHECK-NEXT: vcmpgtuw 2, 2, 3
-; CHECK-NEXT: xxsel 34, 35, 36, 34
+; CHECK-NEXT: xxsel 34, 35, 0, 34
; CHECK-NEXT: blr
%a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
%c = icmp ugt <4 x i32> %x, %a
@@ -523,7 +523,7 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
; CHECK-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI32_1@toc@ha
-; CHECK-NEXT: vspltisb 5, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: addi 3, 3, .LCPI32_1@toc@l
; CHECK-NEXT: lvx 3, 0, 3
; CHECK-NEXT: addis 3, 2, .LCPI32_0@toc@ha
@@ -531,7 +531,7 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
; CHECK-NEXT: vcmpgtuw 3, 2, 3
; CHECK-NEXT: lvx 4, 0, 3
; CHECK-NEXT: vadduwm 2, 2, 4
-; CHECK-NEXT: xxsel 34, 34, 37, 35
+; CHECK-NEXT: xxsel 34, 34, 0, 35
; CHECK-NEXT: blr
%a = add <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
%c = icmp ugt <4 x i32> %x, <i32 -43, i32 -43, i32 -43, i32 -43>
@@ -563,13 +563,13 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI34_0@toc@ha
-; CHECK-NEXT: vspltisb 4, -1
; CHECK-NEXT: addi 3, 3, .LCPI34_0@toc@l
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: xxswapd 35, 0
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: vaddudm 3, 2, 3
; CHECK-NEXT: vcmpgtud 2, 2, 3
-; CHECK-NEXT: xxsel 34, 35, 36, 34
+; CHECK-NEXT: xxsel 34, 35, 0, 34
; CHECK-NEXT: blr
%a = add <2 x i64> %x, <i64 42, i64 42>
%c = icmp ugt <2 x i64> %x, %a
@@ -581,17 +581,17 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
; CHECK-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval:
; CHECK: # %bb.0:
; CHECK-NEXT: addis 3, 2, .LCPI35_1@toc@ha
-; CHECK-NEXT: vspltisb 5, -1
; CHECK-NEXT: addi 3, 3, .LCPI35_1@toc@l
; CHECK-NEXT: lxvd2x 0, 0, 3
; CHECK-NEXT: addis 3, 2, .LCPI35_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI35_0@toc@l
+; CHECK-NEXT: lxvd2x 1, 0, 3
; CHECK-NEXT: xxswapd 35, 0
-; CHECK-NEXT: lxvd2x 0, 0, 3
+; CHECK-NEXT: xxleqv 0, 0, 0
+; CHECK-NEXT: xxswapd 36, 1
; CHECK-NEXT: vcmpgtud 3, 2, 3
-; CHECK-NEXT: xxswapd 36, 0
; CHECK-NEXT: vaddudm 2, 2, 4
-; CHECK-NEXT: xxsel 34, 34, 37, 35
+; CHECK-NEXT: xxsel 34, 34, 0, 35
; CHECK-NEXT: blr
%a = add <2 x i64> %x, <i64 42, i64 42>
%c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43>
@@ -617,9 +617,9 @@ define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_sum(<16 x i8> %x, <16 x
; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: vaddubm 3, 2, 3
-; CHECK-NEXT: vspltisb 4, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: vcmpgtub 2, 2, 3
-; CHECK-NEXT: xxsel 34, 35, 36, 34
+; CHECK-NEXT: xxsel 34, 35, 0, 34
; CHECK-NEXT: blr
%a = add <16 x i8> %x, %y
%c = icmp ugt <16 x i8> %x, %a
@@ -631,10 +631,10 @@ define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_notval(<16 x i8> %x, <16
; CHECK-LABEL: unsigned_sat_variable_v16i8_using_cmp_notval:
; CHECK: # %bb.0:
; CHECK-NEXT: xxlnor 36, 35, 35
-; CHECK-NEXT: vspltisb 5, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: vcmpgtub 4, 2, 4
; CHECK-NEXT: vaddubm 2, 2, 3
-; CHECK-NEXT: xxsel 34, 34, 37, 36
+; CHECK-NEXT: xxsel 34, 34, 0, 36
; CHECK-NEXT: blr
%noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%a = add <16 x i8> %x, %y
@@ -661,9 +661,9 @@ define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_sum(<8 x i16> %x, <8 x i
; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: vadduhm 3, 2, 3
-; CHECK-NEXT: vspltisb 4, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: vcmpgtuh 2, 2, 3
-; CHECK-NEXT: xxsel 34, 35, 36, 34
+; CHECK-NEXT: xxsel 34, 35, 0, 34
; CHECK-NEXT: blr
%a = add <8 x i16> %x, %y
%c = icmp ugt <8 x i16> %x, %a
@@ -675,10 +675,10 @@ define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_notval(<8 x i16> %x, <8
; CHECK-LABEL: unsigned_sat_variable_v8i16_using_cmp_notval:
; CHECK: # %bb.0:
; CHECK-NEXT: xxlnor 36, 35, 35
-; CHECK-NEXT: vspltisb 5, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: vcmpgtuh 4, 2, 4
; CHECK-NEXT: vadduhm 2, 2, 3
-; CHECK-NEXT: xxsel 34, 34, 37, 36
+; CHECK-NEXT: xxsel 34, 34, 0, 36
; CHECK-NEXT: blr
%noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%a = add <8 x i16> %x, %y
@@ -705,9 +705,9 @@ define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_sum(<4 x i32> %x, <4 x i
; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: vadduwm 3, 2, 3
-; CHECK-NEXT: vspltisb 4, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: vcmpgtuw 2, 2, 3
-; CHECK-NEXT: xxsel 34, 35, 36, 34
+; CHECK-NEXT: xxsel 34, 35, 0, 34
; CHECK-NEXT: blr
%a = add <4 x i32> %x, %y
%c = icmp ugt <4 x i32> %x, %a
@@ -719,10 +719,10 @@ define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4
; CHECK-LABEL: unsigned_sat_variable_v4i32_using_cmp_notval:
; CHECK: # %bb.0:
; CHECK-NEXT: xxlnor 36, 35, 35
-; CHECK-NEXT: vspltisb 5, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: vcmpgtuw 4, 2, 4
; CHECK-NEXT: vadduwm 2, 2, 3
-; CHECK-NEXT: xxsel 34, 34, 37, 36
+; CHECK-NEXT: xxsel 34, 34, 0, 36
; CHECK-NEXT: blr
%noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
%a = add <4 x i32> %x, %y
@@ -749,9 +749,9 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_sum(<2 x i64> %x, <2 x i
; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_sum:
; CHECK: # %bb.0:
; CHECK-NEXT: vaddudm 3, 2, 3
-; CHECK-NEXT: vspltisb 4, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: vcmpgtud 2, 2, 3
-; CHECK-NEXT: xxsel 34, 35, 36, 34
+; CHECK-NEXT: xxsel 34, 35, 0, 34
; CHECK-NEXT: blr
%a = add <2 x i64> %x, %y
%c = icmp ugt <2 x i64> %x, %a
@@ -763,10 +763,10 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2
; CHECK-LABEL: unsigned_sat_variable_v2i64_using_cmp_notval:
; CHECK: # %bb.0:
; CHECK-NEXT: xxlnor 36, 35, 35
-; CHECK-NEXT: vspltisb 5, -1
+; CHECK-NEXT: xxleqv 0, 0, 0
; CHECK-NEXT: vcmpgtud 4, 2, 4
; CHECK-NEXT: vaddudm 2, 2, 3
-; CHECK-NEXT: xxsel 34, 34, 37, 36
+; CHECK-NEXT: xxsel 34, 34, 0, 36
; CHECK-NEXT: blr
%noty = xor <2 x i64> %y, <i64 -1, i64 -1>
%a = add <2 x i64> %x, %y
diff --git a/llvm/test/CodeGen/PowerPC/setcc-logic.ll b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
index 87f73e7b2e8..05eaad8b50a 100644
--- a/llvm/test/CodeGen/PowerPC/setcc-logic.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
@@ -325,7 +325,7 @@ define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: all_sign_bits_clear_vec:
; CHECK: # %bb.0:
-; CHECK-NEXT: vspltisb 4, -1
+; CHECK-NEXT: xxleqv 36, 36, 36
; CHECK-NEXT: xxlor 34, 34, 35
; CHECK-NEXT: vcmpgtsw 2, 2, 4
; CHECK-NEXT: blr
@@ -338,7 +338,7 @@ define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: all_bits_set_vec:
; CHECK: # %bb.0:
-; CHECK-NEXT: vspltisb 4, -1
+; CHECK-NEXT: xxleqv 36, 36, 36
; CHECK-NEXT: xxland 34, 34, 35
; CHECK-NEXT: vcmpequw 2, 2, 4
; CHECK-NEXT: blr
@@ -391,7 +391,7 @@ define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: any_bits_clear_vec:
; CHECK: # %bb.0:
-; CHECK-NEXT: vspltisb 4, -1
+; CHECK-NEXT: xxleqv 36, 36, 36
; CHECK-NEXT: xxland 34, 34, 35
; CHECK-NEXT: vcmpequw 2, 2, 4
; CHECK-NEXT: xxlnor 34, 34, 34
@@ -405,7 +405,7 @@ define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: any_sign_bits_clear_vec:
; CHECK: # %bb.0:
-; CHECK-NEXT: vspltisb 4, -1
+; CHECK-NEXT: xxleqv 36, 36, 36
; CHECK-NEXT: xxland 34, 34, 35
; CHECK-NEXT: vcmpgtsw 2, 2, 4
; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/signbit-shift.ll b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
index d87a24128b9..d66b7fc5161 100644
--- a/llvm/test/CodeGen/PowerPC/signbit-shift.ll
+++ b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
@@ -29,7 +29,7 @@ define i32 @add_zext_ifpos(i32 %x) {
define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_zext_ifpos_vec_splat:
; CHECK: # %bb.0:
-; CHECK-NEXT: vspltisb 3, -1
+; CHECK-NEXT: xxleqv 35, 35, 35
; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l
; CHECK-NEXT: vcmpgtsw 2, 2, 3
@@ -81,7 +81,7 @@ define i32 @add_sext_ifpos(i32 %x) {
define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_sext_ifpos_vec_splat:
; CHECK: # %bb.0:
-; CHECK-NEXT: vspltisb 3, -1
+; CHECK-NEXT: xxleqv 35, 35, 35
; CHECK-NEXT: addis 3, 2, .LCPI6_0@toc@ha
; CHECK-NEXT: addi 3, 3, .LCPI6_0@toc@l
; CHECK-NEXT: vcmpgtsw 2, 2, 3
diff --git a/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll b/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
index 62f17acb8a7..cba2b5a5b8e 100644
--- a/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
@@ -80,7 +80,7 @@ define <2 x i64> @test_sub(<2 x i64> %x, <2 x i64> %y) nounwind {
define <2 x i64> @decrement_by_one(<2 x i64> %x) nounwind {
; VSX-LABEL: decrement_by_one:
; VSX: # %bb.0:
-; VSX-NEXT: vspltisb 3, -1
+; VSX-NEXT: xxleqv 35, 35, 35
; VSX-NEXT: vsubudm 2, 2, 3
; VSX-NEXT: blr
;
diff --git a/llvm/test/CodeGen/PowerPC/vselect-constants.ll b/llvm/test/CodeGen/PowerPC/vselect-constants.ll
index b4264e5ee63..df939d066d6 100644
--- a/llvm/test/CodeGen/PowerPC/vselect-constants.ll
+++ b/llvm/test/CodeGen/PowerPC/vselect-constants.ll
@@ -130,9 +130,9 @@ define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
; CHECK-LABEL: sel_0_or_minus1_vec:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, 1
-; CHECK-NEXT: vspltisb 4, -1
; CHECK-NEXT: xxland 34, 34, 35
-; CHECK-NEXT: vadduwm 2, 2, 4
+; CHECK-NEXT: xxleqv 35, 35, 35
+; CHECK-NEXT: vadduwm 2, 2, 3
; CHECK-NEXT: blr
%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
ret <4 x i32> %add
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