diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/pr38819.ll | 26 |
2 files changed, 28 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 129e0c10a04..d018e01d58c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -39073,7 +39073,8 @@ static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG, // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have // a 32-bit target where SSE doesn't support i64->FP operations. - if (!Subtarget.useSoftFloat() && Op0.getOpcode() == ISD::LOAD) { + if (!Subtarget.useSoftFloat() && Subtarget.hasX87() && + Op0.getOpcode() == ISD::LOAD) { LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); EVT LdVT = Ld->getValueType(0); diff --git a/llvm/test/CodeGen/X86/pr38819.ll b/llvm/test/CodeGen/X86/pr38819.ll new file mode 100644 index 00000000000..11d16250378 --- /dev/null +++ b/llvm/test/CodeGen/X86/pr38819.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse,-sse2,-x87 | FileCheck %s + +define void @foo(i64 %x, float* %b) { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushl %esi +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: .cfi_offset %esi, -8 +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi +; CHECK-NEXT: pushl {{[0-9]+}}(%esp) +; CHECK-NEXT: .cfi_adjust_cfa_offset 4 +; CHECK-NEXT: pushl {{[0-9]+}}(%esp) +; CHECK-NEXT: .cfi_adjust_cfa_offset 4 +; CHECK-NEXT: calll __floatdisf +; CHECK-NEXT: addl $8, %esp +; CHECK-NEXT: .cfi_adjust_cfa_offset -8 +; CHECK-NEXT: movl %eax, (%esi) +; CHECK-NEXT: popl %esi +; CHECK-NEXT: .cfi_def_cfa_offset 4 +; CHECK-NEXT: retl +entry: + %conv = sitofp i64 %x to float + store float %conv, float* %b + ret void +} |
