diff options
102 files changed, 175 insertions, 140 deletions
diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h index 7d17694d3ee..d92ee93268e 100644 --- a/llvm/include/llvm/CodeGen/Passes.h +++ b/llvm/include/llvm/CodeGen/Passes.h @@ -345,8 +345,9 @@ namespace llvm { /// pointer or stack pointer index addressing. extern char &LocalStackSlotAllocationID; - /// ExpandISelPseudos - This pass expands pseudo-instructions. - extern char &ExpandISelPseudosID; + /// This pass expands pseudo-instructions, reserves registers and adjusts + /// machine frame information. + extern char &FinalizeISelID; /// UnpackMachineBundles - This pass unpack machine instruction bundles. extern char &UnpackMachineBundlesID; diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index 6cb359362fe..164d0be2855 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -137,13 +137,13 @@ void initializeEarlyTailDuplicatePass(PassRegistry&); void initializeEdgeBundlesPass(PassRegistry&); void initializeEliminateAvailableExternallyLegacyPassPass(PassRegistry&); void initializeEntryExitInstrumenterPass(PassRegistry&); -void initializeExpandISelPseudosPass(PassRegistry&); void initializeExpandMemCmpPassPass(PassRegistry&); void initializeExpandPostRAPass(PassRegistry&); void initializeExpandReductionsPass(PassRegistry&); void initializeMakeGuardsExplicitLegacyPassPass(PassRegistry&); void initializeExternalAAWrapperPassPass(PassRegistry&); void initializeFEntryInserterPass(PassRegistry&); +void initializeFinalizeISelPass(PassRegistry&); void initializeFinalizeMachineBundlesPass(PassRegistry&); void initializeFlattenCFGPassPass(PassRegistry&); void initializeFloat2IntLegacyPassPass(PassRegistry&); diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt index 7269c54b45f..5d8a1382867 100644 --- a/llvm/lib/CodeGen/CMakeLists.txt +++ b/llvm/lib/CodeGen/CMakeLists.txt @@ -21,12 +21,12 @@ add_llvm_library(LLVMCodeGen EarlyIfConversion.cpp EdgeBundles.cpp ExecutionDomainFix.cpp - ExpandISelPseudos.cpp ExpandMemCmp.cpp ExpandPostRAPseudos.cpp ExpandReductions.cpp FaultMaps.cpp FEntryInserter.cpp + FinalizeISel.cpp FuncletLayout.cpp GCMetadata.cpp GCMetadataPrinter.cpp diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp index 31b6bb7688a..c37ed57781d 100644 --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -30,10 +30,10 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeEarlyIfConverterPass(Registry); initializeEarlyMachineLICMPass(Registry); initializeEarlyTailDuplicatePass(Registry); - initializeExpandISelPseudosPass(Registry); initializeExpandMemCmpPassPass(Registry); initializeExpandPostRAPass(Registry); initializeFEntryInserterPass(Registry); + initializeFinalizeISelPass(Registry); initializeFinalizeMachineBundlesPass(Registry); initializeFuncletLayoutPass(Registry); initializeGCMachineCodeAnalysisPass(Registry); diff --git a/llvm/lib/CodeGen/ExpandISelPseudos.cpp b/llvm/lib/CodeGen/FinalizeISel.cpp index a27c2e3c39f..772d7f71bb3 100644 --- a/llvm/lib/CodeGen/ExpandISelPseudos.cpp +++ b/llvm/lib/CodeGen/FinalizeISel.cpp @@ -1,4 +1,4 @@ -//===-- llvm/CodeGen/ExpandISelPseudos.cpp ----------------------*- C++ -*-===// +//===-- llvm/CodeGen/FinalizeISel.cpp ---------------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,10 +6,11 @@ // //===----------------------------------------------------------------------===// // -// Expand Pseudo-instructions produced by ISel. These are usually to allow -// the expansion to contain control flow, such as a conditional move -// implemented with a conditional branch and a phi, or an atomic operation -// implemented with a loop. +/// This pass expands Pseudo-instructions produced by ISel, fixes register +/// reservations and may do machine frame information adjustments. +/// The pseudo instructions are used to allow the expansion to contain control +/// flow, such as a conditional move implemented with a conditional branch and a +/// phi, or an atomic operation implemented with a loop. // //===----------------------------------------------------------------------===// @@ -21,13 +22,13 @@ #include "llvm/Support/Debug.h" using namespace llvm; -#define DEBUG_TYPE "expand-isel-pseudos" +#define DEBUG_TYPE "finalize-isel" namespace { - class ExpandISelPseudos : public MachineFunctionPass { + class FinalizeISel : public MachineFunctionPass { public: static char ID; // Pass identification, replacement for typeid - ExpandISelPseudos() : MachineFunctionPass(ID) {} + FinalizeISel() : MachineFunctionPass(ID) {} private: bool runOnMachineFunction(MachineFunction &MF) override; @@ -38,12 +39,12 @@ namespace { }; } // end anonymous namespace -char ExpandISelPseudos::ID = 0; -char &llvm::ExpandISelPseudosID = ExpandISelPseudos::ID; -INITIALIZE_PASS(ExpandISelPseudos, DEBUG_TYPE, - "Expand ISel Pseudo-instructions", false, false) +char FinalizeISel::ID = 0; +char &llvm::FinalizeISelID = FinalizeISel::ID; +INITIALIZE_PASS(FinalizeISel, DEBUG_TYPE, + "Finalize ISel and expand pseudo-instructions", false, false) -bool ExpandISelPseudos::runOnMachineFunction(MachineFunction &MF) { +bool FinalizeISel::runOnMachineFunction(MachineFunction &MF) { bool Changed = false; const TargetLowering *TLI = MF.getSubtarget().getTargetLowering(); @@ -69,5 +70,7 @@ bool ExpandISelPseudos::runOnMachineFunction(MachineFunction &MF) { } } + TLI->finalizeLowering(MF); + return Changed; } diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 02f17f3ba74..b40594ffe55 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -218,7 +218,7 @@ namespace { bool isAllocatable(unsigned Reg) const { return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) && - !regsReserved.test(Reg); + !regsReserved.test(Reg); } // Analysis information if available diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 0ad5bf70e31..f5a7c082e5b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -8537,7 +8537,7 @@ void SelectionDAGBuilder::populateCallLoweringInfo( /// avoid constant materialization and register allocation. /// /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not -/// generate addess computation nodes, and so ExpandISelPseudo can convert the +/// generate addess computation nodes, and so FinalizeISel can convert the /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids /// address materialization and register allocation, but may also be required /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index c7a199bf2e0..5c41e6a72a5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -656,6 +656,35 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { // Determine if floating point is used for msvc computeUsesMSVCFloatingPoint(TM.getTargetTriple(), Fn, MF->getMMI()); + // Replace forward-declared registers with the registers containing + // the desired value. + for (DenseMap<unsigned, unsigned>::iterator + I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); + I != E; ++I) { + unsigned From = I->first; + unsigned To = I->second; + // If To is also scheduled to be replaced, find what its ultimate + // replacement is. + while (true) { + DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); + if (J == E) break; + To = J->second; + } + // Make sure the new register has a sufficiently constrained register class. + if (TargetRegisterInfo::isVirtualRegister(From) && + TargetRegisterInfo::isVirtualRegister(To)) + MRI.constrainRegClass(To, MRI.getRegClass(From)); + // Replace it. + + + // Replacing one register with another won't touch the kill flags. + // We need to conservatively clear the kill flags as a kill on the old + // register might dominate existing uses of the new register. + if (!MRI.use_empty(To)) + MRI.clearKillFlags(From); + MRI.replaceRegWith(From, To); + } + TLI->finalizeLowering(*MF); // Release function-specific state. SDB and CurDAG are already cleared diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 4dbcd265d0a..98b4742be1c 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -815,6 +815,13 @@ bool TargetPassConfig::addCoreISelPasses() { } else if (addInstSelector()) return true; + // Expand pseudo-instructions emitted by ISel. Don't run the verifier before + // FinalizeISel. + addPass(&FinalizeISelID); + + // Print the instruction selected machine code... + printAndVerify("After Instruction Selection"); + return false; } @@ -874,12 +881,6 @@ void TargetPassConfig::addMachinePasses() { } } - // Print the instruction selected machine code... - printAndVerify("After Instruction Selection"); - - // Expand pseudo-instructions emitted by ISel. - addPass(&ExpandISelPseudosID); - // Add passes that optimize machine instructions in SSA form. if (getOptLevel() != CodeGenOpt::None) { addMachineSSAOptimization(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 9a8aea2edf0..b10f53cfbc4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -752,7 +752,8 @@ bool AMDGPUPassConfig::addPreISel() { } bool AMDGPUPassConfig::addInstSelector() { - addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel())); + // Defer the verifier until FinalizeISel. + addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false); return false; } diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5ba510d1a33..473cdbb575c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23385,7 +23385,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget, MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); MFI.setHasCopyImplyingStackAdjustment(true); // Don't do anything here, we will expand these intrinsics out later - // during ExpandISelPseudos in EmitInstrWithCustomInserter. + // during FinalizeISel in EmitInstrWithCustomInserter. return SDValue(); } case Intrinsic::x86_lwpins32: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option-fastisel.ll b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option-fastisel.ll index 73158f54325..401523c60ff 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option-fastisel.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option-fastisel.ll @@ -25,7 +25,7 @@ ; DISABLED-NOT: IRTranslator ; DISABLED: AArch64 Instruction Selection -; DISABLED: Expand ISel Pseudo-instructions +; DISABLED: Finalize ISel and expand pseudo-instructions ; FASTISEL: Enabling fast-isel ; NOFASTISEL-NOT: Enabling fast-isel diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll index a044b3492f4..54361eab689 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll @@ -62,7 +62,7 @@ ; DISABLED-NOT: IRTranslator ; DISABLED: AArch64 Instruction Selection -; DISABLED: Expand ISel Pseudo-instructions +; DISABLED: Finalize ISel and expand pseudo-instructions define void @empty() { ret void diff --git a/llvm/test/CodeGen/AArch64/O0-pipeline.ll b/llvm/test/CodeGen/AArch64/O0-pipeline.ll index aa9b1d0c0f7..b25d4e94e3e 100644 --- a/llvm/test/CodeGen/AArch64/O0-pipeline.ll +++ b/llvm/test/CodeGen/AArch64/O0-pipeline.ll @@ -42,7 +42,7 @@ ; CHECK-NEXT: InstructionSelect ; CHECK-NEXT: ResetMachineFunction ; CHECK-NEXT: AArch64 Instruction Selection -; CHECK-NEXT: Expand ISel Pseudo-instructions +; CHECK-NEXT: Finalize ISel and expand pseudo-instructions ; CHECK-NEXT: Local Stack Slot Allocation ; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Two-Address instruction pass diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll index 98cef01b6a9..03815481ef5 100644 --- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll +++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll @@ -76,7 +76,7 @@ ; CHECK-NEXT: AArch64 Instruction Selection ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: AArch64 Local Dynamic TLS Access Clean-up -; CHECK-NEXT: Expand ISel Pseudo-instructions +; CHECK-NEXT: Finalize ISel and expand pseudo-instructions ; CHECK-NEXT: Early Tail Duplication ; CHECK-NEXT: Optimize machine instruction PHIs ; CHECK-NEXT: Slot index numbering diff --git a/llvm/test/CodeGen/AArch64/apple-latest-cpu.ll b/llvm/test/CodeGen/AArch64/apple-latest-cpu.ll index 033c3772af0..2773aeb7ad3 100644 --- a/llvm/test/CodeGen/AArch64/apple-latest-cpu.ll +++ b/llvm/test/CodeGen/AArch64/apple-latest-cpu.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=arm64-apple-ios -mcpu=apple-latest -stop-before=expand-isel-pseudos -o - 2>&1 < %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-ios -mcpu=apple-latest -stop-before=finalize-isel -o - 2>&1 < %s | FileCheck %s ; CHECK-LABEL: @dummy ; CHECK: "target-cpu"="apple-latest" diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-rem.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel-rem.ll index 635e6b92542..1c245a3bb9a 100644 --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-rem.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-rem.ll @@ -1,5 +1,5 @@ ; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s -; RUN: llc %s -O0 -fast-isel -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t +; RUN: llc %s -O0 -fast-isel -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-after=finalize-isel -o /dev/null 2> %t ; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA ; CHECK-SSA-LABEL: Machine code for function t1 diff --git a/llvm/test/CodeGen/AArch64/fast-isel-dbg.ll b/llvm/test/CodeGen/AArch64/fast-isel-dbg.ll index 4d26b9142af..602d454044d 100644 --- a/llvm/test/CodeGen/AArch64/fast-isel-dbg.ll +++ b/llvm/test/CodeGen/AArch64/fast-isel-dbg.ll @@ -1,4 +1,4 @@ -; RUN: llc -o - %s -fast-isel -stop-before=expand-isel-pseudos | FileCheck %s +; RUN: llc -o - %s -fast-isel -stop-before=finalize-isel | FileCheck %s ; Make sure fast-isel produces DBG_VALUE instructions even if no debug printer ; is scheduled because of -stop-before. target triple="aarch64--" diff --git a/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll b/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll index 1617d13f7e1..c38fb7b8c75 100644 --- a/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll +++ b/llvm/test/CodeGen/AArch64/tail-call-unused-zext.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=arm64--- -stop-after=expand-isel-pseudos -o - %s | FileCheck %s +; RUN: llc -mtriple=arm64--- -stop-after=finalize-isel -o - %s | FileCheck %s ; Check that we ignore the zeroext attribute on the return type of the tail ; call, since the return value is unused. This happens during CodeGenPrepare in diff --git a/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll b/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll index f3cd607d779..927a0d9daab 100644 --- a/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll +++ b/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll @@ -1,4 +1,4 @@ -; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos | FileCheck %s +; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after finalize-isel | FileCheck %s ; This test verifies that the instruction selection will add the implicit ; register operands in the correct order when modifying the opcode of an ; instruction to V_ADD_I32_e32. diff --git a/llvm/test/CodeGen/ARM/GlobalISel/pr35375.ll b/llvm/test/CodeGen/ARM/GlobalISel/pr35375.ll index ebef54542bc..6147646df95 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/pr35375.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/pr35375.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple armv7-- -stop-before=expand-isel-pseudos < %s -; RUN: llc -O0 -mtriple armv7-- -stop-before=expand-isel-pseudos -global-isel < %s +; RUN: llc -O0 -mtriple armv7-- -stop-before=finalize-isel < %s +; RUN: llc -O0 -mtriple armv7-- -stop-before=finalize-isel -global-isel < %s ; CHECK: PKHBT diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll index f9a4e712450..e3eab216bd5 100644 --- a/llvm/test/CodeGen/ARM/O3-pipeline.ll +++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll @@ -58,7 +58,7 @@ ; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Branch Probability Analysis ; CHECK-NEXT: ARM Instruction Selection -; CHECK-NEXT: Expand ISel Pseudo-instructions +; CHECK-NEXT: Finalize ISel and expand pseudo-instructions ; CHECK-NEXT: Early Tail Duplication ; CHECK-NEXT: Optimize machine instruction PHIs ; CHECK-NEXT: Slot index numbering diff --git a/llvm/test/CodeGen/ARM/Windows/dbzchk.ll b/llvm/test/CodeGen/ARM/Windows/dbzchk.ll index 324808cb0bf..365951080d4 100644 --- a/llvm/test/CodeGen/ARM/Windows/dbzchk.ll +++ b/llvm/test/CodeGen/ARM/Windows/dbzchk.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV +; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV ; int f(int n, int d) { ; if (n / d) @@ -40,7 +40,7 @@ return: ; CHECK-DIV-DAG: successors: %bb.3 ; CHECK-DIV-DAG: %bb.3 -; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD +; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD ; int r; ; int g(int l, int m) { @@ -74,7 +74,7 @@ return: ; CHECK-MOD-DAG: successors: %bb.2 ; CHECK-MOD-DAG: %bb.2 -; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG +; RUN: llc -mtriple thumbv7--windows-itanium -print-after=finalize-isel -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG ; RUN: llc -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM ; unsigned c; diff --git a/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll b/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll index 1dabb880d61..88af4475bfb 100644 --- a/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll +++ b/llvm/test/CodeGen/ARM/Windows/vla-cpsr.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-machineinstrs=expand-isel-pseudos 2>&1 | FileCheck %s +; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o /dev/null %s -print-after=finalize-isel 2>&1 | FileCheck %s declare arm_aapcs_vfpcc void @g(i8*) local_unnamed_addr diff --git a/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll b/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll index a57506872f9..d6b72a2f0af 100644 --- a/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll +++ b/llvm/test/CodeGen/ARM/copy-by-struct-i32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=armv7-unknown-linux < %s -stop-before=expand-isel-pseudos | FileCheck --check-prefix=BEFORE-EXPAND %s +; RUN: llc -mtriple=armv7-unknown-linux < %s -stop-before=finalize-isel | FileCheck --check-prefix=BEFORE-EXPAND %s ; RUN: llc -mtriple=armv7-unknown-linux < %s | FileCheck --check-prefix=ASSEMBLY %s ; Check COPY_STRUCT_BYVAL_I32 has CPSR as operand. diff --git a/llvm/test/CodeGen/Generic/MachineBranchProb.ll b/llvm/test/CodeGen/Generic/MachineBranchProb.ll index 441652110f2..afe454a62e3 100644 --- a/llvm/test/CodeGen/Generic/MachineBranchProb.ll +++ b/llvm/test/CodeGen/Generic/MachineBranchProb.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s +; RUN: llc < %s -print-after=finalize-isel -o /dev/null 2>&1 | FileCheck %s ; Hexagon runs passes that renumber the basic blocks, causing this test ; to fail. diff --git a/llvm/test/CodeGen/Hexagon/call-v4.ll b/llvm/test/CodeGen/Hexagon/call-v4.ll index ad42bb5eab6..045aa23d2e9 100644 --- a/llvm/test/CodeGen/Hexagon/call-v4.ll +++ b/llvm/test/CodeGen/Hexagon/call-v4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 < %s | FileCheck %s +; RUN: llc -march=hexagon -print-after=finalize-isel -o /dev/null 2>&1 < %s | FileCheck %s ; REQUIRES: asserts ; CHECK: J2_call @f1 diff --git a/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir b/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir index 324678b47aa..b1913149df0 100644 --- a/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir +++ b/llvm/test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir @@ -2,7 +2,7 @@ # RUN: -verify-machineinstrs %s -o - | FileCheck %s # # RUN: llc -mtriple aarch64-- -global-isel=true -global-isel-abort=2 \ -# RUN: -start-after=regbankselect -stop-before=expand-isel-pseudos \ +# RUN: -start-after=regbankselect -stop-before=finalize-isel \ # RUN: -simplify-mir -verify-machineinstrs %s -o - 2>&1 \ # RUN: | FileCheck %s --check-prefix=FALLBACK diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll index 8ff09bbd237..fcbe4318204 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after expand-isel-pseudos -o %t.mir %s +; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s ; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s ; Test that SIMachineFunctionInfo can be round trip serialized through diff --git a/llvm/test/CodeGen/MIR/Generic/multiRunPass.mir b/llvm/test/CodeGen/MIR/Generic/multiRunPass.mir index e055c44205b..97113d43a79 100644 --- a/llvm/test/CodeGen/MIR/Generic/multiRunPass.mir +++ b/llvm/test/CodeGen/MIR/Generic/multiRunPass.mir @@ -1,15 +1,15 @@ -# RUN: llc -run-pass expand-isel-pseudos -run-pass peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE -# RUN: llc -run-pass expand-isel-pseudos,peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE -# RUN: llc -run-pass peephole-opt -run-pass expand-isel-pseudos -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO -# RUN: llc -run-pass peephole-opt,expand-isel-pseudos -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO +# RUN: llc -run-pass finalize-isel -run-pass peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE +# RUN: llc -run-pass finalize-isel,peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE +# RUN: llc -run-pass peephole-opt -run-pass finalize-isel -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO +# RUN: llc -run-pass peephole-opt,finalize-isel -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO # REQUIRES: asserts # This test ensures that the command line accepts # several run passes on the same command line and # actually create the proper pipeline for it. -# PSEUDO_PEEPHOLE: -expand-isel-pseudos +# PSEUDO_PEEPHOLE: -finalize-isel # PSEUDO_PEEPHOLE-SAME: {{(-machineverifier )?}}-peephole-opt -# PEEPHOLE_PSEUDO: -peephole-opt {{(-machineverifier )?}}-expand-isel-pseudos +# PEEPHOLE_PSEUDO: -peephole-opt {{(-machineverifier )?}}-finalize-isel # Make sure there are no other passes happening after what we asked. # CHECK-NEXT: --- | diff --git a/llvm/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll b/llvm/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll index 7847fc89371..8f354c11b7b 100644 --- a/llvm/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll +++ b/llvm/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll @@ -1,16 +1,16 @@ ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ ; RUN: -mcpu=mips32 -mattr=+fpxx \ -; RUN: -stop-after=expand-isel-pseudos | \ +; RUN: -stop-after=finalize-isel | \ ; RUN: FileCheck %s -check-prefix=FPXX-IMPLICIT-SP ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ ; RUN: -mcpu=mips32r6 -mattr=+fp64,+nooddspreg \ -; RUN: -stop-after=expand-isel-pseudos | \ +; RUN: -stop-after=finalize-isel | \ ; RUN: FileCheck %s -check-prefix=FP64-IMPLICIT-SP ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ ; RUN: -mcpu=mips32r2 -mattr=+fpxx \ -; RUN: -stop-after=expand-isel-pseudos | \ +; RUN: -stop-after=finalize-isel | \ ; RUN: FileCheck %s -check-prefix=NO-IMPLICIT-SP define double @foo2(i32 signext %v1, double %d1) { diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir index 9298d9418da..92e26186f45 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir @@ -1,5 +1,5 @@ # RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ -# RUN: -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir index 42ce1236253..38a5fb4ee26 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir @@ -1,5 +1,5 @@ # RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ -# RUN: -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir index d9d7f9a777f..3db06f70a9d 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dext-size.mir b/llvm/test/CodeGen/Mips/instverify/dext-size.mir index f20677d9ec4..c66050ae159 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir index a25f25e42e2..14b9da27821 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir index 3f9c2bdff3f..e8ca6179257 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir index 823519f3e55..1136281a633 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir index e62904ce5f8..f70f3fe8764 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir index ed0a8747a8b..2f01b5ad534 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir index f1d038739d5..da6444914b0 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-size-valid.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK-NOT: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir index 927862ed394..2958c5d272d 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir index c2f1b89bec8..e4cfd7c21d7 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir index 6203b87bb21..05aaf2d2fd5 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-size.mir index d69136ca4e2..2227d6f8043 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir index 7cc6c2e1aef..0b8399724bd 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir index 54c55cee97e..6f92d790c53 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir index fd18417591a..e7872360cb7 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir index 015380951d0..503199c50ad 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir index b9b88a9fd42..2a81501d24a 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir index 99aee894815..198bd09d75f 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir index c10fe557608..b2f1cf02454 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir index 39a81a6b58b..69f817258a3 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-size.mir index ad6653ca8cb..460956ab46b 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir index f8266f0f571..b6202f5b3a9 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir index eeac163a215..3b7fd0699c0 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-size.mir index 6beb781df3b..0e17e20eed8 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/micromips-eva.mir b/llvm/test/CodeGen/Mips/micromips-eva.mir index ba30a293e61..7f0ae721b36 100644 --- a/llvm/test/CodeGen/Mips/micromips-eva.mir +++ b/llvm/test/CodeGen/Mips/micromips-eva.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \ +# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \ # RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s --- | diff --git a/llvm/test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll b/llvm/test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll index df592c49cc6..54302fb662e 100644 --- a/llvm/test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll +++ b/llvm/test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips -stop-after=expand-isel-pseudos < %s | FileCheck %s +; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips -stop-after=finalize-isel < %s | FileCheck %s ; CHECK: JAL_MM ; CHECK-NOT: JALR16_MM diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir index 53c5910b0da..dfc5bffb7ae 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir @@ -1,5 +1,5 @@ -# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \ -# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic -mxgot \ +# RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \ +# RUN: -stop-after=finalize-isel -relocation-model=pic -mxgot \ # RUN: -o /dev/null %s # A simple test to show that we can parse the target specific flags: gpoff-hi, diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir index a8e1191abcb..a34efa9fdfd 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir @@ -1,5 +1,5 @@ -# RUN: llc -march=mips -start-before=expand-isel-pseudos \ -# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic \ +# RUN: llc -march=mips -start-before=finalize-isel \ +# RUN: -stop-after=finalize-isel -relocation-model=pic \ # RUN: -o /dev/null %s # A simple test to show that we can parse the target specific flags: got-call, diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir index 2c3a450f2da..5ec96c411fb 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-pic.mir @@ -1,5 +1,5 @@ -# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \ -# RUN: -stop-after=expand-isel-pseudos -relocation-model=pic \ +# RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \ +# RUN: -stop-after=finalize-isel -relocation-model=pic \ # RUN: -o /dev/null %s # A simple test to show that we can parse the target specific flags: gpoff-hi, diff --git a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir index ebe11837f56..5630926aadf 100644 --- a/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir +++ b/llvm/test/CodeGen/Mips/mirparser/target-flags-static-tls.mir @@ -1,5 +1,5 @@ -# RUN: llc -march=mips64 -target-abi n64 -start-before=expand-isel-pseudos \ -# RUN: -stop-after=expand-isel-pseudos -relocation-model=static -o /dev/null %s +# RUN: llc -march=mips64 -target-abi n64 -start-before=finalize-isel \ +# RUN: -stop-after=finalize-isel -relocation-model=static -o /dev/null %s # A simple test to show that we can parse the target specific flags: highest, # higher, hi, lo, tprel-lo, tprel-hi, gpoff-hi, gpoff-lo, gottprel. diff --git a/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir index 438a7e1d0e4..f21f148f587 100644 --- a/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir +++ b/llvm/test/CodeGen/Mips/unaligned-memops-mapping.mir @@ -1,4 +1,4 @@ -# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=expand-isel-pseudos \ +# RUN: llc -O0 -march=mips -mcpu=mips32r3 -mattr=+micromips,+eva -start-after=finalize-isel \ # RUN: -filetype obj %s -o - | llvm-objdump -mattr=+eva -d - | FileCheck %s # Test that MIPS unaligned load/store instructions can be mapped to their diff --git a/llvm/test/CodeGen/Mips/unaligned-memops.ll b/llvm/test/CodeGen/Mips/unaligned-memops.ll index af290a7bcf0..a9595fea71b 100644 --- a/llvm/test/CodeGen/Mips/unaligned-memops.ll +++ b/llvm/test/CodeGen/Mips/unaligned-memops.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MIPS -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=expand-isel-pseudos < %s | FileCheck %s --check-prefix=MICROMIPS +; RUN: llc -march=mips -mcpu=mips32r2 -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MIPS +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -stop-before=finalize-isel < %s | FileCheck %s --check-prefix=MICROMIPS ; Test that the correct ISA version of the unaligned memory operations is ; selected up front. diff --git a/llvm/test/CodeGen/PowerPC/debuginfo-split-int.ll b/llvm/test/CodeGen/PowerPC/debuginfo-split-int.ll index e12d5e5d220..922727ff1bf 100644 --- a/llvm/test/CodeGen/PowerPC/debuginfo-split-int.ll +++ b/llvm/test/CodeGen/PowerPC/debuginfo-split-int.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -stop-before=expand-isel-pseudos -o - | FileCheck %s +; RUN: llc < %s -stop-before=finalize-isel -o - | FileCheck %s source_filename = "foo.c" target datalayout = "E-m:e-p:32:32-i64:64-n32" diff --git a/llvm/test/CodeGen/SystemZ/cc-liveness.ll b/llvm/test/CodeGen/SystemZ/cc-liveness.ll index e4cbb15ea6e..f1bb582ede4 100644 --- a/llvm/test/CodeGen/SystemZ/cc-liveness.ll +++ b/llvm/test/CodeGen/SystemZ/cc-liveness.ll @@ -2,7 +2,7 @@ ; not be placed betwen two compare and load-on-condition instructions. ; ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -pre-RA-sched=list-ilp \ -; RUN: -print-after=expand-isel-pseudos 2>&1 | FileCheck %s +; RUN: -print-after=finalize-isel 2>&1 | FileCheck %s ; ; CHECK-LABEL: bb.0.bb: ; CHECK: CLI diff --git a/llvm/test/CodeGen/SystemZ/debuginstr-02.mir b/llvm/test/CodeGen/SystemZ/debuginstr-02.mir index 459b7bb9d16..1a209496d03 100644 --- a/llvm/test/CodeGen/SystemZ/debuginstr-02.mir +++ b/llvm/test/CodeGen/SystemZ/debuginstr-02.mir @@ -2,7 +2,7 @@ # the presence of DEBUG_VALUE machine instructions. # # RUN: llc %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \ -# RUN: -start-before=expand-isel-pseudos -o - 2>&1 | FileCheck %s +# RUN: -start-before=finalize-isel -o - 2>&1 | FileCheck %s # # CHECK-LABEL: %bb.1: # CHECK: ldr diff --git a/llvm/test/CodeGen/X86/MachineBranchProb.ll b/llvm/test/CodeGen/X86/MachineBranchProb.ll index 7b84740ef70..4a84feeaec0 100644 --- a/llvm/test/CodeGen/X86/MachineBranchProb.ll +++ b/llvm/test/CodeGen/X86/MachineBranchProb.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -print-after=finalize-isel -o /dev/null 2>&1 | FileCheck %s ;; Make sure a transformation in SelectionDAGBuilder that converts "or + br" to ;; two branches correctly updates the branch probability. diff --git a/llvm/test/CodeGen/X86/O0-pipeline.ll b/llvm/test/CodeGen/X86/O0-pipeline.ll index c1e03ff4b33..271aec5fa05 100644 --- a/llvm/test/CodeGen/X86/O0-pipeline.ll +++ b/llvm/test/CodeGen/X86/O0-pipeline.ll @@ -38,7 +38,7 @@ ; CHECK-NEXT: Module Verifier ; CHECK-NEXT: X86 DAG->DAG Instruction Selection ; CHECK-NEXT: X86 PIC Global Base Reg Initialization -; CHECK-NEXT: Expand ISel Pseudo-instructions +; CHECK-NEXT: Finalize ISel and expand pseudo-instructions ; CHECK-NEXT: Local Stack Slot Allocation ; CHECK-NEXT: X86 speculative load hardening ; CHECK-NEXT: MachineDominator Tree Construction diff --git a/llvm/test/CodeGen/X86/O3-pipeline.ll b/llvm/test/CodeGen/X86/O3-pipeline.ll index 175640a00e3..7364d950f45 100644 --- a/llvm/test/CodeGen/X86/O3-pipeline.ll +++ b/llvm/test/CodeGen/X86/O3-pipeline.ll @@ -67,7 +67,7 @@ ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: Local Dynamic TLS Access Clean-up ; CHECK-NEXT: X86 PIC Global Base Reg Initialization -; CHECK-NEXT: Expand ISel Pseudo-instructions +; CHECK-NEXT: Finalize ISel and expand pseudo-instructions ; CHECK-NEXT: X86 Domain Reassignment Pass ; CHECK-NEXT: Early Tail Duplication ; CHECK-NEXT: Optimize machine instruction PHIs diff --git a/llvm/test/CodeGen/X86/catchpad-weight.ll b/llvm/test/CodeGen/X86/catchpad-weight.ll index ca4b97a7b00..116f2852d3a 100644 --- a/llvm/test/CodeGen/X86/catchpad-weight.ll +++ b/llvm/test/CodeGen/X86/catchpad-weight.ll @@ -1,4 +1,4 @@ -; RUN: llc -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s +; RUN: llc -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s ; Check if the edge weight to the catchpad is calculated correctly. diff --git a/llvm/test/CodeGen/X86/fast-isel-fneg-kill.ll b/llvm/test/CodeGen/X86/fast-isel-fneg-kill.ll index f0b7aa48c34..d75f421f7ec 100644 --- a/llvm/test/CodeGen/X86/fast-isel-fneg-kill.ll +++ b/llvm/test/CodeGen/X86/fast-isel-fneg-kill.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 -stop-after=expand-isel-pseudos | FileCheck %s +; RUN: llc < %s -fast-isel -fast-isel-abort=3 -mtriple=x86_64-apple-darwin10 -stop-after=finalize-isel | FileCheck %s ; Make sure we output the right kill flag for the xor conversion. diff --git a/llvm/test/CodeGen/X86/fixed-stack-di-mir.ll b/llvm/test/CodeGen/X86/fixed-stack-di-mir.ll index 714a980e6b0..30d18630083 100644 --- a/llvm/test/CodeGen/X86/fixed-stack-di-mir.ll +++ b/llvm/test/CodeGen/X86/fixed-stack-di-mir.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=x86_64-apple-unknown -stop-before=expand-isel-pseudos %s -o - -simplify-mir | FileCheck %s +; RUN: llc -mtriple=x86_64-apple-unknown -stop-before=finalize-isel %s -o - -simplify-mir | FileCheck %s ; The byval argument of the function will be allocated a fixed stack slot. Test ; that we serialize the fixed slot correctly. diff --git a/llvm/test/CodeGen/X86/i16lshr8pat.ll b/llvm/test/CodeGen/X86/i16lshr8pat.ll index 68974b72a88..4ec80c22a65 100644 --- a/llvm/test/CodeGen/X86/i16lshr8pat.ll +++ b/llvm/test/CodeGen/X86/i16lshr8pat.ll @@ -1,4 +1,4 @@ -; RUN: llc -stop-after expand-isel-pseudos < %s 2>&1 | FileCheck %s +; RUN: llc -stop-after finalize-isel < %s 2>&1 | FileCheck %s target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" target triple = "i386-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll b/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll index 56e0855d955..47bbff877c5 100644 --- a/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll +++ b/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=expand-isel-pseudos | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f -stop-after=finalize-isel | FileCheck %s ; CHECK: %[[REG1:.*]]:vr512_0_15 = COPY %1 ; CHECK: %[[REG2:.*]]:vr512_0_15 = COPY %2 diff --git a/llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll b/llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll index 34a77ea5fec..fae8c73cf08 100644 --- a/llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll +++ b/llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i686 -stop-after=expand-isel-pseudos | FileCheck %s +; RUN: llc < %s -mtriple=i686 -stop-after=finalize-isel | FileCheck %s ; CHECK: INLINEASM &"", 1, 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags define void @foo() { diff --git a/llvm/test/CodeGen/X86/pr39896.ll b/llvm/test/CodeGen/X86/pr39896.ll index 210230e3c85..64bc57f7810 100644 --- a/llvm/test/CodeGen/X86/pr39896.ll +++ b/llvm/test/CodeGen/X86/pr39896.ll @@ -1,4 +1,4 @@ -; RUN: llc %s -start-after=codegenprepare -stop-after=expand-isel-pseudos -o - | FileCheck %s +; RUN: llc %s -start-after=codegenprepare -stop-after=finalize-isel -o - | FileCheck %s ; PR39896: When code such as %conv below is dropped by SelectionDAG for having ; no users, don't just drop the dbg.value record associated with it. Instead, diff --git a/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir b/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir index 9601732909b..697e03d5c33 100644 --- a/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir +++ b/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-- -run-pass=expand-isel-pseudos -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64-- -run-pass=finalize-isel -verify-machineinstrs -o - %s | FileCheck %s # Check that we're not copying the kill flags with the operands from the pseudo # instruction. --- | diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll index bbeeb6828ca..6870792321f 100644 --- a/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll +++ b/llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=expand-isel-pseudos 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2,fma -stop-after=finalize-isel 2>&1 | FileCheck %s declare float @llvm.sqrt.f32(float) #0 diff --git a/llvm/test/CodeGen/X86/stack-protector-weight.ll b/llvm/test/CodeGen/X86/stack-protector-weight.ll index 9ec929521d6..38fe2266aac 100644 --- a/llvm/test/CodeGen/X86/stack-protector-weight.ll +++ b/llvm/test/CodeGen/X86/stack-protector-weight.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-SELDAG -; RUN: llc -mtriple=x86_64-apple-darwin -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-IR -; RUN: llc -mtriple=i386-pc-windows-msvc -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-SELDAG -; RUN: llc -mtriple=i386-pc-windows-msvc -print-machineinstrs=expand-isel-pseudos -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-IR +; RUN: llc -mtriple=x86_64-apple-darwin -print-after=finalize-isel -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-SELDAG +; RUN: llc -mtriple=x86_64-apple-darwin -print-after=finalize-isel -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=DARWIN-IR +; RUN: llc -mtriple=i386-pc-windows-msvc -print-after=finalize-isel -enable-selectiondag-sp=true %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-SELDAG +; RUN: llc -mtriple=i386-pc-windows-msvc -print-after=finalize-isel -enable-selectiondag-sp=false %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=MSVC-IR ; DARWIN-SELDAG: # Machine code for function test_branch_weights: ; DARWIN-SELDAG: successors: %bb.[[SUCCESS:[0-9]+]](0x7ffff800), %bb.[[FAILURE:[0-9]+]] diff --git a/llvm/test/CodeGen/X86/switch-edge-weight.ll b/llvm/test/CodeGen/X86/switch-edge-weight.ll index 1a564946423..27db6d7b704 100644 --- a/llvm/test/CodeGen/X86/switch-edge-weight.ll +++ b/llvm/test/CodeGen/X86/switch-edge-weight.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=x86_64-- -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s +; RUN: llc -mtriple=x86_64-- -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s declare void @foo(i32) @@ -276,6 +276,6 @@ sw.epilog: ; CHECK: successors: %bb.8(0x20000001), %bb.9(0x5fffffff) } -!1 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} -!2 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} -!3 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} +!1 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} +!2 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} +!3 = !{!"branch_weights", i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10} diff --git a/llvm/test/CodeGen/X86/switch-jump-table.ll b/llvm/test/CodeGen/X86/switch-jump-table.ll index 4c7937078e8..f557edaa07b 100644 --- a/llvm/test/CodeGen/X86/switch-jump-table.ll +++ b/llvm/test/CodeGen/X86/switch-jump-table.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=i686-pc-gnu-linux < %s | FileCheck %s -; RUN: llc -mtriple=i686-pc-gnu-linux -print-machineinstrs=expand-isel-pseudos %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-JT-PROB +; RUN: llc -mtriple=i686-pc-gnu-linux -print-after=finalize-isel %s -o /dev/null 2>&1 | FileCheck %s -check-prefix=CHECK-JT-PROB ; An unreachable default destination is ignored and no compare and branch diff --git a/llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll b/llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll index 70811b153ce..bdf07aea848 100644 --- a/llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll +++ b/llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=x86_64-linux-gnu -stop-after=expand-isel-pseudos < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-linux-gnu -stop-after=finalize-isel < %s | FileCheck %s define i32 @foo(i32 %n) !prof !1 { entry: diff --git a/llvm/test/CodeGen/X86/vecloadextract.ll b/llvm/test/CodeGen/X86/vecloadextract.ll index 94df350a291..c76e81ddb64 100755 --- a/llvm/test/CodeGen/X86/vecloadextract.ll +++ b/llvm/test/CodeGen/X86/vecloadextract.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -;RUN: llc < %s -mtriple=i686 -mattr=sse4.1 -stop-after=expand-isel-pseudos 2>&1 | FileCheck %s +;RUN: llc < %s -mtriple=i686 -mattr=sse4.1 -stop-after=finalize-isel 2>&1 | FileCheck %s ; This test makes sure we discard pointer info when we combine a vector load ; and a variable extractelement into a scalar load using an index. There's also diff --git a/llvm/test/CodeGen/X86/vmaskmov-offset.ll b/llvm/test/CodeGen/X86/vmaskmov-offset.ll index 41379886141..03fead64bc2 100644 --- a/llvm/test/CodeGen/X86/vmaskmov-offset.ll +++ b/llvm/test/CodeGen/X86/vmaskmov-offset.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 -stop-after expand-isel-pseudos -o - %s | FileCheck %s +; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 -stop-after finalize-isel -o - %s | FileCheck %s declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>) declare <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>) diff --git a/llvm/test/CodeGen/X86/xor-combine-debugloc.ll b/llvm/test/CodeGen/X86/xor-combine-debugloc.ll index 3978378d557..ab4fba703bb 100644 --- a/llvm/test/CodeGen/X86/xor-combine-debugloc.ll +++ b/llvm/test/CodeGen/X86/xor-combine-debugloc.ll @@ -1,4 +1,4 @@ -; RUN: llc -stop-after=expand-isel-pseudos < %s | FileCheck %s +; RUN: llc -stop-after=finalize-isel < %s | FileCheck %s ; ; Make sure that when the entry block of IR below is lowered, an instruction ; that implictly defines $eflags has a same debug location with the icmp diff --git a/llvm/test/DebugInfo/ARM/float-stack-arg.ll b/llvm/test/DebugInfo/ARM/float-stack-arg.ll index d5cce276700..baa2f8b51e8 100644 --- a/llvm/test/DebugInfo/ARM/float-stack-arg.ll +++ b/llvm/test/DebugInfo/ARM/float-stack-arg.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=armv4t-unknown-unknown -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s +; RUN: llc -mtriple=armv4t-unknown-unknown -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s ; Verify that a stack-referencing DBG_VALUE is emitted for p5 at the start of ; the function. diff --git a/llvm/test/DebugInfo/Generic/linear-dbg-value.ll b/llvm/test/DebugInfo/Generic/linear-dbg-value.ll index 2ea78eb3dae..11ac6b0ea9f 100644 --- a/llvm/test/DebugInfo/Generic/linear-dbg-value.ll +++ b/llvm/test/DebugInfo/Generic/linear-dbg-value.ll @@ -1,5 +1,5 @@ ; FIXME: Fix machine verifier issues and remove -verify-machineinstrs=0. PR39452. -; RUN: llc -stop-before=expand-isel-pseudos -pre-RA-sched=linearize -verify-machineinstrs=0 < %s | FileCheck %s +; RUN: llc -stop-before=finalize-isel -pre-RA-sched=linearize -verify-machineinstrs=0 < %s | FileCheck %s source_filename = "linear-dbg-value.ll" ; Function Attrs: nounwind readonly uwtable diff --git a/llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll b/llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll index b5692b80435..8dd53eeda22 100644 --- a/llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll +++ b/llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before=expand-isel-pseudos %s -o - | FileCheck %s +; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before=finalize-isel %s -o - | FileCheck %s ; Test the movement of dbg.values of arguments. SelectionDAG tries to be ; helpful and places DBG_VALUEs of Arguments at the start of functions. diff --git a/llvm/test/DebugInfo/X86/dbg-value-frame-index-2.ll b/llvm/test/DebugInfo/X86/dbg-value-frame-index-2.ll index 3f810dba303..d6cd2e961b2 100644 --- a/llvm/test/DebugInfo/X86/dbg-value-frame-index-2.ll +++ b/llvm/test/DebugInfo/X86/dbg-value-frame-index-2.ll @@ -1,4 +1,4 @@ -; RUN: llc -start-after=codegenprepare -stop-before=expand-isel-pseudos < %s -o - | FileCheck %s +; RUN: llc -start-after=codegenprepare -stop-before=finalize-isel < %s -o - | FileCheck %s ; Test that stack frame dbg.values are lowered to DBG_VALUEs, in blocks that ; are local to the alloca, and elsewhere. Differs from dbg-value-frame-index.ll diff --git a/llvm/test/DebugInfo/X86/dbg-value-funcarg.ll b/llvm/test/DebugInfo/X86/dbg-value-funcarg.ll index 310d85c69b4..e2884ead98c 100644 --- a/llvm/test/DebugInfo/X86/dbg-value-funcarg.ll +++ b/llvm/test/DebugInfo/X86/dbg-value-funcarg.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s ; Input to this test looked like this and was compiled using: clang -g -O1 -mllvm -stop-after=codegenprepare -S ; diff --git a/llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll b/llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll index a55103580b6..83bdcc902a0 100644 --- a/llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll +++ b/llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - %s | FileCheck %s +; RUN: llc -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before=finalize-isel -o - %s | FileCheck %s ; Test case was generated from the following C code, ; using: clang -g -O1 -S -emit-llvm s.c -o s.ll diff --git a/llvm/test/DebugInfo/X86/pr40427.ll b/llvm/test/DebugInfo/X86/pr40427.ll index 8b3a4b2b366..88c12e378a0 100644 --- a/llvm/test/DebugInfo/X86/pr40427.ll +++ b/llvm/test/DebugInfo/X86/pr40427.ll @@ -1,4 +1,4 @@ -; RUN: llc -start-after=codegenprepare -stop-before=expand-isel-pseudos -o - < %s | FileCheck %s +; RUN: llc -start-after=codegenprepare -stop-before=finalize-isel -o - < %s | FileCheck %s ; Test for correct placement of DBG_VALUE, which in PR40427 is placed before ; the load instruction it refers to. The circumstance replicated here is where ; two instructions in a row, trunc and add, begin with no-op Copy{To,From}Reg diff --git a/llvm/test/DebugInfo/X86/safestack-byval.ll b/llvm/test/DebugInfo/X86/safestack-byval.ll index 6e3604d408d..7b300f7726c 100644 --- a/llvm/test/DebugInfo/X86/safestack-byval.ll +++ b/llvm/test/DebugInfo/X86/safestack-byval.ll @@ -1,7 +1,7 @@ ; Test dwarf codegen for DILocalVariable of a byval function argument that ; points to neither an argument nor an alloca. This kind of IR is generated by ; SafeStack for unsafe byval arguments. -; RUN: llc -mtriple=x86_64-unknown-unknown -stop-after expand-isel-pseudos %s -o - | FileCheck %s +; RUN: llc -mtriple=x86_64-unknown-unknown -stop-after finalize-isel %s -o - | FileCheck %s ; This was built by compiling the following source with SafeStack and ; simplifying the result a little. diff --git a/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll b/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll index 34c97f7a4c0..95b9e524665 100644 --- a/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll +++ b/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll @@ -1,4 +1,4 @@ -; RUN: llc %s -stop-before expand-isel-pseudos -o - | FileCheck %s +; RUN: llc %s -stop-before finalize-isel -o - | FileCheck %s ;-------------------------------------------------------------------- ; This test case is basically generated from the following C code. diff --git a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll index 116e05746f3..360335fcee1 100644 --- a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll +++ b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s +; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s ; This test case was generated from the following debug.c program, ; using: clang debug.c -g -O1 -S -o dbg_value_phi_isel1.ll -emit-llvm diff --git a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll index e68a69d62e8..44f4d0be63b 100644 --- a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll +++ b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll @@ -1,4 +1,4 @@ -; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s +; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s ; This test case is a modified version of dbg_value_phi_isel1.ll ; where the llvm.dbg.value nodes in for.body has been moved. diff --git a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll index 4aa7243c9e9..9d746645ced 100644 --- a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll +++ b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll @@ -1,4 +1,4 @@ -; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s +; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s ; This test case was generated from the following phi-split.c program, ; using: clang phi-split.c -g -O1 -S -o - --target=i386 -emit-llvm diff --git a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll index 23674ee32cc..491f9d25d63 100644 --- a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll +++ b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll @@ -1,4 +1,4 @@ -; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s +; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s ; This is a reproducer based on the test case from PR37321. diff --git a/llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll b/llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll index dd9fac64c02..a7810c9d130 100644 --- a/llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll +++ b/llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll @@ -1,4 +1,4 @@ -; RUN: llc -start-after=codegenprepare -stop-before expand-isel-pseudos -o - %s | FileCheck %s +; RUN: llc -start-after=codegenprepare -stop-before finalize-isel -o - %s | FileCheck %s ; Test that dbg.values of an SSA variable that's not used in a basic block, ; is converted to a DBG_VALUE in that same basic block. We know that %1 is diff --git a/llvm/test/DebugInfo/X86/sdag-ir-salvage.ll b/llvm/test/DebugInfo/X86/sdag-ir-salvage.ll index 0bd5f18dd17..04754d77563 100644 --- a/llvm/test/DebugInfo/X86/sdag-ir-salvage.ll +++ b/llvm/test/DebugInfo/X86/sdag-ir-salvage.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before expand-isel-pseudos %s -o - | FileCheck %s +; RUN: llc -mtriple=x86_64-unknown-unknown -start-after=codegenprepare -stop-before finalize-isel %s -o - | FileCheck %s ; Test that the dbg.value for %baz, which doesn't exist in the 'next' bb, ; can be salvaged back to the underlying argument vreg. |
