diff options
| -rw-r--r-- | llvm/include/llvm/IR/IntrinsicsHexagon.td | 26 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonIntrinsics.td | 12 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll | 76 |
4 files changed, 98 insertions, 20 deletions
diff --git a/llvm/include/llvm/IR/IntrinsicsHexagon.td b/llvm/include/llvm/IR/IntrinsicsHexagon.td index 8ac56e03be6..09824534472 100644 --- a/llvm/include/llvm/IR/IntrinsicsHexagon.td +++ b/llvm/include/llvm/IR/IntrinsicsHexagon.td @@ -32,16 +32,6 @@ class Hexagon_qi_mem_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, [llvm_i1_ty], [llvm_ptr_ty], [IntrNoMem]>; - -// -// DEF_FUNCTION_TYPE_1(void_ftype_SI,BT_VOID,BT_INT) -> -// Hexagon_void_si_Intrinsic<string GCCIntSuffix> -// -class Hexagon_void_si_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_ptr_ty], - []>; - // // DEF_FUNCTION_TYPE_1(HI_ftype_SI,BT_I16,BT_INT) -> // Hexagon_hi_si_Intrinsic<string GCCIntSuffix> @@ -4959,11 +4949,25 @@ Hexagon_di_di_Intrinsic<"HEXAGON_S2_interleave">; // def int_hexagon_S2_deinterleave : Hexagon_di_di_Intrinsic<"HEXAGON_S2_deinterleave">; + // // BUILTIN_INFO(HEXAGON.dcfetch_A,v_ftype_DI*,1) // def int_hexagon_prefetch : -Hexagon_void_si_Intrinsic<"HEXAGON_prefetch">; +Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>; +def int_hexagon_Y2_dccleana : +Hexagon_Intrinsic<"HEXAGON_Y2_dccleana", [], [llvm_ptr_ty], []>; +def int_hexagon_Y2_dccleaninva : +Hexagon_Intrinsic<"HEXAGON_Y2_dccleaninva", [], [llvm_ptr_ty], []>; +def int_hexagon_Y2_dcinva : +Hexagon_Intrinsic<"HEXAGON_Y2_dcinva", [], [llvm_ptr_ty], []>; +def int_hexagon_Y2_dczeroa : +Hexagon_Intrinsic<"HEXAGON_Y2_dczeroa", [], [llvm_ptr_ty], + [IntrWriteMem, IntrArgMemOnly, IntrHasSideEffects]>; +def int_hexagon_Y4_l2fetch : +Hexagon_Intrinsic<"HEXAGON_Y4_l2fetch", [], [llvm_ptr_ty, llvm_i32_ty], []>; +def int_hexagon_Y5_l2fetch : +Hexagon_Intrinsic<"HEXAGON_Y5_l2fetch", [], [llvm_ptr_ty, llvm_i64_ty], []>; def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>; def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>; diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td index 2dc74632e9b..30ebf89c980 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -45863,6 +45863,7 @@ tc_30665cb0, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000000; let isSoloAin1 = 1; +let hasSideEffects = 1; } def Y2_dccleaninva : HInst< (outs), @@ -45872,6 +45873,7 @@ tc_30665cb0, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000010; let isSoloAin1 = 1; +let hasSideEffects = 1; } def Y2_dcfetch : HInst< (outs), @@ -45900,6 +45902,7 @@ tc_30665cb0, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000001; let isSoloAin1 = 1; +let hasSideEffects = 1; } def Y2_dczeroa : HInst< (outs), @@ -45909,6 +45912,7 @@ tc_30665cb0, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000110; let isSoloAin1 = 1; +let hasSideEffects = 1; let mayStore = 1; } def Y2_icinva : HInst< diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td index c611857ec26..104a28654dd 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td @@ -1366,6 +1366,18 @@ defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vmaskedstorenq>; defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vmaskedstorentq>; defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vmaskedstorentnq>; +//******************************************************************* +// SYSTEM +//******************************************************************* + +def: T_R_pat<Y2_dccleana, int_hexagon_Y2_dccleana>; +def: T_R_pat<Y2_dccleaninva, int_hexagon_Y2_dccleaninva>; +def: T_R_pat<Y2_dcinva, int_hexagon_Y2_dcinva>; +def: T_R_pat<Y2_dczeroa, int_hexagon_Y2_dczeroa>; + +def: T_RR_pat<Y4_l2fetch, int_hexagon_Y4_l2fetch>; +def: T_RP_pat<Y5_l2fetch, int_hexagon_Y5_l2fetch>; + include "HexagonIntrinsicsV3.td" include "HexagonIntrinsicsV4.td" include "HexagonIntrinsicsV5.td" diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll b/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll index ac4c53e221d..23473c92da9 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll @@ -1,13 +1,71 @@ -; RUN: llc -march=hexagon -O0 < %s | FileCheck %s -; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s -; Hexagon Programmer's Reference Manual 11.9.1 SYSTEM/USER +; RUN: llc -march=hexagon < %s | FileCheck %s -; CHECK-CALL-NOT: call +target triple = "hexagon" -; Data cache prefetch -declare void @llvm.hexagon.prefetch(i8*) -define void @prefetch(i8* %a) { - call void @llvm.hexagon.prefetch(i8* %a) +; CHECK-LABEL: dc00: +; CHECK: dcfetch +define void @dc00(i8* nocapture readonly %p) local_unnamed_addr #0 { + tail call void @llvm.hexagon.prefetch(i8* %p) ret void } -; CHECK: dcfetch({{.*}}+#0) + +; CHECK-LABEL: dc01: +; CHECK: dccleana +define void @dc01(i8* nocapture readonly %p) local_unnamed_addr #0 { +entry: + tail call void @llvm.hexagon.Y2.dccleana(i8* %p) + ret void +} + +; CHECK-LABEL: dc02: +; CHECK: dccleaninva +define void @dc02(i8* nocapture readonly %p) local_unnamed_addr #0 { +entry: + tail call void @llvm.hexagon.Y2.dccleaninva(i8* %p) + ret void +} + +; CHECK-LABEL: dc03: +; CHECK: dcinva +define void @dc03(i8* nocapture readonly %p) local_unnamed_addr #0 { +entry: + tail call void @llvm.hexagon.Y2.dcinva(i8* %p) + ret void +} + +; CHECK-LABEL: dc04: +; CHECK: dczeroa +define void @dc04(i8* nocapture %p) local_unnamed_addr #0 { +entry: + tail call void @llvm.hexagon.Y2.dczeroa(i8* %p) + ret void +} + +; CHECK-LABEL: dc05: +; CHECK: l2fetch(r{{[0-9]+}},r{{[0-9]+}}) +define void @dc05(i8* nocapture readonly %p, i32 %q) local_unnamed_addr #0 { +entry: + tail call void @llvm.hexagon.Y4.l2fetch(i8* %p, i32 %q) + ret void +} + +; CHECK-LABEL: dc06: +; CHECK: l2fetch(r{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}}) +define void @dc06(i8* nocapture readonly %p, i64 %q) local_unnamed_addr #0 { +entry: + tail call void @llvm.hexagon.Y5.l2fetch(i8* %p, i64 %q) + ret void +} + +declare void @llvm.hexagon.prefetch(i8* nocapture) #1 +declare void @llvm.hexagon.Y2.dccleana(i8* nocapture readonly) #2 +declare void @llvm.hexagon.Y2.dccleaninva(i8* nocapture readonly) #2 +declare void @llvm.hexagon.Y2.dcinva(i8* nocapture readonly) #2 +declare void @llvm.hexagon.Y2.dczeroa(i8* nocapture) #3 +declare void @llvm.hexagon.Y4.l2fetch(i8* nocapture readonly, i32) #2 +declare void @llvm.hexagon.Y5.l2fetch(i8* nocapture readonly, i64) #2 + +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #1 = { inaccessiblemem_or_argmemonly nounwind } +attributes #2 = { nounwind } +attributes #3 = { argmemonly nounwind writeonly } |
