diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 4ec4be9bc48..e3b179c5caf 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -1095,6 +1095,7 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { case 106: return createRegOperand(VCC); case 108: return createRegOperand(TBA); case 110: return createRegOperand(TMA); + case 125: return createRegOperand(SGPR_NULL); case 126: return createRegOperand(EXEC); case 235: return createRegOperand(SRC_SHARED_BASE); case 236: return createRegOperand(SRC_SHARED_LIMIT); diff --git a/llvm/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt b/llvm/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt new file mode 100644 index 00000000000..adeb47aa9d4 --- /dev/null +++ b/llvm/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX10 + +# GFX10: s_ashr_i64 s[0:1], null, s0 ; encoding: [0x7d,0x00,0x80,0x91] +0x7d,0x00,0x80,0x91 + +# GFX10: s_and_b64 s[0:1], null, null ; encoding: [0x7d,0x7d,0x80,0x87] +0x7d,0x7d,0x80,0x87 |
